AMD went from 64kb in Zen 1 down to 32kb in Zen 2/3. Bigger isn't always better. It only matters if the architecture can actually use the cache effectively.
M1 has a massive reorder buffer, so it needs and can use more L1 cache. It's pretty much that simple.
It's more complicated on x86 because of the 4k page size. The L1 is heavily complicated if it is larger than the number of cache ways times the page size, since the virtual->physical tlb lookup happens in parallel. 8 way * 4kb = 32kb. AppleARM runs with a 16kb page size. 8 way * 16kb = 128kb
M1 has a massive reorder buffer, so it needs and can use more L1 cache. It's pretty much that simple.