How does FPGA fabric solve the bw bottleneck exactly?
What solves it is putting the compute power closer to the CPU (or memory). But you can do that with an FPGA or a GPU, or a CPU matrix etc. Compared to FPGA, the others will have much more compute power(especially for HPC) in the same die size/heat envelope.
I think the idea is to bring the compute power closer to the storage or NIC devices. At least that is the impression I am getting from their smartNIC/smartssd device.
In this case being video streaming in from the NIC, encoding/decoding occurring directly on the NIC.
Same to a degree with the bespoke smartssd where if you have some complex encryption, encoding, decoding or data driven application than the processing happens directly on the storage device via the FPGA.
