I have heard speculation that the issue is actually satellite signal steering. They’re using phased array antennas on both sides so the satellites need to know where to be listening
They haven't released any real info on it. But there's been teardown videos of the CPE showing the phased array design. And the patent for the terminals, which is public, shows a dual beamforming phased array. It clearly needs to be in order to maintain a seamless make-before-break with rising and descending satellites that are illuminating specific areas on the ground with spot beams.
If it was just knowing where to focus, the terminal could send a low bitrate signal with that information. And/or they could let you punch in new coordinates before you go somewhere.
That's why it would break if you leave the active cells entirely. It's not why it would break if you move from one active cell into a different active cell.
And they don't have that many satellites. Each one needs to have a pretty large active area.
Taat makes sense, with a small number of users they are not likely to spend CPU time doing fast Fourier transforms and whatnot for areas with zero subscribers
Are you sure about that? I see there's an article from a couple years ago talking about quad-core A53 CPUs with FPGAs. That's most likely used for the satellite avionics, rather than for the starlink radios. While it's possible the avionics and the radios are tightly coupled, I would be surprised if they were. They're probably mostly separate for fault tolerance reasons.
I suspect FPGAs wouldn't be fast enough to do the RF magic. I figure they likely partnered with a company like Qualcomm to develop some custom silicon, or adapted some existing cell tower silicon, since those chipsets are largely "software defined" these days anyway.
FPGAs are extremely commonly used in the RF telecomm space. You don't implement a multiplier in the free-form FPGA fabric, instead such FPGAs have banks of 'DSP blocks' which essentially give you hard silicon ALUs which you can then hook up however you want. This gives you extremely flexible and potentially massive parallelism with very tight latency guarantees, and you don't lose a huge amount of performance because most of the heavy lifting is in hard silicon anyway. Also FPGAs excel at high bandwidth I/O, which is usually extremely important in these use-cases. A DSP or even a GPU might give you more FLOPs per W or $, but they'll usually struggle with latency.
The quad-code A53 CPUs with FPGAs sounds like Xilinx's RFSoCs, which are explicitly designed to basically give you a custom high-performance base station on a chip (though they can't directly convert to the frequency range Starlink is using).
Not sure what your comment on the frequency range is implying. All signals are converted to baseband before processing. Nobody processes signals on the ground at Ku/Ka frequencies.
The response below mine goes into great deal, but yes, it's going to be fpgas, or an FPGA with a management cpu core in there. They had many reqs open for fpga developers early on.
