x86 only needs to macro op fuse 2 instructions at most, meaning you can look at the first instruction and immediately see which fusion to apply.
With RISC-V there are proposals to macro op fuse things like array out of bounds checks which comprise 5 instructions. You can't just check the first instruction and then the second. It's entirely possible that instruction 1 has 6 different micro op fusion patterns and you have to read instruction 2 to cut down on the number of potential patterns. It's also possible that the second instruction is not relevant in determining the pattern meaning you have to scan 3 instructions to determine the pattern. You have to start this pattern search on the beginning of every instruction you decode which limits your ability to add more decoders. Of course with enough spare transistors this is merely an extremely difficult problem, not an impossible one.
Yeah but each CPU can choose exactly how much fusion they want to do. That is not part of the ISA or promise they make to developers. Doing macro-op fusion like x86 should be a big win anyway combined with compressed instructions.
With RISC-V there are proposals to macro op fuse things like array out of bounds checks which comprise 5 instructions. You can't just check the first instruction and then the second. It's entirely possible that instruction 1 has 6 different micro op fusion patterns and you have to read instruction 2 to cut down on the number of potential patterns. It's also possible that the second instruction is not relevant in determining the pattern meaning you have to scan 3 instructions to determine the pattern. You have to start this pattern search on the beginning of every instruction you decode which limits your ability to add more decoders. Of course with enough spare transistors this is merely an extremely difficult problem, not an impossible one.