Yes, the Intel policy to intentionally cripple their cheaper SKUs, hoping to extort money from customers by pushing them to buy more expensive SKUs, is extremely annoying.
For example, right now all the new Tiger Lake CPUs contain a so-called "In-Band ECC" device, which allows error detection and correction even when using LPDDR4x memories, which do not have an ECC variant, like the DIMMs or SODIMMs.
This works by storing the ECC codes in a reserved part of the memory, so increasing the reliability is paid by a slight reduction in the memory capacity and in the memory bandwidth.
Nonetheless, those who are risk-averse, like me, would prefer this trade-off and would enable the "In-Band ECC".
However, you cannot do that because Intel disables the "In-Band ECC" feature on all Tiger Lake SKUs, except on 3 SKUs intended for Embedded and Industrial Temperature Range, which are presumably more expensive.
"In-Band ECC" is even disabled on the other 4 Tiger Lake SKUs for the Embedded market, which leaves them without any visible advantage over the normal Tiger Lake SKUs.
When Intel competed with Intel, this kind of business decisions probably made money for Intel, but now, knowledgeable customers should better buy from competitors, e.g. the new Ryzen V2000 for embedded applications, which support standard ECC memories without problems.
> Yes, the Intel policy to intentionally cripple their cheaper SKUs, hoping to extort money from customers by pushing them to buy more expensive SKUs, is extremely annoying.
I agree that this practice sucks, but to play devils advocate - is it possible that this is due to binning / yield maximization?
I would think that maybe they can save a very low proportion of chips with ECC not-working, but the large majority would be completely arbitrary market segmentation: handling of ECC is going to be limited to a small relative surface area of the die.
Now Intel 10nm still seems to be so bad that maybe it is interesting enough to bin on that, and maybe that's the cause Tiger Lake is even more limited on ECC capabilities than before in the various SKU. Although we already saw a restrictive move on Comet Lake.
Instead of continuing to multiply their SKU (I think they had enough even 5 or 10 years ago), Intel should go back to the drawing board and ship interesting microarch on better nodes...
Yup. Number of cores, cache size, and clock speed are things which make sense for binning to improve yield. Most other features do not (ECC memory support does not require much silicon, the odds of it being damaged while the rest of the chip is OK are too slim for binning to make sense).
For example, right now all the new Tiger Lake CPUs contain a so-called "In-Band ECC" device, which allows error detection and correction even when using LPDDR4x memories, which do not have an ECC variant, like the DIMMs or SODIMMs.
This works by storing the ECC codes in a reserved part of the memory, so increasing the reliability is paid by a slight reduction in the memory capacity and in the memory bandwidth.
Nonetheless, those who are risk-averse, like me, would prefer this trade-off and would enable the "In-Band ECC".
However, you cannot do that because Intel disables the "In-Band ECC" feature on all Tiger Lake SKUs, except on 3 SKUs intended for Embedded and Industrial Temperature Range, which are presumably more expensive.
"In-Band ECC" is even disabled on the other 4 Tiger Lake SKUs for the Embedded market, which leaves them without any visible advantage over the normal Tiger Lake SKUs.
When Intel competed with Intel, this kind of business decisions probably made money for Intel, but now, knowledgeable customers should better buy from competitors, e.g. the new Ryzen V2000 for embedded applications, which support standard ECC memories without problems.