That's good to know. At least that does ensure it's an ASIC, not an FPGA.
Besides lack of V extension, I'm sad about the seemingly artificial limits (8GB RAM onboard instead of slots, so you can't easily make a workstation out of this) and the still outrageous price.
I think that it has its market niche (developers working on risc-v ports), but most of us are better off trying RISC-V cores on an FPGA or emulator.
I'm hoping China will solve the cheap RISC-V SoC situation by releasing some cheap chip SBCs can be built on, at some point soon.
Lowrisc used to be all about doing that in an open hardware manner, but it seems the moment they got some funding, they got distracted into experiments (e.g. pointer validation stuff) that have little to do with achieving the original goal.
QEMU is shockingly excellent. Do not extrapolate, but one piece of code I was working on ran at a 1/4 of the speed in RISC-V under QEMU compared to the host. That's a really amazing result.
Much of that is due to RISC-V being quite emulation-friendly as far as ISA's go. You wouldn't guess that given e.g. the weird encoding of insn operands, but that turns out to be a minor factor in practice.
Absolutely. QEMU is JITting so decode is only done once. What helps here is the absence of crazy semantics, like flag updates. Some things are still expensive, such as indirect branches (jalr), virtual memory translation (load/store), and handling RISC-V's 31 registers without hitting memory for each of them (the host ISA, x64, has only 16 architectural registers).
Note that RISC-V instruction set extensions can always be emulated in machine mode, so the lack of V or B extensions will only ever be an issue wrt. performance, not compatibility.
Besides lack of V extension, I'm sad about the seemingly artificial limits (8GB RAM onboard instead of slots, so you can't easily make a workstation out of this) and the still outrageous price.
I think that it has its market niche (developers working on risc-v ports), but most of us are better off trying RISC-V cores on an FPGA or emulator.
I'm hoping China will solve the cheap RISC-V SoC situation by releasing some cheap chip SBCs can be built on, at some point soon.
Lowrisc used to be all about doing that in an open hardware manner, but it seems the moment they got some funding, they got distracted into experiments (e.g. pointer validation stuff) that have little to do with achieving the original goal.