I like RISC-V and I like RV32E, the 16-register variant which is still 'OPEN' and not yet ratified. I think RVC is a very elegant compressed instruction approach; it can address 8 registers and is part of RV32E. RVC is far better than the Thumb or MIPS16 modes.
Yeah, I like RISC-V generally, especially the base and the vector extension. However, they really went off the rails with the Bit Manipulation Extensions [1] still in draft form. Compare bfp which mixes control + data in the same register with ARMv8 bfi. It's only been added since the 0.92 draft but it seems to me very un-RISC-like.
I think you'll find that cutting out 16 registers wins you less area than it costs you in code ROM; and at a given execution speed target, you'll be costing yourself in power and area to make up for it.
There may be some kinds of software where this is not an issue, but for a lot of common types of software, 16 registers just keeps losing.
It’s not about the die area, but rather the instruction encoding space. And because you can freely mix and match long and short instructions, in practice it doesn’t matter much.
Yeah, I like RISC-V generally, especially the base and the vector extension. However, they really went off the rails with the Bit Manipulation Extensions [1] still in draft form. Compare bfp which mixes control + data in the same register with ARMv8 bfi. It's only been added since the 0.92 draft but it seems to me very un-RISC-like.
[1] https://github.com/riscv/riscv-bitmanip