That is 500 cycles without mitigation for CPU bugs, and without considering the non-local performance effects.
Non-local performance effects arise from TLB and other cache invalidation, which is required when changing from one task to another. You can't avoid that without putting everything in the same address space, which would make the system a fake microkernel. Fake microkernels have the less-readable code of microkernel design but without any benefits other than buzzword compliance.
CPU bugs like Meltdown and Spectre mean that every IPC now needs to blow away all sorts of caches and prediction. For example, you wipe out branch history. The cycles spent during the IPC call are only a tiny portion of the cost. The loss of cache content (TLB, branch history, data cache, code cache, etc.) greatly slows down the CPU.
Oh, I wouldn't dismiss "fake microkernels" so completely. One of them used to power a rather popular (proprietary) NAS Filer. I don't have a reference -- I believe this little gem never found its way into a publication (though the file system that ran on top of it did: https://www.cs.princeton.edu/courses/archive/fall04/cos318/d...).
Well, for one, those bugs aren't an issue on non-shared devices, and anything else outside of x86. That is not insignificant...that is still the majority of devices.
Two, the benchmarks for IPC usually include the cost of cache invalidation. This one [0] for SeL4 clearly shows the difference on Skylake for the kernels compiled with Meltdown mitigations. Still in the sub-microsecond range.
Plenty of non-x86 got hit by those bugs. ARM got both. PowerPC was hit as well.
Meltdown: Intel x86, IBM POWER, ARM Cortex-A75
Spectre: Intel x86, AMD x86, ARM (Cortex-R7, Cortex-R8, Cortex-A8, Cortex-A9, Cortex-A15, Cortex-A17, Cortex-A57, Cortex-A72, Cortex-A73, various Apple-designed cores) and some IBM hardware.
Lots of devices are shared, thanks to things like javascript.
Non-local performance effects arise from TLB and other cache invalidation, which is required when changing from one task to another. You can't avoid that without putting everything in the same address space, which would make the system a fake microkernel. Fake microkernels have the less-readable code of microkernel design but without any benefits other than buzzword compliance.
CPU bugs like Meltdown and Spectre mean that every IPC now needs to blow away all sorts of caches and prediction. For example, you wipe out branch history. The cycles spent during the IPC call are only a tiny portion of the cost. The loss of cache content (TLB, branch history, data cache, code cache, etc.) greatly slows down the CPU.