Seems like a great summary, but it should probably be expanded to cover a few things that really matter these days but were beyond the scope of the article originally.
It really doesn't explain much that is relevant to how SMP is done, but there's been a lot of interesting architectural progress there: The point-to-point HyperTransport links and on-die memory controller were the two biggest advantages the Opteron initially had over contemporaneous Xeons that used a shared front side bus connected to a memory controller in the Northbridge, but it also meant bring the complexities of NUMA to mainstream systems. Intel's first Dual-Core CPUs were also just two P4s sharing a socket, which was less effective than later designs that that had shared L2 and L3 caches.
I'd also like to see a bit more about GPUs, as they use a different mix of techniques (many cores, in-order, but also VLIW) and have quite different memory and cache systems (eg. ring buses, directly controllable global/local/constant memory regions).
It really doesn't explain much that is relevant to how SMP is done, but there's been a lot of interesting architectural progress there: The point-to-point HyperTransport links and on-die memory controller were the two biggest advantages the Opteron initially had over contemporaneous Xeons that used a shared front side bus connected to a memory controller in the Northbridge, but it also meant bring the complexities of NUMA to mainstream systems. Intel's first Dual-Core CPUs were also just two P4s sharing a socket, which was less effective than later designs that that had shared L2 and L3 caches.
I'd also like to see a bit more about GPUs, as they use a different mix of techniques (many cores, in-order, but also VLIW) and have quite different memory and cache systems (eg. ring buses, directly controllable global/local/constant memory regions).