C++ is a poor fit for this. Proper high-level HDLs are better to understand and ...

xvilka on Nov 26, 2019 | parent | context | favorite | on: Unleashing Open-Source Silicon

C++ is a poor fit for this. Proper high-level HDLs are better to understand and work with. Mentioned in the neighbor commment Clash[1], Chisel[2]/FIRRTL[3], Hardcaml[4], Spatial[5], various Python-based languages, there many[6].

[1] https://clash-lang.org/

[2] https://www.chisel-lang.org/

[3] https://www.chisel-lang.org/firrtl/

[4] https://github.com/janestreet/hardcaml

[5] https://spatial-lang.org/

[6] https://github.com/drom/awesome-hdl

pjmlp on Nov 26, 2019 [–]

While I agree, CodePlay, Khronos, Intel, and LLVM think otherwise with their SYSCL, oneAPI and LLVM bitcode to FPGA ongoing projects.