On: Building a lock free continuous ring buffer in Rust

[dragontamer]

> There is no "cache flushing" when barriers or other instructions are used to ensure seqcst on any system I am aware of.

Good to know. I've seen enough of your other posts to trust you at your word.

BTW: I'll have you know that AMD GPUs implement "__threadfence()" as "buffer_wbinvl1_vol", which is documented as:

> buffer_wbinvl1_vol -- Write back and invalidate the shader L1 only for linesthat are marked volatile. Returns ACK to shader.

So I'm not completely making things up here. But yes, I'm currently looking at some GPU assembly which formed the basis of my assumption. So you can mark at least ONE obscure architecture that pushes data out of the L1 cache on a fence / memory barrier!

[tntn → dragontamer]

GPU L1 caches are typically not coherent, so flushing them is necessary on GPU architectures.

[BeeOnRope → dragontamer]

Right, I could have been clearer that I was restricting my comments to general purpose CPUs.