We briefly note that the entire privileged-level design described in this document could be replaced with an entirely different privileged-level design without changing the user-level ISA, and possibly without even changing the ABI. In particular, this privileged specification was designed to run existing popular operating systems, and so embodies the conventional level-based protection model. Alternate privileged specifications could embody other more flexible protection-domain models.
Do many/most other architectures have this attribute? The idea of replacing only one "side" of an architecture has never crossed my mind before and seems pretty cool.
I can only think of two other examples that successfully planned for the future: the IBM 360 (extremely CISC, but still alive today) and the DEC Alpha (beautiful design, but now mostly dead).
If the choice had been Itanium or bust, it would have turned out much different outcome.
The main problem was that not many programs could sustain 3 parallel instructions in their critical path, which meant that the compiler would often generate NOPs to fill the empty instruction slots. IIRC the Itanium typically achieved around 40% of its theoretical performance on conventional workloads. The term "NOP density" was coined specifically to research this problem.
There is another interesting observation in  that I haven't realized before: even if the compiler were to succesfully generate 3 instructions per cycle, the processor then had to possibly fetch 3 memory locations in that instruction cycle. If two of those were already in cache, the instruction would still stall on the third memory fetch. Contrast this with the implicit parallellism of hyperthreading, where the processor can continue executing a different thread when the current thread encounters a memory stall.
Complaining that it doesn't support Linux is like complaining that a Honda Civic can't compete in Formula One.
It's the lack of full MMU that's the actual reason, it keeps the chip firmly in the microcontroller domain.
Memory is expansive, because Si chip area is expansive. The chip is designed for cheap special purpose applications. For that it fulfills the function.
Btw. you can run Linux on it, you just need to do something and can't simply put the latest and greatest Ubuntu distribution on it.
Please do tell more! I just made a Superbuy account but can't for the life of me figure out how to use it.
I'm somewhat fluent in Mandarin (my reading's a little rusty), so if that opens up additional options I'd love to know of them.
I want to see what Espressif, SiPeed, or some other vendor manages to do with RISC-V. I'm currently prototyping an A2DP vendor codec extension for Opus using an ESP32 board, and it is pretty painless. Bluetooth is the high value bit in my opinion.
There's also a dev board, which is probably much more useful than these bare modules. Unfortunately also out of stock: https://www.seeedstudio.com/Sipeed-MAix-BiT-for-RISC-V-AI-Io...
Theoretically it should be possible to run "Linux" on a glorified microcontroller like the OP with μClinux, but I haven't seen that used for "real" work. It certainly couldn't be used as a general purpose OS.
Not against a limited lifespan, but I really do like the model of a bridge device that communicates over wire or bluetooth, especially for consumer IOT - bt-based standards prevent vendor lock-in, for example.
Imagine if you worked months to develop a product based on this chip and after all this work you can't use it because it is out of stock with no further info. This is why it'll make no sense to use such chips until they can be bought at digikey, mouser etc in serious quantities.
In this particular case a vendor on that site claims:
> 3. There are 5.9MB SRAM can be used for convolutional neural network acceleration, so, it is possible to run small model like tiny-yolo v2,MobileNet, as you see in face detection routine video.