Note that Nvidia's core counts are misleading. To apply Nvidia's logic to Xeon Phi, a 64-core Xeon Phi is really 512 cuda cores--each SIMD lane is counted as an independent "Cuda core".
I wish we could talk about GPUs and similar architectures in terms of their total FPU width—how many 32b or 64b floating point operations can be done per clock— and as a secondary measure the number of independent instruction streams that can be worked on in parallel. One provides a upper bound on the arithmetic power of the chip and the other predicts how easy it will be to get close to full utilization of those compute resources. Distilling an architecture down to just one core count only guarantees that you can't compare it against dissimilar architectures.
