Many designs, especially ASICs have components ("IP") written in Verilog and VHD...

krupan on Oct 30, 2018 | parent | context | favorite | on: Spatial: A High Level Programming Language for FPG...

Many designs, especially ASICs have components ("IP") written in Verilog and VHDL. The commercial tools all support both languages. This is a big reason Free tools have not caught on

analognoise on Oct 30, 2018 [–]

Yes. We need to solve this problem for open source.