It is cheaper to make chip 4 times the size, than doubling the amount of process layers.
The trick is to add 3D features that don't involve making an entirely new device on top of another. This is the case for RAM, MRAM, and flash memory: they share devices in the stack, the only parts that are being scaled vertically are charge/spin carrying parts, but not amplifiers, backend, data lanes, or other devices.
There was a lot of talk about making 3D standard cells (stuff from which normal, non-memory, devices are made of.) The amount of work is immense. Every year there are a dozen cookie cutter PhD work like "3D NAND/XOR/INVERT device that is N percents smaller than before," but it will take years to cover and unify the whole cornucopia of devices in cell libraries. And only once it's done, will major fabs think of switching to that. No fab will try to add much more litho layers just to reduce footprint of only one device or macrocell.
The trick is to add 3D features that don't involve making an entirely new device on top of another. This is the case for RAM, MRAM, and flash memory: they share devices in the stack, the only parts that are being scaled vertically are charge/spin carrying parts, but not amplifiers, backend, data lanes, or other devices.
There was a lot of talk about making 3D standard cells (stuff from which normal, non-memory, devices are made of.) The amount of work is immense. Every year there are a dozen cookie cutter PhD work like "3D NAND/XOR/INVERT device that is N percents smaller than before," but it will take years to cover and unify the whole cornucopia of devices in cell libraries. And only once it's done, will major fabs think of switching to that. No fab will try to add much more litho layers just to reduce footprint of only one device or macrocell.