AFAIK the Z80 hasn't been publicly reverse-engineered to transistor level completely, it's mostly some important pieces (those that Ken Sherriff did, mentioned in the article) but apparently that was enough...
Notable that one of its direct predecessors, the Intel 8080, was reverse-engineered to transistor level:
I find it interesting that he used transparent latches at first, then after experiencing random glitches switched to flip-flops. I guess the Z80 designers had control of and deeply understood their timing, something you don't get with a FPGA :)
>"A-Z80 is a conceptual implementation of the venerable Zilog Z80 processor targeted to synthesize and run on a modern FPGA device."
Could someone say what exactly "synthesize" means in this context? Is this loading lookup tables in the FPGA in order to implement the code you wrote in your HDL - Verilog, VHDL, something else?
Exactly, synthesizable HDL code means code that can be actually translated into logic gates inside an FPGA [1]. Not every HDL instruction is synthesizable.
Verilog and VHDL have extensive support for non-synthesizable code, which are used for verification, simulation, testing, etc - e.g., [2].
What I didn't see was performance info -- how fast (clock rate) did the CPU run in the various FPGAs? I see the size (# LUTs etc) at https://opencores.org/project/a-z80 but not max CPU clock. Alternately, timing for 4-cycle instructions like 'LD A,B'-- which in the original Z80 took 2 M cycles, 7 T states, 4 MHz execution time = 1.75 uSec.
Notable that one of its direct predecessors, the Intel 8080, was reverse-engineered to transistor level:
https://zeptobars.com/en/read/KR580VM80A-intel-i8080-verilog...