Simpler MCUs have real hardwired SRAM access registers.
On more complex systems, even SRAM access goes through some stateful scheduling circuitry. So, interrupt latency on mainstream MCUs can't be reduced much.
If you want XIP with adequate latency, there is no alternative to spending money on Everspin MRAM. You will have accommodate the latency of SPI access, but that was never an issue in my practice.
Bwah hah, that reminds of me the ADSP-21xx series... They had a second register file for the interrupts. No pushing or popping. Interrupts happens, bam, all of your accesses are exactly where you left them! And when you're done, return to main thread and all registers are exactly where you left them on the next clock cycle!!!
If you have it, then use it. Its purpose is exactly to hold latency sensitive code, like interrupt handlers. The challenge is of course is to fit your code into it as it is usually small.
On more complex systems, even SRAM access goes through some stateful scheduling circuitry. So, interrupt latency on mainstream MCUs can't be reduced much.
If you want XIP with adequate latency, there is no alternative to spending money on Everspin MRAM. You will have accommodate the latency of SPI access, but that was never an issue in my practice.