When we get to 7nm, the today's chip that is using 1 cm^2 size silicon can probably be build with 0.25 cm^2 size silicon die. (IO pads are another factor).
If "everything (mainly yield?) being equal ", they should be able build 4x amount of chips from the same silicon wafer. Again, assuming IO is not an issue.
If the process cost, yield is similar, the new chips "can be" 4x cheaper OR they can pack 4 times # of transistors into the same 1 cm^2 area. It can means more CPU, GPU cores, much larger L1, L2, L3 cache for the same chip size.
When we get to 3 nm, they can build 16x amount of chips from the same 12 inch wafer.
"When we get to 3 nm, they can build 16x amount of chips from the same 12 inch wafer."
That's only if they are not up against pad-limited die size. Long ago people were running up against the issue of pad-limited die size, where the size of the I/O ring set the die size while the core logic ended up using less than all the available area. People were trying to figure out what extra stuff to throw into the core since it was shrinking so fast and the I/O was not. That was usually more memory, but that wasn't always useful.
So what's happening on that front these days? Are the current architectures actually able to make use of many more cores and memory without blowing up the I/O count of the chip?
Today we are @ ~ 14, 16 nm.
When we get to 7nm, the today's chip that is using 1 cm^2 size silicon can probably be build with 0.25 cm^2 size silicon die. (IO pads are another factor).
If "everything (mainly yield?) being equal ", they should be able build 4x amount of chips from the same silicon wafer. Again, assuming IO is not an issue.
If the process cost, yield is similar, the new chips "can be" 4x cheaper OR they can pack 4 times # of transistors into the same 1 cm^2 area. It can means more CPU, GPU cores, much larger L1, L2, L3 cache for the same chip size.
When we get to 3 nm, they can build 16x amount of chips from the same 12 inch wafer.