Imagine graph paper with the length of the side of a square being the feature size. 3nm. Where you shade in represents the metalization. Now imagine you have a design rule that says a metalization trace must be no less than 3 squares wide, for the sake of functionality.
That's a 3nm process. You might get away with putting to 9nm lines within 3nm of each other, or you might come up with some interesting transistor shapes that would not be possible on a larger process. But a trace would still have to be 9nm.
