On: An FPGA-friendly 32-bit RISC-V CPU implementation

[duskwuff]

For an FPGA implementation, it's often useful to hook the soft core into the FPGA's own JTAG controller, so that it's possible to program the FPGA and debug the core over a single connection. This is often not portable even between FPGAs, and certainly isn't portable to ASIC, but it makes development a lot easier, so...

[Dolu → duskwuff]

Yes i agree, would have been more convenent to use the integrated jtag of the FPGA, but i focused on making an universal solution first :)