Couldn't you hypothetically design the pinout to be suitably symmetrical to avoid major part of the wasted pins. For example if the chip has 4 memory channels, then lay out the memory pins identically but rotated in each quadrant. Same principle should apply to other major pin count consumers (pcie lanes, power/ground pins), which leaves somewhat small area that needs to be duplicated/quadrupled.
Of course implementing such design would be ridiculously complicated with very little benefit. But it would be pretty cool though :)
