I think this has been garbled, but he's referring to synchronisation across clock and power domains.
Normal D flip-flops require that, at the time of the clock edge arriving, the inputs are not changing. If you violate this you get "metastability" and data loss. Special structures are needed when you move data from a fast-clocked area to a slower. On processors, usually the core is at one (maybe variable!) speed while the peripherals and DRAM are at a lower speed (what used to be called "front side bus").
As to the application for async, maybe he's right and maybe he isn't. There would have to be synchronisation to fixed external bus speeds, but 20% seems very high as a proportion of power consumption.
Normal D flip-flops require that, at the time of the clock edge arriving, the inputs are not changing. If you violate this you get "metastability" and data loss. Special structures are needed when you move data from a fast-clocked area to a slower. On processors, usually the core is at one (maybe variable!) speed while the peripherals and DRAM are at a lower speed (what used to be called "front side bus").
As to the application for async, maybe he's right and maybe he isn't. There would have to be synchronisation to fixed external bus speeds, but 20% seems very high as a proportion of power consumption.