Chip fabrication costs are usually a direct value per mm2 the chip takes up in the wafer.
Besides that, a smaller area is also good for yield (% of chips that test out OK out of all fab'ed, in case random defects occur in any of the many processing steps.)
Besides that, a smaller area is also good for yield (% of chips that test out OK out of all fab'ed, in case random defects occur in any of the many processing steps.)