Those schematics though are just throwing everything into a bus... It isn't really differentiating signals at all.
What is the difference between just labeling all the FPGA outputs (which is done here), and then labeling the inputs where they go rather than having the bus line in between?
Or in other words, is this really the best schematic to be comparing against?
>And you would use this with KiCAD -- this just takes the place of eeschema.
That's the point -- if the schematic is just connecting pins to buses and other pins, how is that improved by drawing a rectangle and placing the pins on its perimeter? It can be clearer as a simple textual netlist, or even clearer as a simple textual program that generates the netlist.
What is the difference between just labeling all the FPGA outputs (which is done here), and then labeling the inputs where they go rather than having the bus line in between?
Or in other words, is this really the best schematic to be comparing against?
>And you would use this with KiCAD -- this just takes the place of eeschema.
Yes, I misspoke.