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In a similar vein, here is a VM I made for educational purposes.

https://zenoamaro.github.io/chip3/

It runs in the browser, featuring a fully inspectable CPU and RAM, rewindable execution, and simple inline disassembly of the source. It's also got a simple assembler (no GUI yet, sorry for that) which it uses to run the example program[1].

The hardware is as simple as possible:

- 3-bit instruction set, for a grand total of 8 instructions, inspired by the PDP-8

- 5-bit addressing, giving 32 words of 8 bit RAM

- A simple, integrated printer

The source is, I hope, documented well enough[2]. There is a handbook available[3], and a small IDE is in the works.

[1]: https://github.com/zenoamaro/chip3/blob/master/dist/index.ht...

[2]: https://github.com/zenoamaro/chip3/blob/master/src/System/CP...

[3]: https://github.com/zenoamaro/chip3#programmers-handbook




Cute little cpu! I like the OPR instruction, neat way of handling increment/decrement (DEC by way of NOT and INC). Are ROR and ROL also chained? That's neat too.


Thanks! It is derived PDP-8's own OPR instruction, which goes even further, with many carefully aligned combinations leading to clever results. A testament of ingenuity which reveals fine craftsmanship.

In reality, I've considered switching to a regular mapping, so to have 32 no-operand instructions instead, which would fit the original five operations, all sensible combinations, plus more.

But chaining operands is definitely a more extravagant thing, so I think it can be instructive in showing how creative a solution can be in face of limitations .


The chaining kind of reminds me of how z80's ALU works [1]. It's kind of chained in together over time.

[1] http://www.righto.com/2013/09/the-z-80-has-4-bit-alu-heres-h...


This is very cool, zenojevski! Good luck with your VM!




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