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Indeed, even TSMC executives noted its 10 and 7nm nodes will have minimum feature sizes of about 20 and 14nm, respectively. (from http://www.eetimes.com/document.asp?doc_id=1329217)


Yeah overall feature size isn't 1 to 1 with the "process" anymore, hasn't been there for a long time.

All of them use various sub-wavelength techniques like using multiple stencils and masks to create aperture / fresnel lense like effects etc.

Pretty much since you have multiple measurements for "feature size" like fin, gate, interconnect pitch etc. companies are just naming their process roadmap to show "progress". I don't think even Intel's 14nm process actually has a 14nm "feature size" and if it does I don't know what measurement they are basing it on.

http://images.anandtech.com/doci/8367/14nmFeatureSize.png http://images.anandtech.com/doci/8367/14nmFinfet2.png




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