Some upcoming chips are supposed to support switching individual processes to x86's "TSO" memory model. That might be the most significant extension that Apple has for x86 emulation: it allows eliding all memory fence instructions used to adapt to the weaker memory model.
LoongArch could have instructions that emulate specific x86 behaviour and flags, but there is practically no documentation available.
Is it just "some upcoming chips" inventing their own extensions? Or is this a standardized ARM extension?
Basically, will writing against these upcoming chips mean writing one implementation for Qualcomm, one implementation for Rockchip, one implementation for Samsung, etc? Or will it just require one implementation for the standard ARM "switch to total store ordering memory model" extension
I'm sorry, I meant RISC-V, not ARM. So far the RISC-V standard has specified behaviour under the TSO memory model and a flag in the ELF header for code that has been compiled for TSO. There is not yet any ratified extension for dynamic switching of memory model but I'd expect anything vendor-specific to be wrapped behind a Linux syscall.
Fair enough. Sort of. You can get the same assurances OTP gives you using secure boot + open source + reproducible builds.
Regardless the rest us who don't want to go through the extra work OTP creates still of use want to put our credit cards, fido2 keys, government licences, concert tickets and whatever else in one general purpose computing device so we don't have to carry lots of little auth devices. To do pull that off securely this device must have firmware I can not change.
The OP wants to make it illegal to sell a device with firmware I can not change.
In asking for that, they've demonstrated they don't have a clue how secure and opening computing works. If they somehow got it implemented it would be a security disaster for them and everybody else.
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