Probably done with 3 separate litho/etch layers, where they etch and process in groups of 110 or so.
Each of those layers can have a cell, so if you have a tlc device at a 100nm pitch, you have a density of 321*3/(1e-4)^2 bits/mm, or about 1e11bits/mm2.
Fun reference: atomic density is 1atom/.5nm, so 1/5e-7^2, or 4e12/mm2 ish.
Lithography lives in the thin film approximation anyway. Timiosheko is a good reference. There are papers from Barnett or Nix that are very nice, but edges will probably end up a fem solver domain.
I am not sure where that would come from. There is nothing about dsa that means this.
Dsa is one of many patterning assist technologies, just...an old one. Neat, but not 'new'. You use patterning assist to make smaller, more regular features, which is exactly what the 16a vs 18a refers to.
That has somewhat less to do with performance, which is tied as much to material, stress, and interface parameters. Nothing gets better from being smaller in the post dennard scaling era, the work of integration is making better devices anyway.
Patterning choices imply different consequences. For example,.a.double euv integration can take advantage of spacer assists to reduce ler and actually improve cdu even with a double expose. Selective etch can improve bias, spacer trickery can create uniquely small regular features that cannot be done with single patterns. Conversely, overlay trees get bushier, and via CD variance can cause horrific electrical variance. It is complicated, history dependent, and everything is on the developmental edge.
DSA is what is going to make it possible for Intel to compete at all. Without it, they are going to have fancy machines in fancy foundries that are too expensive to attract any customers.
To the best of my knowledge, DSA never made it out of the lab.
But still, what is stopping others from also developing DSA? I am not sure the technology alone will be Intel's savior. They've been on the decline for a while, ever since they took a jab at Nvidia for releasing CUDA, they demonstrated a narrow vision, consistently, and now they're playing a catch up game.
Half your wires deliver power, half deliver signal. So if you do both on the same side, you need twice the density of wires. If you split the delivery into two parts, you get double the density without needing to make things smaller.
This isn't quite right. Big wires (ideally entire planes) deliver power. Small wires deliver signal. Half and half isn't the right split, and you don't want to make power wires smaller.
The very different requirements of the two is where a lot of the gains come in.
It is going to get even a bit more interesting when you consider power gaters and virtual power supplies. Now the real power will be on the back side and the virtual power will be on the front side. Fun time for power analysis.
True! I went a little far in the name of 'eli5'. I think it roughly holds that you gain about a factor of 1.5 in routing density by removing the power distribution, so you can relax some critical patterning. But I havent looked closely in a long time.
Oft-missed pedagogical point for working with five-year-olds:
Precision is important. You'll notice every comment I made was as simple as I can make it, but /technically correct/. I did not oversimplify to where I changed facts.
* It's okay if five-year-olds don't fully understand something. That builds exposure, and leaves a placeholder for future information and curiosity.
* On the other hand, if you build out an array of misconceptions, those become very expensive to address later.
To a large extent, the younger the child, the more comfortable they will be with being told things they don't understand. A baby doesn't care if you're reading them a book on trucks or a book on homeomorphic transformations; they're picking out the phonemes. A toddler will trust you as an adult, and won't understand 90% of the stuff they hear anyways. A five-year-old, you can still say a lot they won't understand and they'll be not just okay but happy. By maybe seven, lack-of-understanding will become frustrating, and in most cases, by eleven, it's gone.
I could write a long essay on this stuff, and why it's so important to maintain that ability to be confused and half-understand, but I very intentionally leave placeholders when working with five-year-olds.
The benefit of X-ray is they go through everything (so you can see metal). The problem is they go through everything, so you have little signal.
For metal/bump voids, hard to inspect any other way
The harder problem for X-ray inspection is that 1) resolution is difficult to scale economically (possible, but hard). And 2) if any version of wafer or die direct bond dominates (I tend to believe it will), then x-ray won't be good enough anyway, so hard to spend the investment on this.
You are correct. You can do mask edits or short runs in some cases beam.
Even more interesting is mask level overlay and CD correction using ultrafast absorption based stress fields. There are some heat technologies out there
It isn't complex at all. Take the average density (average of sram and logic), take the square root of that, and you have (barring a factor) the node.
The best way to understand the dimension is to look at the contacted gate pitchm2 pitchcell height,and take the square root. The pitches obviously make an area, the cell height sets the 'design' component. So you get a reasonably scaled number.
Putting it that way also clarifies technology. Why euv, to tighten contacted gate pitch. Why cobalt: to tighten up metal 2 pitch (without killing resistance). Why backside metal: lowers cell height. There is of course more to it, but it is a good way to coarsely understand
A good way to know if it is marketing is if someone talks about feature sizes instead of pitches. Patterning is done by pitch. For example, you don't do euv to make smaller features. You do it to make more complex layouts at tight pitch.
> contacted gate pitchm2 pitchcell height,and take the square root
I am having trouble parsing `pitchm2 pitchcell height`.
Assuming that you meant to use `*` and then HN's markdown assumed it was italics, and placing `×` where italics start and begin:
sqrt(pitch × m2 pitch × cell height)
Then I am left with the questions:
What are the units of pitch? Best guess: length units? (Based on: cell height having length units. `m2 pitch` being dimensionaless?
Why do the pitches "obviously make an area" then?
What are the units of metal to pitch? Best guess: dimensionless. (Based on the final units of the sqrt being repoted in length, and the cell height presumably having units of length).
What the units of cell height? Best guess: length units, based on what the variable is called.
Each of those layers can have a cell, so if you have a tlc device at a 100nm pitch, you have a density of 321*3/(1e-4)^2 bits/mm, or about 1e11bits/mm2.
Fun reference: atomic density is 1atom/.5nm, so 1/5e-7^2, or 4e12/mm2 ish.
Not too far away.
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