
A smaller, cheaper RISC V board - MrsPeaches
https://hackaday.com/2017/09/18/a-smaller-cheaper-risc-v-board/
======
Joking_Phantom
IMO, the first step for people interested in promoting RISC V should be to get
it into the hands of the universities' undergrads. Berkeley's EECS 151 lab
final semester project was to implement a RISC V CPU at 50 MHz on a FPGA.

If EE/CS departments of colleges adopt RISC V hardware for teaching their
students, providing cheap microcontrollers and boards to students at the start
of their semester classes, those precocious little buggers are going to build
Doom clones and help port their favorite flavor of linux onto them. When
you've got a generation of top talent tinkering with an ISA that doesn't suck
like x86, you're going to see adoption in actual industry.

~~~
userbinator
_When you 've got a generation of top talent tinkering with an ISA that
doesn't suck like x86, you're going to see adoption in actual industry._

RISC V is not much more than a slightly tweaked MIPS, the previous "preferred
academic architecture", and we all know what happened to that... much to the
chagrin of those who thought MIPS would be "the future of computing".

My prediction is that it will probably replace MIPS where it's currently used
( _very_ low-end tablets and phones, and a lot of home routers), but won't
really displace ARM or x86. A "pure RISC" like MIPS and now RISC V just
doesn't have the "CISCness" that makes successful CPUs beyond the theoretical.

[https://www.extremetech.com/extreme/188396-the-final-isa-
sho...](https://www.extremetech.com/extreme/188396-the-final-isa-showdown-is-
arm-x86-or-mips-intrinsically-more-power-efficient)

Look at the results for the Loongson. It has at least twice as much cache as
the others and 4-way OoO, yet after normalising for clock frequency and
process power, it manages to be dead last in efficiency on 3 out of 4 of the
benchmarks.

I've been following trends in the industry since the 90s. The "RISC dream" is
still very much a dream. Trying to get an overly simple and restrictive ISA to
perform well is sheer folly. Things that the RISC proponents thought would
matter (decode complexity, number of architectural registers, addressing mode
complexity) actually didn't, and what they thought wouldn't matter (memory
bandwidth/latency, clock speed, instruction density), did. A denser, more
_intel_ -ligent (pun fully intended) ISA is what x86 and ARM is moving toward,
while the MIPS/RISC advocates are going backwards.

~~~
legulere
> Look at the results for the Loongson.

This is a processor comparison. The Loongson is the only 90nm chip here. No
wonder it has no chance against 32nm and 40nm chips. The 60nm A8 also performs
horribly.

~~~
userbinator
If you read the linked paper you'll see that they scaled the process size and
clock speed accordingly.

------
unwind
I think this is very interesting, and certainly consider myself a "fan" of the
RISC-V ISA and project. Great to see cheaper/smaller boards coming along.

I'm still hoping they can somehow get access to a flash process, so that they
can integrate the CPU core (and peripherals, of course) with the flash in the
same chip. This board still uses QSPI to talk to an external flash, which
houses the code.

I'm not sure how programming is done, with "traditional" microcontrollers that
have their own flash, you use JTAG (or even serial on the older ones) to
program the flash directly, then just remove the JTAG lines and reset the
board and it runs your code. With this, I guess you have to program the SPI
flash directly, or (perhaps?) use JTAG to talk to the microcontroller core and
control its SPI that way?

Anyway, my understanding is that flash memory is "deep analog magic" which the
people behind RISC-V haven't mastered yet, so they can't design the memory
into the same chip as the processor core.

------
problems
Nice. That's a big improvement in price over the previous ones.

I'm still a little unclear on RISC-V's goals - are they looking at the
microcontroller market or are they looking more to offer an alternative for
ARM and x86 CPUs?

In the microcontroller market there's a lot of competition right now,
especially with devices like the ESP32 going for $8 with wifi and bluetooth.

~~~
pgeorgi
> I'm still a little unclear on RISC-V's goals

Maybe a bit cynic, but given their churn in the lower level specifications
(supervisor mode and up) my guess is:

Main goal: write lots of theses and papers and obtain degrees.

Secondary goal: have an unencumbered ISA to help with the main goal.

Everything else depends on those who adopt the ISA. If some org is willing to
spend the multi-million $$$ necessary to design a high-performance desktop
class CPU (and more to make it a reality), it will happen.

Those low-end chips are easier to do, and an easier market to serve: The ISA's
license fees are a bigger chunk of the chip's price, so RISC-V dropping that
to 0 helps more. You also don't need to build a high-end chip that blasts
everything else out of the water before your newcomer is even considered,
since in the microcontroller market there are several pockets of "good
enough".

If that works out, there might be attempts to scale up later (when they have
experience and financial resources to work with).

~~~
noir_lord
Something I was thinking about the other day was what will happen when we hit
mass market process limits, Intel has always stayed ahead of it's competitors
outside of x86 land even when their architectures where not competitive by
having the best process but when the rest of the world catches up and suddenly
I can order a 20bn transistor 3nm (or whatever) chip with RISC-V cores then
things start to look a lot different.

Throw in that we already have a mainstream (if you squint) desktop OS that is
a compile away (and has driver support for a _lot_ of hardware) and if I where
Intel I'd be worried in the mid-term.

Hell for the first time since the first AMD64's came out Chipzilla is looking
vulnerable from the AMD direction, a surprise to a lot of people (including
myself, I bought a Ryzen 1700 for work back in late May and I've been
astounded by the performance per £ on my workloads).

~~~
subwayclub
Intel has a lot of threats lately. Things seem to be moving towards a small
die and MCM strategy to get better yields and move investment towards the
package and FSB. AMD made a huge investment in that direction with Zen arch
and Infinity Fabric - Threadripper's big package and high core count has
opened a new tier of enthusiast desktops - and they may have plans for
furthering that on the GPU side of things(Vega is positioned for efficiency at
lower wattage, which is poorly reflected in the "hot-and-loud" flagship
releases. It's expected to pair well with Zen in the forthcoming Raven Ridge
APUs though.)

Intel shares with Nvidia(also currently using large dies) a limited form of
performance leadership at the high end that may be eroded in the face of these
shifts. Most of the market is going to see more benefit from more cores
instead of faster cores with the current conditions. That might be less true
once we're talking about a baseline of 16 or 32 cores, but 2 is proving to be
too few for current workloads.

And that's just their nearest competitor. ARM SOCs have consumed the mobile
market and are creeping upwards. My ARM Chromebook makes a pretty good Linux
desktop too, and you can practically trip over RaspPi devices.

~~~
noir_lord
I'm nothing but happy with my Ryzen 1700, I nearly held off a year buying my
new laptop because I wanted to see what their mobile chips where like.

In the end I went with an i7-7700HQ because I simply couldn't make my old
laptop last any longer, 8GB ram just wasn't enough for my workflow.

If the mobile Ryzens are amazing I'm going to regret that maybe.

------
spilk
Slightly off topic, but are there more-or-less boilerplate RISC-V verilog/VHDL
designs available that can deploy to ~$100ish FPGA boards? I'd be super
interested in messing with that if so. I took digital design and HDL related
courses in university but haven't really had an opportunity to do anything
productive with that yet.

~~~
peller
I have no experience with any of this, but to my knowledge what you're looking
for is the Rocket Chip.[0] It's a RISC-V core implemented in Chisel. The
primary FPGA target is a bit steep at around $500 [1] but there's a "small"
config[2] that targets a more reasonable $190 board [3].

[0] [https://github.com/freechipsproject/rocket-
chip](https://github.com/freechipsproject/rocket-chip)

[1] [http://store.digilentinc.com/zedboard-zynq-7000-arm-fpga-
soc...](http://store.digilentinc.com/zedboard-zynq-7000-arm-fpga-soc-
development-board/)

[2] [https://github.com/freechipsproject/rocket-chip#-how-can-
i-p...](https://github.com/freechipsproject/rocket-chip#-how-can-i-
parameterize-my-rocket-chip)

[3] [http://store.digilentinc.com/zybo-zynq-7000-arm-fpga-soc-
tra...](http://store.digilentinc.com/zybo-zynq-7000-arm-fpga-soc-trainer-
board/)

------
phkahler
Just saw this:

[http://markets.businessinsider.com/news/stocks/SEGGER-
Adds-S...](http://markets.businessinsider.com/news/stocks/SEGGER-Adds-Support-
for-SiFive-s-Coreplex-IP-to-Its-Industry-Leading-J-Link-Debug-
Probe-1002381278)

The ecosystem is starting to pull industry players.

------
Dowwie
Notice how they're selling through GroupGets?

Aside from GroupGets and MassDrop, who else is operating in the crowd-funded,
discounted bulk-purchase collaborative.. consumption.. space?

~~~
ageofwant
US$45 to ship down under for a US$50 order seems, excessive... guess I'll be
buying the AU$10, shipping included one-hung-lo gearbest knockoff in a few
months time then. Pity really, I love supporting these kind of projects.

~~~
voltagex_
Check what PriceUSA or Shipito would charge. (not affiliated, have used both
of these services before)

------
chubs
I wonder if you can program this with Rust? There seems to be some support for
a LLVM backend which would suggest 'yes'. However the gcc linker is still
required which I'm unclear on whether that rules it out:
[https://riscv.org/software-tools/low-level-virtual-
machine-l...](https://riscv.org/software-tools/low-level-virtual-machine-
llvm/)

~~~
kam
It's a work in progress: [https://github.com/rust-
embedded/rfcs/issues/36](https://github.com/rust-embedded/rfcs/issues/36)

------
baobrien
Does anybody know if/where you can just buy the FE310 on it's own?

~~~
lndmrk
[https://www.crowdsupply.com/sifive/hifive1/updates/fe310-chi...](https://www.crowdsupply.com/sifive/hifive1/updates/fe310-chips-
and-improved-documentation-are-now-available)

~~~
baobrien
Thanks! I missed that. $5 per chip is really not bad for a higher end
microcontroller, especially with the 'low volume' tax.

