
FPGA internal tristate buses - chclau
http://fpgasite.blogspot.com/2017/05/fpga-internal-tri-state-buses.html
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lisper
TL;DR: as semiconductor technology advances, the limiting factor in an FPGA
shifts from not having enough transistors to wire speed: smaller wires have
higher resistance and so they are slower than the old fat wires. When
transistor count is the limiting factor, tri-state drivers make sense. When
wire speed the limiting factor, they don't.

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al2o3cr
Tristate buses are mostly a workaround for interconnect (pins on chips & wires
on boards) being expensive. Early CPUs sometimes took it even further, using
not only tri-state but address/data latching; the 8008 is a classic example (8
data bits & 14 address bits output through a single byte-wide connection).

The tradeoff in something like the 8008 is lower performance: the 22 bits
required to form a full address + data pair need 3 clock cycles to travel from
inside the CPU to the peripherals.

What we see instead in FPGAs is "buses" like AMBA - unidirectional data &
address, sometimes with wide paths for data (the Xilinx AXI4 generator claims
up to 1024 bits). These let designers take advantage of plentiful interconnect
to get more bandwidth without needing the underlying FPGA's clock rate to
increase.

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davemp
Who is this author? This seems mostly wrong to me. Shrinking die size doesn't
seem to have anything to do with the removal of tristate buffers from FPGAs.
FPGA vendors are constently trying to shorten the length/amount of
interconnects because it translates into faster designs with more logic
regardless of die size.

What what I've heard/read. The RAM change is entirely due to architectural
improvements and a shift towards "columnar" design. Architects have learned
that having your data flow in a similar direction simplifies routing and leads
to more dense and faster designs.

The pattern:

LOGIC <\- CONTROLLER <=> RAM

Doesn't translate well to modern FPGA architectures because of the multiple
data directions, so architects switched to:

INPUT/CONTROLLER -> RAM -> READ_LOGIC

* This is a simplification as FPGAs place and route is a pretty huge problem with many trades offs to consider.

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chclau
I am the author of the article and it may seem wrong to you but it is the way
things unfolded. Once interconnections were faster than the transistors, at
the beginning of the 2000's that fact was reverted, now transistors are much
faster than interconnection. It is the reason behind many other development,
like multi-core devices. Since transistors are faster than interconnections,
it is reasonable to make many units working fast than a big unit working
slower because of the interconnections.

The tristate buffers were abandoned on the FPGA market, followed by the ASIC
market.

~~~
davemp
Sorry, you are definately right about the motivation for the change. My first
paragraph is off base. I should have said "this seems incomplete" instead of
wrong.

I just wanted to see the architectual reasoning behind how switching from
tristate -> unidirectional leads to faster interconnects.

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amelius
> With the evolution of semiconductors technology, internal tri-state buffers
> were abandoned.

I suspect it also provides a nice guarantee that you will never have two
drivers on the same line (potentially causing short-circuits).

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mcshicks
I really think this has more to do with the size of a pull up resistor on chip
than anything else. I'm not an IC designer, but I do know that the way you
make a resistor on chip for an analog circuit is a snake like structure in
silicon, much bigger than a transistor for digital logic.

[https://en.wikipedia.org/wiki/Integrated_circuit](https://en.wikipedia.org/wiki/Integrated_circuit)

~~~
chclau
You may be having a confusion between tristate buses and open-collector, or
open-drain, drivers

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DigitalJack
tristate bussing invites the possibility of contention (one driver trying to
drive the bus high while the other drives it low). You can burn up your chip
doing this, an will certainly degrade it in any case.

