
The Linux Kernel FPGA Subsystem - yummypaint
https://www.kernel.org/doc/html/latest/driver-api/fpga/index.html
======
elevation
This subsystem will configure an FPGA attached to your host by sending it a
bitstream you provide. You still have to use your FPGAs vendor tools to
generate the bitstream.

One popular use case is for System-on-Chip (SoC) designs that pair a Processor
System (PS) with Programmable Logic (PL); once the PS is running the kernel,
the FPGA Manager can be used to program the PL fabric from kernel space.

FPGA Manager has another handy feature for FPGA images that implement new
peripherals on buses like SPI, I2C, PCI, AXI, etc. These devices are not
"discoverable" in the sense that they are capable of communicating to the
kernel what driver must be loaded to support them. So in along with a
bitstream, FPGA Manager accepts a device tree overlay which indicates to the
kernel what drivers to load for the new resources implemented by the
configured FPGA. This causes the kernel to probe the requisite drivers after
the FPGA configuration has completed. The FPGA manager can also unload drivers
for devices implemented in an FPGA that is being reconfigured.

Unfortunately, in LTS kernels 4.9 and 4.14, while SoC vendors include support
for their own PL targets, the FPGA Manager subsystem was written as a
singleton; once you've configured e.g, the PL, you can't configure additional
peripheral FPGAs.

~~~
qubex
> _was written as a singleton_

Can you please explain this? What does it mean exactly? And is it different in
versions of the kernel that aren’t the ones you explicitly mention?

~~~
ouzu
A singleton is a design pattern making sure only one instance of an object can
exist

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qubex
I know the term but I can’t quite understand how to interpret it in this
specific context. Does it mean you can only program an FPGA once? Only one
FPGA? One object per bus?

I really don’t understand it.

~~~
anewvillager
> you can't configure additional peripheral FPGAs.

My understanding is that you can only have a single FPGA.

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mhh__
What kind of data throughout can you get with this?

I've always wanted to play with something like this but FPGAs worth connecting
to a PC are $$$.

~~~
non-entity
Admittedly, I'm pretty ignorant of FPGA's right now, but I was curious about
PCIe based boards a while back and was able to find some moderately priced
ones such as

[https://www.latticesemi.com/products/developmentboardsandkit...](https://www.latticesemi.com/products/developmentboardsandkits/ecp5pciexpressdevkit)

It's around $300, which might not be cheap, but it's certainly more affordable
than other I've seen which are very much out of the range of any hobbyists.

~~~
5-
that one has been superseded by the ecp5 versa.

[https://www.latticesemi.com/en/Products/DevelopmentBoardsAnd...](https://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/ECP5VersaDevelopmentKit)

it's still $275, and in addition to lattice tools, it is well supported by the
open source trellis/yosys/nextpnr flow:

[https://github.com/SymbiFlow/prjtrellis](https://github.com/SymbiFlow/prjtrellis)

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yummypaint
Came across a pretty clear video with an iCE40 and a rasPI showing the
concept, though its from 2017. Presumably it would be a similar process to do
this with a pci card?
[https://www.youtube.com/watch?v=nIEB1VAGUcs](https://www.youtube.com/watch?v=nIEB1VAGUcs)

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baybal2
Since when it was in the kernel?

~~~
Znafon
The first commit is from Oct 7 2015.

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bawana
Is there a tutorial for dummies somewhere? I want to implement my deep
learning model in an fpga to see if it would be faster.

~~~
czig
I like this book:
[https://github.com/hamsternz/IntroToSpartanFPGABook/blob/mas...](https://github.com/hamsternz/IntroToSpartanFPGABook/blob/master/IntroToSpartanFPGABook.pdf)

It’s free and the exercises are very helpful for getting some hands on
experience.

