
Sidestepping Moore’s Law - Lind5
https://semiengineering.com/sidestepping-moores-law/
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kurthr
I'm surprised there's no discussion of wafer level stacking and interconnect.
I suppose that's mostly done at the foundry, but stacking digital with memory
and/or flash could have real bandwidth and performance effects.

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sanxiyn
Isn't that what "2.5D" in the article refers to?

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AChamarthy
2.5D is connecting chips laterally on an interposer. Full 3D IC wafer level
Packaging would be stacking wafers on top of each other a in dense,
heterogenous, 3D configuration - i.e. "memory near compute"

Ex: [https://www.kurzweilai.net/radical-new-vertically-
integrated...](https://www.kurzweilai.net/radical-new-vertically-
integrated-3d-chip-design-combines-computing-and-data-storage)

