
System on Chip wrapping the SERV RISC-V soft processor - homarp
https://www.rotwang.co.uk/projects/serv.html
======
nl
Worth noting that the new ESP32-S2 board has a RISC-V co-processor[1], and
SeeedStudios recently released the Sipeed MaixCube with a K210 RISC-V[2] as
the main processor (and a screen etc for $25!! I've ordered one).

[1] [https://maker.pro/esp8266/tutorial/a-comparison-of-the-
new-e...](https://maker.pro/esp8266/tutorial/a-comparison-of-the-new-
esp32-s2-to-the-esp32)

[2] [https://www.seeedstudio.com/Sipeed-Maix-
Cube-p-4553.html](https://www.seeedstudio.com/Sipeed-Maix-Cube-p-4553.html)

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jborza
Cool work! Thanks for the article. It’s writeups like this that made me want
to “upgrade” from emulating RISC-V in software to designing a core (I’ll try
VHDL though).

~~~
tyingq
I read this recently, might be helpful to see some of the choices (not all
RiscV):
[https://justanotherelectronicsblog.com/?p=705](https://justanotherelectronicsblog.com/?p=705)

Edit: A list of riscv implementations: [https://github.com/riscv/riscv-cores-
list](https://github.com/riscv/riscv-cores-list)

~~~
jhallenworld
We need a better list, but it would be quite some work to make it. I'd like a
list of performance, size, implementation language and bus interfaces.

I've been looking at this one for high end (1.9 DMIPS/MHz!):

[https://github.com/ultraembedded/biriscv](https://github.com/ultraembedded/biriscv)

Google/lowRISC has this one:

[https://github.com/lowRISC/ibex](https://github.com/lowRISC/ibex)

I'm using picorv32 right now on Lattice ECP5- running code out of SPI-flash,
but I added an instruction cache for speed.

It's amazing how many RISC-V things are happening all at once right now.

Anybody know of any free RISC-Vs with floating point? It would be helpful to
have something similar to ARM Cortex-M4F.

Edit:

From the "riscv-cores-list" I see WARP-V, which I'm not interested in due to
"TL-Verilog". But its FPU is this:

[http://www.jhauser.us/arithmetic/HardFloat.html](http://www.jhauser.us/arithmetic/HardFloat.html)

So all of these RISC-Vs should have optional FPU support based on HardFloat
:-) (not that I have any idea of the size of HardFloat).

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fit2rule
This is really great work and quite well documented .. I can't help but wonder
at the .. high granularity .. applications in the audio-synthesis world, where
SERV's could be deployed at scale to assist in timbrality .. I guess this
might be very useful in a DSP context for things other than MI-synthesis too
.. definitely going to check back to see where this goes ..

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ryanmjacobs
Wow! This looks _really, really_ promising. I can't believe they got it to run
on the 5280-logic-cell Lattice chip. This is perfect for a low-cost FPGA +
soft-core platform.

I'm going to try out gcc RISC-V compilation and see if I can get a program to
boot!

Shameless plug: We use the 5280 LC chip for
[https://webfpga.io/kickstarter](https://webfpga.io/kickstarter)

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ngcc_hk
Wonder the hardware. Gone a few ice around but it is either 1k or 8k. Is that
core workable on these?

