
SiFive Introduces 7 Series RISC-V Cores with E7, S7 and the U7 Series - pepsi
https://www.cnx-software.com/2018/11/02/sifive-7-series-risc-v-cores-e76-s76-u74/
======
gnulinux
When can I buy an affordable, complete RISC-V computer? I've been long
planning to cook my own with FPGA but it seems like soon we'll start getting
affordable RISC-V CPUs with other utility support?

~~~
qlk1123
With QEMU you can already do amazing things. Every component required by Linux
From Scratch has been stable, and you can get a Fedora/Debian image for that
as well.

~~~
gnulinux
I know QEMU works, I wrote a small kernel using RISC-V and just want to see it
on bare metal.

------
mhb
HiFive1 - Arduino RISC-V Dev Board

The HiFive1 is a low-cost, Arduino-compatible development board featuring the
Freedom E310 making it the best way to start prototyping and developing your
RISC‑V applications. Not only can the HiFive1 help build RISC-V platforms, but
it is also the first commercially available option to do so! The HiFive1 can
simply be plugged into your computer via the micro USB port located to the
front of the board. Additionally, the HiFive1 comes programmed with a simple
bootloader and a demo software, that way you aren’t restricted to the Arduino
IDE if you don’t choose to do so.

[https://www.sparkfun.com/products/15026](https://www.sparkfun.com/products/15026)

------
PinkMilkshake
I've only had a passing interest in learning assembly. It's always been in the
"maybe one day" category.

But after learning about how small the RISC-V instruction set is (less than 50
apparently, but I can't find a citation for that anywhere), I'm far more
motivated to get into it.

~~~
Posibyte
I recommend the 6502[1] if you're just starting. What you learn applies almost
everywhere, and it's very much a what-you-write-is-what-happens sort of
processor. No branch prediction, no caches, no fancy features. Its op-set is
very small and highly expressive. They still make them, in fact.

That said, whether you choose to start with it or RISC-V, from personal
experience SiFive's implementations are phenomenal. I used one of their free-
implementations, and I was blown away by how easy it was to use their
automated tools to build a core exactly the way I wanted. Not as easy as
generating a NIOS core, but much more capable. With an Artix-7, I had a very
capable low-range processor in about an hour.

[1]:
[https://skilldrick.github.io/easy6502/](https://skilldrick.github.io/easy6502/)

~~~
masklinn
If you just want to dip your hand in, chip8 is also a good starting point (if
even less useful than 6502): where 6502 has about 80 actual opcodes acrosss
~50 mnemonics
([https://en.wikipedia.org/wiki/MOS_Technology_6502#Assembly_l...](https://en.wikipedia.org/wiki/MOS_Technology_6502#Assembly_language_instructions))
chip8 has 35 opcodes across 19 mnemonics (ADD, AND, CALL, CLS, DRW, JP, LD,
OR, RET, RND, SE, SHL, SHR, SKNP, SKP, SNE, SUB, SUBN, XOR).

------
jbeard4
I am pretty excited about RISC-V. Hoping to see a v8 JavaScript and Node.js
port in the future.

~~~
thethirdone
That shouldn't be super hard. I don't think there is much assembly in either.
And C can be compiled to RISC-V already.

My only experience porting node was to a specialized ARM system a while ago,
so ARM support may have been already built in or things may have changed.

edit: as people have commented, there indeed is a fair amount of arch specific
stuff for reference the mips directory
[https://github.com/v8/v8/tree/master/src/mips64](https://github.com/v8/v8/tree/master/src/mips64)

~~~
comex
V8 has a JIT, which is always going to require work to port to a new
architecture. But the new-ish TurboFan backend is supposed to have the
architecture-dependent parts relatively well factored out[1], so it's not as
hard as it might be.

[https://docs.google.com/presentation/d/1_eLlVzcj94_G4r9j9d_L...](https://docs.google.com/presentation/d/1_eLlVzcj94_G4r9j9d_Lj5HRKFnq6jgpuPJtnmIBs88)

------
brianolson
SiFive press release here: [https://www.sifive.com/press/sifive-core-
ip-7-series-creates...](https://www.sifive.com/press/sifive-core-ip-7-series-
creates-new-class-of-embedded)

------
aidenn0
The M7 is an out-of-order processor, these all look to be in-order. Many
artificial benchmarks (including Dhrystone) are very forgiving of in-order
stages, so I would expect this to underperform relatively to a similarly
benchmarked M7.

~~~
Zeetah
M7 is actually an in-order processor. It does have six-stage dual-issue
pipeline.

~~~
aidenn0
Oh you're right. It has speculative execution, but is otherwise strictly in-
order, my mistake.

------
ivoras
Hmm, does it really have only 16 KiB of RAM or am I misinterpreting the spec?

What would be the use case for a 320 MHz processor with 16 KiB RAM? Even
ESP8266 has 80 KiB and runs at 80 MHz.

~~~
SloopJon
The only place I see that mentions 16 KB is the instruction cache on the S7
monitor core. Apart from cache, it doesn't look like any of these include RAM.

~~~
crankylinuxuser
That's fairly standard. The problem there is going to be attaching ddr3
modules to a board. BGA is a pain in the ass for anything past 10x10 using a
toaster oven. And for doing it "right" you really need xray QA.

------
jabl
Is this based on the open source rocket chip, or is it a proprietary design?

