

Wasted IC Designs - kumarski
http://www.kumar.vc/tesla-would-cry-about-these-ic-designs/

======
nkurz
Cached:
[http://webcache.googleusercontent.com/search?q=cache%3Awww.k...](http://webcache.googleusercontent.com/search?q=cache%3Awww.kumar.vc%2Ftesla-
would-cry-about-these-ic-designs%2F)

I presume he means Nikola Tesla
([http://en.wikipedia.org/wiki/Nikola_Tesla](http://en.wikipedia.org/wiki/Nikola_Tesla))
rather than the electric car company
([http://www.teslamotors.com](http://www.teslamotors.com)), but I still don't
understand the reference. Is there more to it than the general notion than Mr.
Tesla had many ideas that never reached fruition?

~~~
kumarski
I had an anecdote about the failure prone nature of IC design and Tesla's
failed commercialization attempts.

------
yongjik
I'm ignorant on IC designs, but this whole post sounds like a big "solution in
search of a problem" to me. Could someone enlighten us on whether there are
really enough abandoned IC designs that are economically viable?

~~~
kumarski
The idea is that there's 10-20 percent of useful IC designs. Additionally,
efabless provides the environment to design, test, and simulate the IC with
respect to the foundry/fab.

~~~
kumarski
I should have probably outlined why it's meaningful, or why I'm taking a risk
on it.

\- IC design software as it currently stands has no version control. (I was
shocked at this...)

\- IC designs are built in a closed box.

\- There's an absurdly high level of unsellable designs. This occurs because
there's no customer feedback loop and you can't predict the direction of the
IC market.

Additionally, I'm pretty stoked about things like: prefundia.com
kickstarter.com

Because... they mitigate production risk.

The cost of failure in IC design is pretty big. Efabless gives away the
software part of it for free to IC designers.

~~~
ChuckMcM
This doesn't really match my understanding of things, this is what I'm
familiar with.

IC design software is too loose a term. Most, if not all, integrated circuits
are designed these days using a hardware description language (VHDL and
Verilog being most popular) and those languages/files have exactly the same
level of source code control that any source code does, git, mercurial, CVS,
etc. They are just text files, they have a build and a test processes.

Further integrated circuits can be collaboratively designed, look at
FPGACPU.org as an interesting example.

This one is really hard to wrap my head around:

CLAIM: There is an absurdly high level of unsalable designs.

EVIDENCE: This occurs because there's no customer feedback loop and you can't
predict the direction of the IC market.

Bad chip designs exist for the same reason that bad software exists, some
people just produce bad designs. I think you were trying to argue that there
are good designs that didn't get produced, but that is true for any design.

So that said lets talk about what _is_ hard.

It is hard for me, as an individual, to get a wafer start at a fab. It is hard
for me as an individual to _generate_ masks for a specific process.

It is hard for me, as an individual, to get the circuit parameters for a
particular process and so that I can do both a good layout and can tweak my
masks for good yield.

It is hard for me, as an individual, to get my processed wafers diced, tested,
and packaged.

Historically, getting all of those things done to convert a working chip
design from simulation to testable parts, has been a few million dollars. And
at the end of those millions one has (wafer size / die size ) * layout
efficency * process yield * testing yield number of parts. These are divided
up into one or more 'bins' (if they are still usable at different frequencies
or voltages). And when I divide that number of chips by the amount of money
I've spent, I've got a price per chip that has to be something the market will
be willing to pay.

That is both a lot of hoops, and sitting down for betting one round costs a
few million.

So what, exactly, is efabless.com de-risking? Unlike circuit boards, you can't
easily put several different IC designs on the same chip and expect a fixed
yield across them (sort of the OSHPark model). You can do what some folks have
done which is buy "excess" capacity on older generation fabs (like Atmel's)
and get a discount because you're helping them keep things running, but its
still quite expensive.

The cost of failure in IC design is nearly zero. Once you've done the
simulations you've just burned CPU cycles up to that point. If the process is
_well characterized_ there is exactly zero reason for a chip you produce to
not work when it comes out the other end. A long time friend from my Intel
days remarked that it used to be news if a chip worked the first time, now it
is news if it _doesn 't_ work the first time you bake it.

I can see a challenge that low run rate chips are too expensive for the market
they are trying to serve (which is why FPGAs have been growing in leaps and
bounds). The original solution, ASICs which are less space efficient than
bespoke designs are great for taking an FPGA design into production. So the
modern "chip" process has evolved to design it, ship your MVP on FPGAs, if you
get sufficient traction you do a two or three metal layer ASIC, if you get
even more traction you plug in the process design library and do layout for a
specific process. Where does efabless fit into that?

~~~
GregBuchholz
>So the modern "chip" process has evolved to design it, ship your MVP on
FPGAs, if you get sufficient traction you do a two or three metal layer ASIC,
if you get even more traction you plug in the process design library and do
layout for a specific process. Where does efabless fit into that?

I don't know what efabless is all about, but I could see several areas that
don't fit your mold. Analog, RF, ultra low power, sensors (optical, etc.),
switching power supplies, MEMS, etc..

~~~
ChuckMcM
That is a really awesome point. I don't know how you could even _begin_ to
cost effectively get the price of designing your own circuit geometries into
peoples hands ala kickstarter. Not to mention how to simulate the physics of
those devices prior to fabrication.

------
adyus
While the idea seems interesting, a quick read of this post reveals no
connection whatsoever to Tesla. I'm baffled by the title.

I wonder if this idea could also be applied to other types of work-intensive
designs that simply were ahead of their time and could be resurrected with
today's tech, such as car design.

~~~
dang
You're right—the title was linkbait. We changed it in accordance with the HN
guidelines.

~~~
kumarski
It wasn't. One version of the draft of the blog post mentioned Nicola Tesla
and his inability to commercialize successfully. I took it out because I
thought it detracted.

I should have changed the title accordingly.

------
sp332
Cache
[http://webcache.googleusercontent.com/search?q=cache:http://...](http://webcache.googleusercontent.com/search?q=cache:http://www.kumar.vc/tesla-
would-cry-about-these-ic-designs/&strip=0) Edit: The pictures are still
loading even though the blog is down.

------
bsder
This doesn't fix IC design. The fix to IC design is simple:

Free design tools.

Without free tools, you can't "carry" a design until it becomes economically
viable because you have to pay Cadence/Mentor/etc. continuously.

The problem is that the number of people who can make such tools borders on
zero to begin with. Combine that with the fact that most companies will pay
you quite a bit if you are that good at ECAD programming, and you basically
have no programmers available.

(For a good example, look at the state of free PCB tools vs the ones you buy.
VLSI is at least an order of magnitude few users and programmers than _THAT_.)

~~~
kumarski
These are free.

~~~
bsder
And where can I download these tools?

This isn't free. You are attempting to extract rent from already cost-sunk
designs rather than enabling a blossoming of new design ecosystem.

~~~
kumarski
Not yet downloadable.

This is free. Okay, let's suppose you want to create an IC from scratch, we'll
support that too and allow you to use our design ecosystem for free too.

Simply message me.

------
solarmist
Site's rate limiting. Can anyone describe what this is?

------
sitkack
The company that the post mentions, EFabless, has an HN instance setup for IC
related news.

[http://clktok.efabless.com/](http://clktok.efabless.com/)

~~~
arbuge
Is the HN software available to third parties then?

~~~
kumarski
[http://stackoverflow.com/questions/4285617/how-do-i-
install-...](http://stackoverflow.com/questions/4285617/how-do-i-install-arc-
to-get-a-hacker-news-clone-website)

~~~
sitkack
Although for nearly the same effort one can get reddit up and running,
[https://github.com/reddit/reddit](https://github.com/reddit/reddit)

And then with
[http://redditenhancementsuite.com/](http://redditenhancementsuite.com/) one
has a pretty good app.

------
jrockway
He probably wouldn't be too happy about the site's ability to handle the HN
effect either ;)

~~~
kumarski
I'm very unhappy about this. arghh. Could you post a screenshot if an error
appears. Thanks mucho.

~~~
michaelt
Got this a while ago (may be fixed now)
[https://imgur.com/ViY80BH](https://imgur.com/ViY80BH)

~~~
kumarski
Thank you Michael. :)

