
SiFive to Introduce New RISC-V Processor Architecture and RISC-V PC - abbeyj
https://www.businesswire.com/news/home/20200914005108/en/SiFive-To-Introduce-New-RISC-V-Processor-Architecture-and-RISC-V-PC-at-Linley-Fall-Virtual-Processor-Conference
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lsb
It looks like SiFive is making a vector processor, to potentially compete with
GPUs (Nvidia makes chips with dozens of multiprocessors on them, each with
arbitrarily many cores)

Super exciting!

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josemanuel
I’m getting confused. You mention this is a product to eventually compete with
GPUs. So is this a quasi-gpu that’s being announced? Will there be a opengl or
vulkan driver to interface with it? Is this a regular accelerator? Your
comment does not add much clarity.

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colejohnson66
If it is in fact a CPU designed to be used like a GPU, that’d be very akin to
Intel’s (dead) Project Larabee.[0] As I understand it, it was supposed to be a
GPGPU[a] that internally was just an x86-64 processor with massive vector
units. So, in theory, one could offload practically an _entire game_ onto a
Larabee card (save for IO probably) and do computations there. Compare that to
a GPU where computations must be sent back and forth between the CPU and GPU.

Linus Sebastion (of LinusTechTips) managed to get his hands on one and made a
video on it.[1] It’s been a while since I’ve seen the video, but, IIRC, they
weren’t able to get it to work, so the video was a bit of a letdown.

[0]:
[https://en.wikipedia.org/wiki/Larrabee_(microarchitecture)](https://en.wikipedia.org/wiki/Larrabee_\(microarchitecture\))

[1]:
[https://www.youtube.com/watch?v=um-1fAVU1OQ](https://www.youtube.com/watch?v=um-1fAVU1OQ)

[a]: general purpose GPU

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josemanuel
It all reads extremely vague. What do these all mean? Is there anything in R-V
other than the constant hype propelled by sifive?!

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FullyFunctional
What is "R-V"? Please use correct non-ambiguous terminology.

The press release says nothing, but 740 suggest it's based on the 74 which is
a dual issue core with the vector extension. The latter is a big deal
(basically doubles the silicon area for one metric), but ISTM that it's not
the OoO core, so not in the same class as eg. BOOM.

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colejohnson66
“R-V” is pretty clearly “RISC V”

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FullyFunctional
It's not clear to me. The big new thing in the 74 core is the vector extension
(thus, RV64GCV) and in the context of the question it might very well have
been that the OP was asking about. Clear and effective communication benefits
from the absence of ambiguity lest we just end up with a bunch of TLAs that
ATM seems FTW, but might raise a "WTF" for someone else. YMMV.

EDIT: reworded

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josemanuel
Did I touch a sore point when I wrote R-V? From your reaction It seems like I
did. Is the term R-V perceived as detrimental? Does R-V not sound cool? I
think it does.

