
LMARV-1: A RISC-V processor you can see [video] - Retr0spectrum
https://www.youtube.com/watch?v=yLs_NRwu1Y4
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turblety
Robert Baruch has a bunch of great videos and if you look at the website for
his "Project 54/74" [1] he spends lots of time taking high resolution photos
of decapped processors. Really, it's an amazing educational experience. If you
guys can spare just a few dollars/pounds/whatever a month he has a Patreon
page [2] where you can donate to help him continue his research.

1\.
[https://project5474.org/index.php?title=Main_Page](https://project5474.org/index.php?title=Main_Page)

2\.
[https://www.patreon.com/user?u=3190442](https://www.patreon.com/user?u=3190442)

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the-dude
Is [2] the canonical link for a Patreon user? Really?

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duncan_bayne
AFAIK, yes.

Meanwhile, perhaps you should send some ETH to Elonn Musk?

[http://nymag.com/selectall/2018/02/how-to-make-
usd6-500-by-p...](http://nymag.com/selectall/2018/02/how-to-make-usd6-500-by-
pretending-to-be-elon-musk-on-twitter.html)

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phkahler
I keep having an odd thought. What if each register was paired with an ALU?
Much more circuitry, but you'd only need two busses instead of three - one for
an operand and one for the result. The other operand would be local to the
ALU. Interconnect would have to be exceptionally expensive for this to make
any sense, but I am amused at the idea anyway.

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nickpsecurity
Although neat in its own right, anyone whose looking at this project out of
concern for subversion should know there's still process nodes in use that you
can see with your own eyes. Well, you dissolve coating around random chips to
put them under a microscope. You're limited to 350nm and up if I'm right that
the property ended around 250nm. There were also 500nm and 700nm available
when I last looked at shuttle runs.

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rijoja
If one wanted to go about and take the easy way out and instead of using
discrete chips going with an FPGA. Which FPGA-chip / board would be a suitable
option?

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rwmj
At the very top end, the VC707 ($3500) will let you run a quad core 64 bit
RISC-V at about 100 MHz. At the bottom end you'd be looking at one of the
boards supported by PicoRV32
([https://github.com/cliffordwolf/picorv32](https://github.com/cliffordwolf/picorv32)),
and some of those are as little as $100. If you want flashing lights as in the
video then the Nexys 4 DDR might be a good compromise (but you'd have to
program the lights to flash yourself).

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Annatar
100 MHz, why so slow?

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rwmj
The very quick explanation is that when you have lots of long wires (and
especially wires of different lengths) between the components of your chip,
you have to wait for all the signals on a bus to arrive before you can latch
them into the component at the next clock edge, and this slows down the
achievable clock speeds.

To explain this properly would require explaining how FPGAs work and how they
differ from ASICs. There's a rather good talk by Uli Drepper which covers some
FPGA basics:
[https://www.youtube.com/watch?v=Q-SkioVSZWw](https://www.youtube.com/watch?v=Q-SkioVSZWw)

In any case 100 MHz for an FPGA processor design is not slow for an FPGA, nor
is it something that can be solved with more money (bigger and smaller FPGAs
suffer the same effect). For GHz designs you have to implement an ASIC. For
comparison, SiFive's FPGA implementation runs at 100 MHz but their ASIC of
near-exactly the same design runs at 1.5 GHz.

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brudgers
For one reason or another, neither of which matter, I was reminded of MMIX:
[https://cs.stanford.edu/~knuth/mmix.html](https://cs.stanford.edu/~knuth/mmix.html)

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jacksmith21006
Love this video but wish waited so I could watch all of them together.

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jasonkostempski
Does everyone say "RISC 5"?

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cesarb
Yes, because the V in RISC-V is the Roman numeral five. See the Introduction
chapter of [https://content.riscv.org/wp-
content/uploads/2017/05/riscv-s...](https://content.riscv.org/wp-
content/uploads/2017/05/riscv-spec-v2.2.pdf) (the very first sentence of that
chapter, in fact, mentions the pronounciation: "RISC-V (pronounced “risk-
five”) is a new instruction set architecture (ISA) [...]").

