
RISC-V based 64-bit quad-core application processor - wanderingjew
https://www.sifive.com/products/coreplex-risc-v-ip/u54-mc/
======
angrygoat
I'm quite excited about Risc-V as a platform - particularly security and
trust-wise. It's great to see that we'll be getting competitive CPUs soon.

Open hardware, implementing an open architecture, which can run open source
software with reproducible builds. A huge win when we're facing pervasive
surveillance hard-wired into current commodity systems.

~~~
Nokinside
Security and trust-wise RISC-V means nothing.

RISC-V is just open instruction set. Below the instruction set is
microarchitecture.

Some have developed low performance free microarchitectures for Risc-V but
same applies to other instruction sets also. You can develop open and secure
X86 microarchitecture if you want.

High performance microarchitecture costs hundreds of millions of dollars to
develop. Someone may develop competitive RISC-V CPU someday but it will not
have open microarchitecture. AMD and Nvidia are examples of fabless companies
who develop and sell proprietary microarchitectures. Thinking that someone
develops open platform that competes with them is not realistic.

SiFive Coreplex IP is good for microcontrollers and alike and relatively
transparent but there are similar microcontroller cores available from ARM
with similar transparency.

~~~
throwaway613834
> You can develop open and secure X86 microarchitecture if you want.

Apparently there are patent landmines you have to traverse first.

~~~
Nokinside
Instruction set can't be patented. Intel tries to patent ways to implement and
functions those instructions carry.

RISC-V will have less problems with those kind of patents, but it's impossible
to design high-end microarchitecture without cross-licensing.

I may sound negative, but I'm actually positive about RISC-V in embedded and
IoT arena. People just attach too much hype for the architecture.

~~~
verall
> Instruction set can't be pantented

This is simply false, as far as Intel is concerned. You can't even emulate x86
(therefore infringing 0 hardware patents) without expected heavy litigation
from Intel.

AFAIK the actual x86 patents have expired but none of the extensions have
(x86-64, SSE, ...)

~~~
Nokinside
Intel naturally tries to threaten and extend patents as much as they can. But
they ISA itself can't be patented.

If you look their actual patents, they are all patents on implementation
details or attempts to patent functions that instructions do.

~~~
em3rgent0rdr
> "Intel naturally tries to threaten and extend patents as much as they can.
> But they ISA itself can't be patented."

It is practically impossible to implement these extensions, such as SSE
variants, without intel being able to make a case against you. So even if
theoretically the ISA can't be patented, for all practical purposes they have
the legal power to effectively prohibit a 3rd-party from implementing an x86
core.

------
saosebastiao
AFACT, the only non-incremental innovations in CPU architecture these days is
open source commoditization (the RISC-V approach) and taking VLIW to the
extreme (the Mill Computing approach). Maybe we've hit diminishing returns,
but both of those ideas still seem super promising to me.

The baffling thing is that we've got VC money coming out of our ears. They're
funding unicorns with no hope of returns and funding every single uber-for-x
idea under the sun. And yet it seems like both of these approaches have
received almost zero funding in comparison. How is it that Mill Computing and
SiFive (or any other RISC-V commercialization company), have not received
billions of dolllars in venture capital yet?

~~~
wmf
VCs invest in monopolies, not commoditization.

~~~
microcolonel
Customers buy into commodities when they are competitive with the monopolies.

VCs invest in ventures, and if those ventures are making money I don't think
the they care what kind of market you're competing in.

------
phkahler
The EE-times article is better IMHO. They hint at some SiFive customers.
There's also a quote about embedded risc-v taking off already - if so I think
we should see these appearing next year.

[https://www.eetimes.com/document.asp?doc_id=1332398](https://www.eetimes.com/document.asp?doc_id=1332398)

------
gioele
> U54-MC Coreplex IP is the world’s first RISC-V based 64-bit quad-core
> application processor, supporting full-featured operating systems such as
> Linux.

Isn't the (still in draft state) Privileged ISA needed to implement a UNIX-
like OS such as Linux?

~~~
_chris_
The current version (v1.10) should be forward-compatible, and I believe is
expected to be fully ratified in the next two months. There has been very
little churn on it for a while now.

[Edit: RISC-V Linux is being upstreamed, and rocket-chip has been running
Linux for years.]

------
Timothycquinn
Looks awesome. Seems like this hardware may be the start of a pivot back
towards RISC for general computing.

Anybody have an idea if work has started on build of OpenBSD or FreeBSD for
Risc-v? Would make an excellent chip for building super secure network edge
devices or FreeNAS box.

~~~
userbinator
_Seems like this hardware may be the start of a pivot back towards RISC for
general computing._

I doubt it. RISC-V will probably be seen more as "truly free and open MIPS",
and maybe eventually start growing CISC-ish extensions --- they will have to
if they want to become/remain competitive with other more popular
architectures. Even ARM has become more CISC-y with the introduction of more
special-purpose instructions.

 _Would make an excellent chip for building super secure network edge devices
or FreeNAS box._

That is where I think RISC-V will find a lot of adoption --- since many low-
end routers and other network devices already use MIPS (and have barely
adequate performance.)

~~~
microcolonel
I don't think there's really any reason to think it won't take off in the
datacenter, on Chromebooks, on Android devices, and network/embedded equipment
as you mention.

Each of these will have a different timeline, but these days there are major
markets which are more agnostic to ISA than they were five years ago.

The inherent commodity nature of designs and silicon based on a royalty-free
ISA will drive down prices to the limits of design and material process, which
will drive adoption.

------
rightos
Very interesting, any information about a target price range?

~~~
opencl
This is an IP core rather than an actual SoC so the pricing will obviously
depend on what else gets packaged with it, but based on the core+caches area
of 0.538mm^2 on 28nm it should be competitive with the Cortex A7/A53/A35. As
seen in Allwinner A64, Raspberry Pi, etc. It does say 2MB of L2 cache whereas
most quad A53 SoCs I've seen have 512KB so the cost is probably going to be a
bit higher from that. But full SoCs are likely going to be in the $5-$10
range.

~~~
petra
The raw cost of the coreplex's silicon is probably ~7 cents. of course there's
extra stuff that goes into a soc, but why do you assume it will go from 7
cents to $5-$10 ? is it because the cost of the A53 etc is insignificant ?

~~~
pjc50
Since when have the silicon costs been the slightest bit relevant to IC
pricing? It's all about volume and recouping R&D costs and other NRE.

~~~
monocasa
Yeah, but this core is open source, which significantly reduces the NRE costs
for most integrators.

~~~
opencl
The RISC-V ISA is free (i.e. you can design your own core without paying
royalties to a company like ARM, which is what SiFive has done here) but this
is a normal paid-for IP core. They do have some SoCs with a "free and open
platform specification" but there's no public repo to download their Verilog
code from.

If you want an actual open source RISC-V core, see:
[https://github.com/lowRISC/lowrisc-chip](https://github.com/lowRISC/lowrisc-
chip)

~~~
asb
Hi, I'm one of the co-founders of the lowRISC project. You're right that
SiFive's licensing arrangements can be somewhat confusing. Although they sell
licenses (like [https://static.dev.sifive.com/business/sifive-license-and-
su...](https://static.dev.sifive.com/business/sifive-license-and-support-
agreement-sample-e51-20170602.pdf)) which look like a typical proprietary IP
agreement, the SiFive Coreplex IP is a derivative of the open-source Rocket
chip generator. SiFive was founded by a team from Berkeley who produced
Rocket, and are almost certainly now the biggest contributor to ongoing Rocket
development.

~~~
monocasa
Off topic question: has there been any work yet on a TileLink IOMMU? I was
playing around with writing one, but didn't want to put in the effort if you
guys or SiFive were just around the corner from releasing your own.

~~~
asb
It's not something we've worked on so far at lowRISC. If SiFive have been
working on something in that area I haven't seen them talk about it publicly.

Sounds like a great project, if you do start working on it I'd love to discuss
more.

------
snvzz
Did I miss the privileged ISA specification passing?

