
Transport-Triggered Architectures - akakievich
http://tce.cs.tut.fi/tta.html
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BillBohan
This is very interesting but does not appear to be helpful for the development
of my TTA processor design. It appears that this project aims for more
parallelism similar to VLIW than my simple MOVE architecture targets.

I would very much appreciate feedback and suggestions regarding my preliminary
specifications which will be changing in the near future (before year's end)
to include MUL, DIV, and floating point support. I really want to have a firm
specification before proceeding with the VHDL implementation.

You can view what I have done at
[https://github.com/BillBohan/NISC](https://github.com/BillBohan/NISC) .

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justaaron
Which of course, sounds awesome. Are there any implementations/examples we can
check out? Does this relate to the concept of a "systolic array" in some way?

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pkaye
I know the Maxim MaxQ is a microcontroller that implements a transport
triggered architecture.

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userbinator
Maxim seems to have quietly EOL'd most if not all of them.

