
6th RISC-V Workshop Proceedings - deepnotderp
https://riscv.org/2017/05/6th-risc-v-workshop-proceedings/
======
CodesInChaos
One thing that worries me about RISC-V is how much encoding space for (major)
opcodes they already used up.

There are 7 bits to encode the opcodes. Of those 128 possible values, 3/4 are
used for 16-bit compressed/thumb instructions.

The remaining 32 values are allocated as follows:

* 4 are for custom instructions * 4 are for larger than 32-bit instructions * 21 are already used * 3 are reserved for future use

While there is some space for minor opcodes (encoded via func3/func7) inside
of the already allocated major opcodes, this allocation seems overly generous
to me considering how young the instruction set still is.

I would have felt far more comfortable with compressed instructions only
taking 1/2 instead of 3/4 of the total available space.

~~~
rwmj
RISC-V isn't limited to 32 bit instructions. In fact RISC-V insns are variable
length, and as well as 16 bit (compressed extension) they can be longer than
32 bits -- in fact much much longer.

More details in section 1.2 of this document: [https://riscv.org/wp-
content/plugins/pdf-viewer/stable/web/v...](https://riscv.org/wp-
content/plugins/pdf-
viewer/stable/web/viewer.html?file=https://content.riscv.org/wp-
content/uploads/2017/05/riscv-spec-v2.2.pdf)

------
inetknght
What RISC-V needs for high adoption, is a well-marketed product similar to the
Raspberry Pi.

Give me an open source model board with a kernel, network, graphics,
peripherals, and general-purpose I/O. Give it to me cheap. Give it to me with
a desktop environment.

Give me example simple real-world use cases ("build a ping response box!",
"build a home video recorder!", "build an internet-enabled light switch!",
"build a sound amp!", "build a robot to take over the world!", etc) and the
hardware and software for a DIY-er to... do it by themselves.

Give people hardware, software, and examples (monkey see, monkey do), and
you'll find more people adopting RISC-V.

~~~
ajross
That's a big ask. Right now RISC-V has a handful of open source CPU cores.
There's no open source network, graphics, peripheral and GPIO hardware that
can be cheaply plugged into a synthesized design that can be sold at the price
you want. Which is to say, while there's plenty of stuff out there that
someone made work on a FPGA once, there's nothing with a track record and
validation/driver stack ready that you can throw into your tools and expect to
get a working chip with. And that's what those SoCs you find in the Pi and
similar boards need if you want to get them out at the small-integer-dollars
price point: no-brainer existing IP that won't surprise anyone along the
manufacturing and support chain.

~~~
zkms
> There's no open source network, graphics, peripheral and GPIO hardware that
> can be cheaply plugged into a synthesized design that can be sold at the
> price you want.

Why not PCIe? Aren't there already a bunch of design/validation/verification
tools for it? A RISC-V CPU with just a bunch of PCIe lanes (and a couple of
channels of fast DDR4) coming off of it (and maybe an IOMMU) would be a lot
easier to integrate with existing hardware, rather than trying to recreate
open-source equivalents of modern GPUs and network hardware.

~~~
k0ngo
I like the idea, but unfortunately PCIe isn't easy or cheap to implement on
silicon. The problem is that you'd need the PHY, which is the high speed,
analog interface, and that needs to be designed and tuned for the fab and
process node you're targeting. In practice the only sane way to get PCIe on
your chip is to buy a PCIe IP block from Faraday or Synopsys. The same goes
for SATA. Ethernet and USB on the other hand is available in discrete PHY
chips, so writing some open-source controller RTL for RGMII and ULPI is much
more reasonable for an open-source chip. (Obviously, if someone would cough up
the money for taping out a RISC-V SoC with PCIe PHYs onboard and make it in a
large enough volume that the price gets down to reasonable levels, I'd be
buying a bunch of'em.)

------
nl
The NVidia slidedeck is pretty interesting: [https://riscv.org/wp-
content/uploads/2017/05/Tue1345pm-NVIDI...](https://riscv.org/wp-
content/uploads/2017/05/Tue1345pm-NVIDIA-Sijstermans.pdf)

~~~
jacquesm
It is actually. Lots of interesting tidbits.

Also this, which I completely missed:

[http://www.cnbc.com/2016/09/20/chinese-company-hacks-
tesla-c...](http://www.cnbc.com/2016/09/20/chinese-company-hacks-tesla-car-
remotely.html)

~~~
akavel
Did you mean some other link? A Tesla story seems totally unrelated

 _edit:_ ok, I get it now: the slidedeck mentions the above Tesla story in a
slide about security.

~~~
jacquesm
That link is in the presentation.

------
pulse7
Folks, you must watch this:
[https://www.youtube.com/watch?v=1FtEGIp3a_M](https://www.youtube.com/watch?v=1FtEGIp3a_M)

~~~
kobeya
Why?

~~~
pulse7
"50 years of Computer Architecture in about 15 minutes" \+ current state and
future

~~~
MycroftJones
Wow, that video is a lecture by one of the leaders of RISC-V. I had no idea
there was a RISC-2 and RISC-3, and that they were optimized for SmallTalk and
Lisp respectively. Wonder what Alan Kay has to say about RISC-V? He's been
banging on about how Intel messed up their chip design, does he approve of
RISC-V? Seems like the perfect time to get things done right.

------
PedroBatista
At the end of the day, RISC-V will only succeed if I can buy a board where I
can attach some SATA drive, a monitor and keyboard/mouse the same way people
buy some ITX board.

This might be tough to hear for people discussing the ins and outs of RISC-V
and why is so much better than x86 or ARM and the big name sponsors don't make
it any better with the usual tight hugs and lullabies. But you need to put it
in the hands of the people just like "the PC", otherwise it will be a pet
project waiting to be forgotten by everybody other than the nostalgic ones.

~~~
abelsson
There's gazillions of embedded processor cores in every device you own. Your
SSD, network card, phone, motherboard, router, TV, modem, car, fridge, you
name it all have multiple processor cores running some piece of firmware you
never see. RISC-V has a pretty good value proposition for those: an open
standard with no licensing costs with a rapidly maturing software ecosystem.
To say that RISC-V will only succeed if you can attach a monitor to it only
betrays a very narrow view of where processors are actually used.

~~~
pjc50
... most of whom are already using ARM.

Intel - _Intel_ \- tried to compete in the embedded market and has recently
quietly withdrawn several of its products. It's a tougher market than it
sounds, and it's also more conservative than you'd expect.

~~~
petra
Intel didn't really try. You know who did really try ? espressif, with their
famous ESP32.

Or the startups: indie-semi, who sell mcu's built as lego's from multiple
dies, affordably! which allows them to do custom-design and semi-custom design
of mcu's per customer , while offering a large library of standard mcu's.

Or terechip, who built a chip packaging process who can handle dies orders of
magnitude smaller than current systems - opening possibilities for far cheaper
mcu's and other simple chips.

Or even ambiq-micro, which created a way to design mcu's that take ~10x(?)
less power by enabling transistors to work on an extremely low supply voltage.

This is how you compete with entrenched competitors. By doing something they
cannot do.

And Intel ? their fab doesn't even fit mcu's(no flash on logic processes, not
good fit for analog). They had no advantage, no differentiation( maybe besides
their neural network, a feature that didn't seem to attract customers). How
did they expect to win ?

~~~
sqeaky
Its almost as if they expect that just putting chips into a market makes that
market have to buy it, almost as if they have gotten to used to not needing to
compete. How could a chip vendor that has thoroughly cornered a few major
market segments and might be considered to have some amount of monopoly status
ever get into such situation?

------
throwaway000002
I used to be a big champion of RISC-V, just look at my submission history, but
I've become increasingly weary due to SiFive's dubious leadership.

1) It's still impossible for anyone to get their hands on an FE310 chip over
half-a-year on from the release of the HiFive board.

2) They promised open-source cores, but somehow backtracked due to "customer
requests". How does this make any sense? And if so, just have an open-source
version, and a closed-source one that, I dunno, has a SiFive logo on the mask.

I was really inspired by them, now I'm mostly dejected. Still, I'm hoping
someone like ST takes their peripherals and makes an MCU with a RISC-V.

~~~
jackckang
Sorry to hear that you're feeling dejected.

On your questions: 1) We are providing FE310 samples to folks who ask us for
them at info@sifive.com

See our past forum posts for similar requests:
[https://forums.sifive.com/t/assistance-getting-in-contact-
wi...](https://forums.sifive.com/t/assistance-getting-in-contact-with-
sifive/562/6) [https://forums.sifive.com/t/e300-on-the-market-other-sbc-
s-w...](https://forums.sifive.com/t/e300-on-the-market-other-sbc-s-with-
it/421)

2) We do provide both versions, just as you recommended. SiFive continues to
maintain the Rocket repository at [https://github.com/freechipsproject/rocket-
chip](https://github.com/freechipsproject/rocket-chip)

We intend to continue to maintain this core and ensure it's compatible with
any updates to the RISC-V specification.

For commercial customers who do not want to utilize rocket-chip, we are
providing them with other options.

-Jack (from SiFive)

~~~
throwaway000002
Thanks Jack for taking the time to respond.

Keeping the faith alive...

------
childintime
What's needed, and possible, today, is a competitive and relatively simple AVR
or ARM-M0/M3/M4 replacement (with I2S). Such a chip is likely to receive
stellar support from the maker-community.

My gut feeling says that such a chip is likely to come from Samsung, but NXP
and Expressif are also likely candidates. All are RISC-V members.

Anything more complex should wait until the specs are complete.

------
legulere
So I guess the thing currently keeping RISC-V from moving forward is
ratification of the privileged spec, which is planned for end of 2017/2018?

[https://riscv.org/wp-
content/uploads/2017/05/Tue1115-Technic...](https://riscv.org/wp-
content/uploads/2017/05/Tue1115-Technical-Committee-Update.pdf)

~~~
lloydjatkinson
> privileged spec

I _hope_ this refers to ring-0-like instructions such as x86 STI, and not some
kind of OEM/manufacturer "you can only use this set of instructions if you pay
us" type privilege?

~~~
lloydjatkinson
Who on earth is downvoting this? Get a grip

~~~
Dylan16807
They're downvoting because the entirety of your comment was a (baseless) worry
about the definition of a word that would have taken seconds to check.

~~~
lloydjatkinson
Totally have time to read huge PDF's every day.

~~~
Dylan16807
It has a section in the wikipedia page, which is right under that PDF in the
search results.

Alternatively in the PDF you would only need to look at the "Introduction"
section for a minute.

------
MycroftJones
So, how does RISC-V compare with Donald Knuth's MMIX instruction set? Did they
use it as a starting base? Consider it at all? Be cool to program MMIX in
actual hardware.

~~~
renox
What makes you think both are related? AFAIK MMIX isn't a very "practical"
ISA.

~~~
monocasa
Yeah, it has something like 256 64bit GPRs. Not even the big monster CPUs have
that many microarchitectual registers to rename to.

~~~
Veedrac
Well Haswell is 168 integer + 168 FP.

