
Benchmarking boot latency on x86 - luu
http://benyossef.com/benchmarking-boot-latency-on-x86/
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amluto
This article makes the assumption that the TSC is zero at power on and counts
monotonically from then on. The problem is that BIOS vendors know this and
sidings try to game it. I have a machine in which it appears that the BIOS
resets the TSC partway through POST, probably to improve benchmarks.

(I can tell this is happening because they only reset it on one core, which
breaks all kinds of things.)

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yuhong
I remember the advice to disable the HPET when Ryzen was released, which also
reminds me of this:
[https://lkml.org/lkml/2015/6/3/4](https://lkml.org/lkml/2015/6/3/4)

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kabdib
Generally speaking, POST will dominate over OS boot time on modern server
hardware. POST is on the order of minutes, _tens of minutes_ for machines with
terabytes of memory . . . and that's with the "fast boot" option selected.

I fondly remember the days of desktop systems with their OSes in ROM. You
could do "Reset, user interface" about as fast as you could say the words. The
whole POST stack has lost its way.

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drewg123
The sooner we can get rid of both legy BIOS and EFI in favor of Coreboot or
something like it, the better. My son's x86 based Chromebook boots to a login
screen from cold power off in just a few seconds, and I've always attributed
it to using Coreboot rather than BIOS.

I mostly don't care about boot times (which is saying a lot, as I do FreeBSD
kernel development and reboot server class systems dozens of times a day
sometimes), that's just a minor benefit of Coreboot. The legacy nature of BIOS
and the complexity of EFI both freak me out from a security / stability point
of view. And don't even get me started on the crappy server board vendor's
java kvm / impi tools. Sigh. The whole crappy ecosystem is due for a
disruption.

