
5-Level Paging and 5-Level EPT [pdf] - luu
https://software.intel.com/sites/default/files/managed/2b/80/5-level_paging_white_paper.pdf
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twotwotwo
One reading of this is that Intel wants some future arch to be able to address
huge amounts of NVRAM as if it were RAM.

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ChuckMcM
Of course they do. If their X-Point stuff (or something like it) ever ships,
they will want to put a couple or three terabytes of NVmemory on the otherside
of the frontside bus. If you can do that you can enable some really amazing
systems architectures. Things like a web search engine that consumes less than
a 100W when it isn't serving a request because it can 'wake from sleep' and
answer a query in under 10mS. And it can reboot in just the few seconds needed
to change out the RAM parts of memory and pick up the giant data structure
with the web index already loaded.

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amluto
Prepare for a new set of exploits affecting every major OS except Linux [1]
involving SYSRET to a non-canonical address.

[1] Linux may get a free pass because I'm going to insist on a specific test
case for this issue.

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bogomipz
>"Prepare for a new set of exploits affecting every major OS except Linux [1]
involving SYSRET to a non-canonical address"

Can you elaborate?

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amluto
Here's a good writeup of the original bug:
[https://fail0verflow.com/blog/2012/cve-2012-0217-intel-
sysre...](https://fail0verflow.com/blog/2012/cve-2012-0217-intel-sysret-
freebsd.html)

With the VA width changing, all the fixes for that and related bugs will need
to be updated.

~~~
bogomipz
Oh interesting, thanks for the link.

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bogomipz
The third paragraph of the first page states:

"Virtual-machine monitors (VMMs) use the virtual-machine extensions (VMX) to
support guest software operating in a virtual machine. VMX transitions are
control flow transfers between the VMM and guest software"

Can anyone explain what "control flow transfers" are?

Is this just referring to a per VM context of a core's control path? Kind of
context switch of sorts to to another VM?

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caf
In this context "control flow transfer" refers to the CPU transitioning
between executing VMM code and guest code.

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bogomipz
Thanks!

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jws
I wonder who asked for this? While 640k might not be enough for everyone, 256
terabytes of directly addressable memory seems, suffient to requirements.

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amluto
But 256 terabytes of _disk_ might not be enough and, if you want to address
your disk like it's RAM, you need more address space.

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twotwotwo
Yeah, I had thought in terms of fancy new kinds of NVRAM, but mmap'ing lots of
existing storage (or a mix) is a legit use case sooner.

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rdmsr
Fun fact: physical addresses will still have at most 52 bits, despite linear
address space having up to 57.

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Symmetry
For garbage collectors and other things you really want a randomly selected
number to only infrequently be a valid address.

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tedunangst
How often do garbage collectors look at physical addresses?

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Symmetry
... You're right, physical address bits are totally irrelevant and I was
confused.

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ctcherry
~144 petabytes 128 pebibytes

