
IC Redesign Can Fuel Moore's Law - mindcrime
https://www.eetimes.com/author.asp?section_id=36&doc_id=1334104
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mcguire
" _To reduce power dissipation and power density significantly without
sacrificing computing performance, we need to invent a new transistor, a logic
device that can be an alternative to CMOS. It should operate under very low
supply voltage, much lower than 0.5V—closer to 250mV or even 100mV._ "

Did I miss the part with the ideas about how to do that?

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jerkstate
There is a 2nd page to the article with a chart of different post-CMOS
transistor technologies under development.

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phkahler
Am I mistaken in thinking most of the alternatives are no better than CMOS?
The chart has diagonal lines for a reason - energy times time seems like a
good measure - and most of the alternative are up and/or to the right. Even
CMOS-HP and CMOS-LV are near the same line but trade power for speed. The
option the author seems to like is almost on that same line but in the
slower/lower power area.

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yazaddaruvala
I’m curious, have we moved passed NAND gate only ICs?

Given that it takes many NAND gates to be logically equivalent to the rest of
logic, wouldn’t creating OR and AND gates directly reduce the number of
transistors and therefore help Moore’s Law as well?

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marvy
That's a really good question and I hope someone comes by to answer it. My
guess is that people go beyond this and already design entire adders and stuff
at the transistor level if they think it affects their bottleneck.

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akiselev
I'm not a silicon engineer (I just pretend to be one to get my vendors to skip
me right to their engineers for support) but afaik, Intel has been using weird
phenomenon in semiconductors for useful work for a decade at a "lower level"
than the logic gates. It's why they've managed to stay ahead of competition
even on equivalent nodes and also why they've dug themselves into a corner
(since they cant decouple their fab from IC design to spin off a TSMC
competitor). Their cell library is likely the most specialized on the planet.

I've also heard whispers that the Movidius Myriad II (company later acquired
by Intel) actually used some sort of monte carlo optimization simulations to
design pieces of the chip. Instead of optimizing some of the more specialized
computer/stereo vision algorithms themselves, they threw the testbench at a
really complicated constraint solver/optimizer and it spit out designs based
on physical simulations where the individual units looked nothing like the
logic gates used by a human designer and far more like an analog circuit using
semiconductors.

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yazaddaruvala
Oh that’s cool!

I had read about simulated annealing being used to optimize FPGA logic unit
layouts.

I assumed something similar was used to optimize gate layouts but never
thought about actually optimizing the transistor layouts independent of NAND.
That sounds like a great idea!

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robius
The OP is advocating for MESO - magneto-electric spin–orbit logic.

From Wikipedia - Magneto-Electric Spin-Orbit (MESO) is a technology for
constructing scalable integrated circuits, which utilize spin–orbit
transduction of electrons. It is intended as a replacement for the CMOS
technology. Compared to CMOS, MESO circuits require less energy for switching,
lower operating voltage, and feature a higher integration density.

More here: [https://www.techspot.com/news/77688-intel-envisions-meso-
log...](https://www.techspot.com/news/77688-intel-envisions-meso-logic-
devices-superseding-cmos-tech.html)

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zozbot123
The article states that MESO was developed by the author's research group at
Intel. To be clear, there's nothing especially new about research into beyond-
CMOS tech. But as we all know, it's rare for this sort of research to have
real consequences on actual products.

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smallstepforman
Whats the hold up with Gallium-Arsenid (instead of silicon)? The PN junction
threshold is 0.3V (instead of 0.7V for silicon). This would disipate less heat
than silican based IC’s. Anyone know the technical reasons why GaLliumArsenid
isn’t feasable yet?

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deepnotderp
1\. As we move to lower nodes, high carrier mobility materials such as GaAs
actually perform _worse_ than silicon due to increased source/drain direct
tunneling. See:
[https://ieeexplore.ieee.org/document/7479214](https://ieeexplore.ieee.org/document/7479214)

2\. Most III-V materials have excellent electron mobility, making for great
n-type transistors, but tend to have poor hole mobility which means bad p-type
transistors. Germanium has high hole mobility, and it is already used in very
small quantities to boost performance (see "germanium stressors")

3\. Most III-Vs have no native oxide, nowadays at 28nm onwards due to the use
of high-k dielectrics. However: Until recently, the growth of oxides on III-V
materials without defects such as fermi level pinning was a Hard Problem.

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BostonEnginerd
That’s a great reference!

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gaze
I suspect there's some fruit on the tree of oscillator based computing. In
other words... design memory and gates the way people have been approaching
quantum computing, with no focus on quantum coherence.

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beautifulfreak
"Negative capacitance" designs could help.
[https://www.nature.com/articles/s41565-017-0010-1](https://www.nature.com/articles/s41565-017-0010-1)

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Taniwha
I think the missing part here is "which of these technologies, if any, offer
4-5 generations of improvement?" \- no one's going to make the decision to
move to a new untested process for just one generation

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robius
It's time for the age of graphene. SV -> GV.

