
Is MIPS Dead? Lawsuit, Bankruptcy, Maintainers Leaving and More - abawany
https://www.cnx-software.com/2020/04/22/is-mips-dead-lawsuit-bankruptcy-maintainers-leaving-and-more/
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RcouF1uZ4gsC
MIPS dying is really the end of an era. I think it was the quintessential RISC
processor of the early 90's. IIRC, Windows NT was developed on a MIPS machine
to ensure that inadvertent x86 dependencies did not sneak into the code.

I remember reading a PCWorld article comparing various processors. This was
the time the Pentium came out. If my memory servers, the MIPS won the overall
performance crown vs Pentium, PowerPC, and Alpha AXP.

~~~
skissane
> IIRC, Windows NT was developed on a MIPS machine to ensure that inadvertent
> x86 dependencies did not sneak into the code.

Not MIPS. Windows NT was initially developed on a more obscure RISC
architecture, Intel i860. It was later ported to MIPS though.

~~~
simcop2387
And ported to DEC Alpha too! It's one of my weirdly favorite ports of NT just
because of how little use I believe it ever actually got.

~~~
vetrom
I've seen live Alpha installations of windows NT driving RIPs at large format
printing shops in the 90s. It was also not unheard of at VMS shops.

~~~
alsobrsp
This reads like a Blade Runner quote.

~~~
ncmncm
Those C-beams.

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narrator
KOMDIV-64[1] is still using MIPS. It's improbable that one would encounter
these chips outside of Russia weapons tech though.

[1][https://en.wikipedia.org/wiki/KOMDIV-64](https://en.wikipedia.org/wiki/KOMDIV-64)

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strooper
May be its days are numbered, but MIPS still has significant presence in the
low to medium end routers (Mediatek's MT72xx, Atheros AR7xxx so on).

~~~
dashwav
MIPS still has a very large presence in the education sector as well - MIPS
asm is very easy to learn because of how consistent it's syntax is and the
plethora of open source debuggers as well.

Learning MIPS was what originally got me interested in ASM programming since
we had a class that was focused on MIPS code and another class that had us
build a digital MIPS processor from scratch. The combination of these two
classes really sold me on the magic of super low-level programming.

~~~
333c
Yep, I also learned MIPS in my CS class. It's pretty nice to program in.

~~~
wott
MIPS is typically seen in computer architecture class because it is simple and
regular (at least the original version seen in class). However, for Assembly
programming, MIPS, like (almost?) all RISC instructions sets, is tedious. Give
me any CISC with a generous range of addressing modes, and I take any day over
MIPS/RISC.

We can make a parallel between those low-level ISA and high-level languages: a
language like Lisp is lean and simple so it is taught and presented as good
design (and people who went through that education keep that in memory), but
when it comes to produce real program almost everybody chooses a much less
regular language, which is way more practical. (Same could be said for stack-
based languages like Forth, which present an extremely simple model to
apprehend, but that doesn't mean at all that it is simple to program in.)

Or postfix vs infix for mathematical expressions/calculations. Same principle:
the one which is based on a very simple model is praised by aesthetes, but
almost everybody prefers the other one, which is simpler to use because it is
more natural, despite being based on a more complex model.

In fact, the simplicity of the model is not of much interest for the user, it
just makes the life of the implementer easier. But for 1 implementer, there
are thousands or millions of users, who want ease of use, not ease of
implementation.

~~~
zozbot234
Traditional addressing modes have been largely abandoned because modern
architectures are based on the load-store principle. Simplicity has little to
do with it, and referring to that whole shift in design as "complex" vs.
"simple" instruction sets is a bit of a misnomer. Besides, well-designed
architectures are not exactly lacking in ease-of-use.

~~~
glangdale
This is only "sort of" true.

First, mod-r/m addressing on x86 is fairly traditional and can often save
considerable calculation over a "simpler" addressing mode (given the
opportunities for add-and-scale operations).

Second, treating x86 machines as load/store architectures passes up the
opportunity to achieve improved code density and increased execution bandwidth
from "microfusion" \- this is when a operation (e.g. "add") is done with a
memory operand. Microfusion, for those not familiar with it, allows two
"micro-ops" (aka uops) that originate from the same instruction to be "fused"
\- that is, issued and retired together (even though they are _executed_
separately).

This can occasionally - in code that has already been militantly tuned to an
inch of its life - yield speedups, as Skylake and similar can only issue and
retire 4 uops per cycle. However, there are 8 execution ports (of which only 4
do traditional 'computation'). Carefully designed code can take advantage of
the fact that issue/retire are in the "fused domain" while execute is "unfused
domain" \- so you can sometimes get 4 computations and 1 load per cycle even
on a 4-issue machine.

I was trained on MIPS and Alpha, so of course old habits die hard, and it's
always tempting to go old school and design everything to act as if the
underlying machine is a load-store architecture. However, this (a) isn't
necessary on x86 and (b) often won't be faster.

The other blow against load-store is that a modern o-o-o architecture can
hoist the load and separate it from the use _anyway_ \- and it doesn't have to
consume a named register to do it (it will use a physical register, of course,
but x86 has way more physical registers than it has names for registers). This
of course is a bigger deal for the rather impoverished register count of x86
so it is, in the words of a former Intel colleague on a different topic, a
"cure for a self-inflicted injury".

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joyj2nd
[https://en.wikipedia.org/wiki/Loongson](https://en.wikipedia.org/wiki/Loongson)

~~~
yellowapple
Relevantly, Richard Stallman used to use a Lemote YeeLoong (notebook with a
Loongson MIPS CPU) before he switched to a librebooted ThinkPad T400.

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vardump
ARM and RISC-V have collectively removed any remaining niches (or future
prospects) for MIPS.

~~~
lsllc
Except that there aren't really any practical (affordable!) RISC-V based Linux
boards/modules.

The Onion Omega2S is based on a MediaTek MT7688 (MIPS32LE) and since the
demise of the CHIP-Pro, is really the only inexpensive surface mount Linux SoM
left.

[https://onion.io/store/omega2s/](https://onion.io/store/omega2s/)

~~~
vardump
That's why I said also "future prospects". It's likely RISC-V will for the
very least fill certain niches.

~~~
lsllc
Right, I just hope they do it quickly! I'd love to see a low cost (e.g. RPi
priced) RISC-V based SoM that runs Linux.

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justicezyx
WAVE computing used to be working on CGRA [1] chip as deep learning
accelerators. I got in touch with a few folks there. They apparently failed
that endeavor and pivoted to MIPS.

[1] [https://wavecomp.ai/wp-
content/uploads/2018/12/WP_CGRA.pdf](https://wavecomp.ai/wp-
content/uploads/2018/12/WP_CGRA.pdf)

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CalChris
It's already been bought+sold a few times.

    
    
      (Stanford)
      MIPS Computer Systems
      SGI
      Spun off, IPO
      Imagination
      Tailwood
      Wave
    

I might have missed one.

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tenebrisalietum
I don't think MIPS is going to completely disappear as long as Linux works on
it. Someone somewhere in some country will keep making them as long as the
licensing situation is more favorable for whatever use than ARM or x86. If the
owning company is going bankrupt that means making MIPS CPUs will be cheaper
than ARM or x86.

~~~
DeathArrow
In China they have lots of new MIPS developments based on existing MIPS
architecture.

The question it's not if someone will use some old MIPS ISA in a few years
from now on, the question is if someone will improve the ISA from now on, in
the same way x86 and ARM are consistently being improved.

Some companies are still fabbing old Z80 CPUs, but that's not to say Z80 has a
bright future.

~~~
arnd
Ingenic an Loongson both have architecture licenses and so far have kept
releasing new chips with their own cores on a regular basis, including (in
Loongson's case) some interesting enhancements. Both are also members in the
RISC-V foundation already though, so it seems likely they would in the long
run pivot their instruction sets to that, like others have done before them:
Andes, C-Sky, Cortus, Cobham-Gaisler, NVIDIA, and presumably many more all
keep supporting old products based on their previous designs while doing new
development on RISC-V.

CIP-United still promises to provide enhanced versions of the both the
architecture and the MIPS Warrior cores for the Chinese market, regardless of
what happens to MIPS Technologies. This may seem utterly futile now, but it is
also the very thing that the US Committee on Foreign Investment was trying to
prevent when it required MIPS to be spun out of Imagination Technologies when
that got sold to Chinese investors.

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api
The writing's been on the wall for MIPS for ages. AFAIK it's not better than
ARM in any meaningful way.

~~~
pm321
The creator of ARM speaks well of RISC-V and considers ARM yesterday's old
news and has moved on. Comparing MIPS to ARM in essentials of architecture is
MIPS more beautiful? ARM I understand is a mess that has evolved for its
niche.

~~~
arnd
I find the latest architecture versions are all remarkably similar as they
have all adapted to the same environment:

The old 32-bit Arm (now called Aarch32) was quite different and only somewhat
RISC-like. Arm's Aarch64 however is mostly derived from MIPS64 with a lot of
modernization plus some parts (exception levels) from 32-bit Arm.

MIPSr6 was an attempt of modernizing MIPSr5 by removing all the ugly bits
(delay slots!) but the incompatible instruction encoding prevented it from
being widely adopted. You cannot buy a single MIPSr6 machine that a mainline
Linux runs on.

RISC-V's design looked at all RISC architectures (Berkely RISC, MIPS, SPARC,
Power, Arm, ...) for inspiration and took the best parts of each. Leaving out
all the historic baggage means it's simpler (the manual is a fraction of the
size), but most of the important decisions are the same as in MIPSr6 and
Armv8/Aarch64.

One notable difference is the handling of compressed (16-bit) instructions:
ARMv8/Aarch64 doesn't have them at all (like RISC-I/RISC-II, ARMv3 and
MIPS-V), MIPSr6/microMIPS needs to switch between formats (like ARMv4T through
ARMv6) and in RISC-V they are optional but can be freely mixed (somewhat like
ARMv7 and nanoMIPS).

~~~
ncmncm
It's disappointing that RISC-V designers swallowed myths that resulted in
unpleasant ISA details.

For example, the notion that condition codes interfere with OoO execution has
been repudiated; Power and x86 both now rename condition registers. Lack of
popcount and rotate in the base instruction set are glaring omissions. (That
x86 got popcount late, and that the bitmanip extension will have them if it
ever gets ratified, are no excuse.) It was silly to make the compare
instruction generate a 1 instead of the overwhelmingly more useful ~0.

We only get a new ISA once in a generation. It is tragic when it is wrong.

It is possible, in principle, that popcount and rotate could be added to the
base 16-bit instructions, but I'm not holding my breath.

------
Traster
I remember listening to some guy from ImgTec brag about how MIPS is the 4th
biggest instruction set in the world as if MIPS had like 20% market share
rather 1% or whetever ridiculous market share ImgTec had bought their way
into. That was literally at the peak when ImgTec were on top of the world,
they'd just built a new campus and were spending like there was no tomorrow.
Then Apple drank their milkshake, and they had to sell everything. Even then
though, it was really bizarre that anyone was still trying to make MIPs a
thing.

MIPS has been the walking dead for a couple of decades now. It's really time
to let go. Especially since there are actually interesting things happening in
the ISA space with RISC-V.

~~~
AnimalMuppet
Pardon my ignorance, but... is RISC-V all that much more alive than MIPS? My
impression is that MIPS has a past, RISC-V may have a future, but neither has
much of a present.

~~~
simcop2387
For desktop or server class stuff, RISC-V is still shaking out but there are
attempts to make it happen on-going right now. For everything else you've got
companies like Western Digital that have committed to shipping a billion[2]
RISC-V processors for their own devices, and many others. [1]

Just take a look at their membership page for people funding or helping
develop the processors, [https://riscv.org/members-at-a-
glance/](https://riscv.org/members-at-a-glance/)

[1]
[https://www.westerndigital.com/company/innovations/risc-v](https://www.westerndigital.com/company/innovations/risc-v)
[2] [https://www.extremetech.com/computing/281891-western-
digital...](https://www.extremetech.com/computing/281891-western-digital-
announces-plans-for-its-own-risc-v-processor)

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DeathArrow
Consolidation, together with buyouts and bankruptcy made a part of the
computing world much more boring.

In the '90s and early 2000s there were lots of CPUs, computer systems,
operating systems.

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csours
Please help me remove some of my ignorance:

ARM = RISC?

Intel = CISC?

? = MIPS?

What else is out there in large amounts?

~~~
ken
I assume that all modern CPUs are CISC-ish opcodes running in microcode on a
RISC-ish core, and it’s been a few decades since those were useful labels.

~~~
zozbot234
There's nothing much that's CISC-like about ARM, MIPS or RISC-V. Even many μC
architectures are closer to "RISC" than "CISC", though there's at least some
room for exceptions there.

~~~
yjftsjthsd-h
> There's nothing much that's CISC-like about ARM,

I struggle to think that ARM can really be called reduced-instruction after
neon or so.

~~~
glangdale
RISC has never been about reduced _number_ of instructions, but their
complexity. A SIMD extension built around load/store architecture is quite
compatible with the principles of RISC, despite the fact that such an
extension might have very numerous instructions.

~~~
yjftsjthsd-h
Well, I learned something today:) I'd always assumed that RISC meant a reduced
number of instructions, but that's clearly not the case. Wikipedia phrases it
as,

> The term "reduced" in that phrase was intended to describe the fact that the
> amount of work any single instruction accomplishes is reduced—at most a
> single data memory cycle—compared to the "complex instructions" of CISC CPUs
> that may require dozens of data memory cycles in order to execute a single
> instruction.[23] In particular, RISC processors typically have separate
> instructions for I/O and data processing.

So yeah, if SIMD instructions can execute in a single cycle (or maybe even a
small number), then it still counts.

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jojobas
All hail Rick Belluzzo.

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MrTortoise
i learnt how cpu work on spim

~~~
iso-8859-1
nah, you only learnt how to use them ;)

