
Visual Guide to 65xx CPU Timing - cmrdporcupine
http://laughtonelectronics.com/Arcana/Visualizing%2065xx%20Timing/Visualizing%2065xx%20CPU%20Timing.html
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yuhong
ARM was able to beat the 386 using similar principles, I think the ARM CPU
itself was designed with DRAM timing in mind:
[http://www.realworldtech.com/forum/?threadid=144991&curposti...](http://www.realworldtech.com/forum/?threadid=144991&curpostid=145604)

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cmrdporcupine
Yeah if you go back and compare an 8mhz ARMv2 in the Archimedes machines with
equivalent code in an Atari ST or Amiga, the ARM wins handily. Of course the
Amiga had the advantage with custom graphics hardware for certain workflows.
But the 68k is not as cycle efficient as the ARM.

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to3m
There's a bit about this in Sophie Wilson's Computer History Museum interview:
[http://www.computerhistory.org/collections/catalog/102746190](http://www.computerhistory.org/collections/catalog/102746190)

See p21, but it's interesting throughout.

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cmrdporcupine
Thanks this is a very inspiring interview.

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aidenn0
The same person made an extended CPU based of of a 65xx that could linearly
address 16MB of ram. Here's a great picture of the back of the CPU board; a
beautiful example of wire-wrap:

[http://laughtonelectronics.com/Arcana/KimKlone/KK%200800%20f...](http://laughtonelectronics.com/Arcana/KimKlone/KK%200800%20fr.jpg)

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duskwuff
NB: This is _not_ a 65C816! It's a 6502 with a very unusual memory mapper. :)

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Dr_Jefyll
Right -- not a 65c816. There's a summary and block diagram here:
[http://laughtonelectronics.com/Arcana/KimKlone/Kimklone_shor...](http://laughtonelectronics.com/Arcana/KimKlone/Kimklone_short_summary.html)

I'm the builder! :o)

\-- Jeff

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aidenn0
The KimKlone impresses me quite a bit; was it just a case of a thought like:
"oh, if I did this and this, I could extend the address space..." and then a
burning desire to see it work, or did something else motivate this?

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Dr_Jefyll
I was in my twenties, I was hugely turned on by the electronics I was
learning, and I was bursting with creativity! There's a little bit of Back
Story explained here, especially the "my KIM" section at the bottom of the
page.
[http://laughtonelectronics.com/Arcana/KimKlone/BrideOfSon%20...](http://laughtonelectronics.com/Arcana/KimKlone/BrideOfSon%20KK%20Lancaster.html)

Also I'm a Forth fan, and when when I realized the counter/timer of a 6522
could be tricked into serving as IP for a 9-cycle machine-code NEXT
instruction, the idea amused me immoderately (LMFAO) and I had to build the
darn thing! :oD Previous HN thread here:
[https://news.ycombinator.com/item?id=3070169](https://news.ycombinator.com/item?id=3070169)

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cmrdporcupine
Have you ever considered making a PCB of the thing and making it available to
others? Hell, I wonder if it'd even be possible to make an expansion model for
old 6502 machines using this technique.

It's very clever. Thank you.

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Dr_Jefyll
Thank _you_ for posting. A PCB would be fun but I'd be inclined to do a
shrink, moving away from all the jelly-bean logic. I'm pretty sure a KimKlone
clone (!) could be done with just a 128 macrocell CPLD, a '574 and the 2 uCode
EPROMs, plus the VIA, the CPU, and the stock memory complement (RAM/ROM).

Do you ever visit the forum at 6502.org? There's a smallish discussion about
KK there...
[http://forum.6502.org/viewtopic.php?f=9&t=1487](http://forum.6502.org/viewtopic.php?f=9&t=1487)

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cmrdporcupine
I do visit, but hadn't seen this thread. Sorting through it.

