
OpenCAPI Unveiled: AMD, IBM, Google, Xilinx, Micron and Mellanox Join Forces - ajdlinux
http://www.anandtech.com/show/10759/opencapi-unveiled-amd-ibm-google-more
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valarauca1
I really enjoy the way AMD and Nvidia fight.

Nvidia makes GSync. So the GPU can control and adjust display refresh rate on
the fly. Proprietary, closed source, requires private Nvidia License. AMD
makes FreeSync. FreeSync open sourced, added to the HDMI, and Display Port
standards.

Now we see Nvidia makes NvLink. Proprietary, very fast, requires private
Nvidia license. AMD partners with IBM, Google, etc., etc. to make OpenCAPI an
open standard that can revise/replace PCIe3.0

Why does this feel like Microsoft vs Linux but with Hardware Standards.

~~~
arcanus
> I really enjoy the way AMD and Nvidia fight

That's why I was so sad AMD was having trouble later year and hope they pull
through. Competition is valuable and benefits the consumer!

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bch
It felt so buried in the article, it's worth pointing out: OpenCAPI == "Open
Coherent Accelerator Processor Interface"

~~~
appleflaxen
Thanks for posting this. What does "coherent" mean in this context, and why is
it special?

~~~
cmrx64
Basically,
[https://en.wikipedia.org/wiki/Cache_coherence](https://en.wikipedia.org/wiki/Cache_coherence).
You want to ensure all the devices on the bus have the same view of memory
contents.

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zmanian
Anand Tech seems quite excited about OpenPower and it does tend make me more
interested in the Talos platform.
[https://www.raptorengineering.com/TALOS/prerelease.php](https://www.raptorengineering.com/TALOS/prerelease.php)

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PhantomGremlin
Was "anyone" as "annoyed" as I was about the "scare quotes" littered
"throughout" the article? It was "hard" to read the "story".

I've been guilty of using too many quotes in the recent past. Someone on HN
called me on it, and I've since toned it down. Now it's something that sticks
out at me.

~~~
joblessjunkie
It makes it seem like the "journalist" doesn't believe his own "reporting".

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praseodym
Related post on the Google Cloud Platform Blog:
[https://cloudplatform.googleblog.com/2016/10/introducing-
Zai...](https://cloudplatform.googleblog.com/2016/10/introducing-Zaius-Google-
and-Rackspaces-open-server-running-IBM-POWER9.html)

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eeks
Hopefully this effort will get us rid of PCIe for good, unlike the version of
CAPI available on POWER8.

~~~
sargun
What's wrong with PCIe? The devices are ubiquitous. It's point-to-point,
allowing for device to device connectivity. We have external PCIe enclosures
and cables. We have a healthy set of PCIe switches.

This is similar. It's also point-to-point, and it has an external story.
Skimming the spec, they've even thought about higher latency (200ns) links,
and optical. Even with these advantages, I'm unsure how it'll work due to the
lack of IP available as compared to PCIe.

Interesting, though. Will be fun to see it play out. It bums me out a little
bit though that POWER isn't easily available yet.

~~~
eeks
PCIe is still rather slow. A single-packet transaction on PCIe costs 120ns.

The lack of IP is the reason why P8/CAPI stuck to PCIe. In the original
design, CAPI was to simply reuse the PCI link layer, not the transaction
layer.

With a cache-coherent system based on PCIe, especially when the coherency
layer is set at L3 like on POWER8, you are looking at ~500ns latency for a
single cache line. This kind of latency is just too much for many
applications.

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madenine
> "NVIDIA is a member of the OpenCAPI consortium, at the "contributor level",
> which is the same level Xilinx has. The same is true for HPE (HP
> Enterprise)"

Awesome.

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visionscaper
Hmmm, interesting. I wonder what this means for the new Intel Xeon Phi Knights
Landing? I liked the approach of many cores on one bootable chip, all having a
reasonable amount of local memory, and high bandwidth interconnects: no need
to offload data to a peripheral (GPU) device. However with this standard the
currently limited bandwidth between peripherals and the main cpu will improve
a lot.

To me it is obvious why Intel is not joining this party.

~~~
convolvatron
well, i think its a bit more about market segments and interoperability than
anything else. currently overall systems from ibm, and, and intel are
fundamentally incompatible. the PCI-E bus that knights landing hangs off of is
a qualitatively different thing than the kinds of memory-coherent inter-cpu
busses that are being addressed with the CAPI proposal. Intel has their own
proprietary QPI. AMD has a quasi-open hyper transport (still?).

If this is done properly it means you could make generic motherboards, and
generic memory controllers, and all sorts of different accelerators and mix
and match them from various vendors. So its no surprise that the smaller
players in the market and trying to gang together and the larger player is
trying to keep lock-in.

Knights Landing as it stands would already integrate in systems better if it
were using an inter-cpu bus than a peripheral bus as well as GPUs, FPGAs, and
certainly RDMA/memory window systems like Mellanox.

Inherent distrust of standards aside, this could be a great win for people
putting together bespoke systems in interesting configurations (i.e. Google),
I don't think there is any downside in theory for Intel except more
competition.

~~~
gpderetta
There are KNL variants that sit on a cpu socket and talk to the rest of the
system via QPI.

~~~
convolvatron
I haven't caught up with the latest phi releases, but I'm really interested to
do so. I haven't been able to find any discussion about a coherent QPI on KNL,
but have found reference to OmniPath, which looks like a non-coherent large
scale memory network. Is that what you were thinking of, or maybe could you
post a reference?

~~~
gpderetta
You are right, I was misremembering. The socketed KNL does not have QPI at
all, so no multisocket boards are possible. Still the socketed KNL doesn't
hang-off the PCI bus as it is its own host processor and has a dedicated link
with memory.

Omnipath is used to drive both the Ethernet and PCIe.

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samfisher83
No Intel ? Without them joining on board this might not be as useful.

~~~
nickpsecurity
We have every big name in this, including an x86 vendor. We don't need Intel.
That's not a statement I can make often. :)

~~~
samfisher83
Intel has 99% of the server market.

~~~
grive
Do they need the market leader to take on the market?

In the end, that's also what is at stake, and the reason Intel might not be
that interested. They will maybe see the light and see that they would have to
steer the collaboration toward a more beneficial direction (for them), but at
first, they will probably wait for it to gain momentum before deciding that
they have to invest money to push the effort in the right direction (for
them).

They have to be a threat for the established company to make a move. What
nickpsecurity is saying by telling that they don't need Intel is that they are
not yet a sufficient threat and that they are capable of becoming one.

~~~
nickpsecurity
Which they will be if they have a competitive technology that has a migration
path for both x86 ISA and about everything else dominating in acceleration
space. Intel might respond by supporting it or deploying their own thing.
They're sure to loose market share, though, if the coalition's standardization
commoditizes accelerators more than Intel's side does. They could loose some
profit margin in the niche along with the market share.

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crudbug
Exciting news on the hardware bus side.

Now waiting for AMD Power9 processors.

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honkhonkpants
Given AMD's involvement, what is the difference between this and coherent
hypertransport?

~~~
wmf
The difference is that NVIDIA, Mellanox, and Xilinx never adopted coherent
Hypertransport.

~~~
honkhonkpants
There was at one point cHT IP available for Xilinx. But that is what I am
kinda getting at. Did cHT fail for reasons of pure timing? Too far ahead of
the market?

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KevinEldon
Hewlett-Packard Enterprise is also a member of this consortium (the source
article was updated to reflect this)

