
A Computing Pioneer Has a New Idea - jaydub
http://www.nytimes.com/2008/11/17/technology/business-computing/17machine.html?_r=1&ref=technology&oref=slogin
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preview
I don't think having a standard processor coupled with programmable gates is a
new idea. The key is in making it simple to use. A basic adder or multiplier
is a well known piece of logic and would be included in a standard FPGA
component library. Will arbitrary custom instructions require an engineer to
develop the FPGA macro? Having a software and a hardware engineer working
together to optimize execution time does not seem new to me. Is the
simplification in the interface between the processor and FPGA gates?

They must have done some research into min and max gates required to implement
logic for custom instructions across the targeted problem domains. An
important question is the time required to reconfigure the FPGA gates.
Multiple FPGA tiles will be needed since it'd take longer to reconfigure the
FPGA gates then to jump to a new branch of code that had its own custom
instruction. This may require a customization to the compiler as time to
reconfigure FPGA gates may need to be taken into account in the order of
execution (not a new problem; just another variable to take into account).

It could be very interesting, but more technical details are needed.

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blackguardx
It doesn't seem like FPGA reprogramming time will be an issue. Presumably,
they will work on one problem at a time. They will have a custom instruction
to calculate Pi and let the machine run for a few months and then switch to
crunching data from seismic oil well probes.

Modern FPGAs can be reprogrammed in a few milliseconds, which seems like a
long time in the computer world. In essence megabytes of SRAM need to be
written to in order to configure an FPGA.

Also, FPGAs have the ability to do partial reconfiguration, but the support is
spotty. In the ideal world, parts of an FPGA would be reconfigured while the
other parts were still in operation.

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preview
The issue I was thinking of is if you needed multiple "custom instructions"
within a loop. Another related issue, if multiple tiles are considered, is the
interconnect between the processor core and the tiles. Interconnect is
expensive, so there's a trade off to be made. Profiling data showing a curve
of unique accelerator functions for the targeted problem domains and their
temporal relationship (e.g. there may be ten accelerator functions but they
are executed several milliseconds apart or functions A and B tend to appear in
an inner loop together) would help make the trade off.

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iigs
Cool. It sounds like maybe they're adding a FPGA in a manner similar to a FPU
-- an annex to the CPU. It would be huge to be able to design, load, and
execute custom instructions for your CPU. For example, it would be pretty
slick to be able to add specific operations that would aid in garbage
collecting, or context switching, or deeply pipeline simple but long serial
processes (a lot of network server or media processes come to mind).

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blackguardx
Many FPGAs come equipped with multiple processor cores on chip. Some models of
the Xilinx Virtex 5 (yes, they spelled it wrong) include 2 PowerPC cores. Some
FPGAs might have as much as 4.

I wonder if anyone has taken these existing FPGAs and tried to do something
similar to what you are suggesting. I know these FPGAs are typically used to
implement DSP logic, but it would be interesting to see if anyone has tightly
coupled the FPGA fabric with the on-board processors for more general
processing applications.

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tlrobinson
Slightly off topic, but "The Soul of a New Machine" was a pretty good book.

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clay
Does anyone have more technical information about this? I tried googling but
just found marketing babble. Also, turns out the headquarters for this place
is a couple blocks away from me, haha.

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kqr2
It sounds like a cross between a traditional CPU + FPGA. The twist is that the
FPGA portions can easily be reconfigured by simple instructions instead of
having to do something complicated like running a CAD tool from Synopsys.

 _The right way to use them_ [FPGAs] _, he decided, was to couple them so
tightly to the microprocessor chip that it would appear they were simply a
small set of additional instructions to give a programmer an easy way to
turbocharge a program. Everything had to look exactly like the standard
programming environment. In contrast, many supercomputers today require
programmers to be “heroic.”_

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13ren
Not new <http://zikzak.net/~zik/thesis/thesis.html> but not bad.

