
AMD EPYC Rome 2P Will Have 128-160 PCIe Gen4 Lanes and a Bonus - vanburen
https://www.servethehome.com/why-amd-epyc-rome-2p-will-have-128-160-pcie-gen4-lanes-and-a-bonus/
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consp
Can someone enlighten me with some information about application requiring the
full 16x PCIe gen4 bandwidth per slot (or 32x gen3 for that matter)? I can
imagine some HPC GPU solutions but other than that what requires the
thoughput?

There is obviously a market for this as both giants are building platforms.

~~~
kilo_bravo_3
Off the top of my head this would be great for massive enterprise VDI
installations and game streaming services (which is just VDI by another name),
ML, AI applications, and NVMe storage.

Personally, this will be good for me because everything I do is bandwidth-
starved.

I'm not a radar scientist but I am a systems engineer supporting radar
scientists working on air- and space-based Synthetic Aperture Radar (SAR)
systems. We use GPUs, FPGAs, and other accelerators to generate images from
SAR data.

Here's an "old and busted" image made from SAR data:
[https://hackadaycom.files.wordpress.com/2014/02/image-
from-s...](https://hackadaycom.files.wordpress.com/2014/02/image-from-sandias-
system.png)

In 2002, it took more than 24 hours to generate a single low-resolution
picture from low-bandwidth SAR data on a $1.5 million Sunfire 15K cluster with
70-ish SPARC CPUs. Today, on a single 3U server with two Xeons and four Tesla
V100s it takes about 15 seconds-- and that's an extremely high resolution
image from very high data rate SAR data.

But our goal is real-time VIDEO from SAR data, so everything needs to be
faster. Network speeds need to be faster, CPUs need to be faster, GPUs need to
be faster and we need more of them, storage needs to be faster, everything
needs to be faster.

I could see a 3/4U box with 16+ 16x PCIe slots each stuffed with a 1-slot GPU
with an NVMe (4x PCIe lanes each!) storage array and a couple of 100GBe dual-
port NICs blasting through SAR data like a hungry hungry hippo.

As far as PCIe lanes go, if I have a 24-drive NVMe array that's 96 PCIe lanes
all by itself.

~~~
justinclift
Hmmm, how many radar pulses need to hit a target to generate video? Sounds
potentially irradating... ;)

eg: _WARNING_ Don't attempt to image living creatures _WARNING_

~~~
wyldfire
RADAR typically uses microwaves, non-ionizing. Over this area it's bound to be
a terribly, terribly small amount of exposure.

~~~
justinclift
Ahhh, no worries.

Just remembering a friend recently telling me about someone who was killed at
a work place. Apparently that person walked in front of the main radar array
(defense related I think) while it was in operation and just dropped dead
instantly. :(

~~~
Yetanfou
At the 1933 World’s Fair in Chicago, Westinghouse demonstrated a 10-kilowatt
shortwave radio transmitter that cooked steaks and potatoes between two metal
plates [1]. In 1946 a Raytheon engineer named Robert Spencer _"...was visiting
a lab where magnetrons, the power tubes of radar sets, were being tested.
Suddenly, he felt a peanut bar start to cook in his pocket. Other scientists
had noticed this phenomenon, but Spencer itched to know more about it. He sent
a boy out for a package of popcorn. When he held it near a magnetron, popcorn
exploded all over the lab. Next morning he brought in a kettle, cut a hole in
the side and put an uncooked egg (in its shell) into the pot. Then he moved a
magnetron against the hole and turned on the juice. A sceptical engineer
peeked over the top of the pot just in time to catch a face-full of cooked
egg. The reason? The yolk cooked faster than the outside, causing the egg to
burst..."_ [2]. This discovery led to a patent application for "the use of
microwaves to heat food", a concept which was eventually realised in the
"Raytheon RadaRange" series of microwave ovens [3].

[1]
[https://en.wikipedia.org/wiki/Microwave_oven#/media/File:Coo...](https://en.wikipedia.org/wiki/Microwave_oven#/media/File:Cooking_with_radio_waves_-
_Chicago_Worlds_Fair_1933.jpg)

[2] [https://spectrum.ieee.org/tech-history/space-age/a-brief-
his...](https://spectrum.ieee.org/tech-history/space-age/a-brief-history-of-
the-microwave-oven)

[3]
[https://en.wikipedia.org/wiki/Microwave_oven#/media/File:NS_...](https://en.wikipedia.org/wiki/Microwave_oven#/media/File:NS_Savannah_microwave_oven_MD8.jpg)

------
craftyguy
>why the AMD EPYC “Rome” generation will _likely_ see 160x PCIe Gen4 lanes
plus likely additional lane(s) for a necessary function.

Emphasis mine. This seems to be pure speculation, not 'news'.

~~~
Patrick-STH
Likely is there because it requires that AMD's partners release servers in
this configuration, and those servers are unreleased. In theory, something
during validation could prevent it or partners could decide not to release
this configuration (which are unlikely but still possible.)

------
lousken
Meanwhile i9 9900k still has only 16 3.0 lanes ...

~~~
eropple
AMD's been adding more PCIe lanes across their hardware lineup than Intel has
to be sure, but EPYC is server-class stuff with 64 cores to a chip. The Ryzen
2 2700X only has 20 lanes for 8 cores.

~~~
_jal
I don't watch this as closely as a lot of people, but my impression is that
Intel has been rationing lanes as one way to segment their market, and AMD
noticed they can easily mess with that strategy.

I spent significantly more for the CPU on a personal build a few years ago
because I needed 40 lanes instead of 24. I'm all for AMD messing with it.

~~~
blattimwind
Intel segments the market across every single facet they can find and that
won't outright keep people from buying their stuff. Hyperthreading, ECC memory
(I ranted about how _insane_ this is before, on numerous occasions), I/O
options, GPU options, cache size, TDP, network and of course socket
compatibility (where Intel figured out that not only can they sell you a new
CPU with 0-5 % more performance every two years, but that they can also make
you buy a new board to go with that just by adding or removing a couple ground
pins).

And Intel got away with it because they had no competition. Monopolies are
always very, very bad for consumers.

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Patrick-STH
Just added a quick note. Everyone in the industry that contacted me today
about this seems to be calling it WAFL or something that sounds like "Waffle"
for the extra bonus PCIe lanes.

