
5/3nm Wars Begin - nanosheet
https://semiengineering.com/5-3nm-wars-begin/
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bogomipz
The article states:

>"Originally, the node name was tied to the transistor gate length
dimensions."

then further down:

>"CPP, a key transistor metric, measures the distance between a source and
drain contact."

I have mistakenly thought that node designations were based on distance
between source and drain. Could someone say why gate length dimensions are the
more significant measurement? The distance between source and drain somehow
feels more intuitive to me. But maybe because this is easier to visualize?

~~~
ajross
"Gate length" referred to the width of the sandwiched semiconductor band with
different doping, (i.e. the "N" part of a PNP CMOS transistor). Traditionally
(which is to say, so long ago that it doesn't really matter) these were the
finest features present in the mask set and were a good metric for fab
sophistication.

That CPP metric is measuring how close together the contact vias for the two
halves of the transistor can be. It's a much bigger number, but still probably
just as good as a proxy for transistor density.

~~~
blattimwind
> "Gate length" referred to the width of the sandwiched semiconductor band
> with different doping, (i.e. the "N" part of a PNP CMOS transistor).

Something doesn't feel quite right.

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RandomTisk
Is this just further marketing malpractice or will there actually be 5 or 3nm
features?

~~~
SethTro
> Today, the node names are little more than marketing terms. 'The node
> designation is becoming more misleading and meaningless," said Samuel Wang,
> an analyst at Gartner. "For example, at 5nm or 3nm, there is no single
> geometry that is actually 5nm or 3nm."

~~~
hartator
So what is 5nm or 3nm?

~~~
wmf
The process marketed as 5nm has roughly twice the density as the process
marketed as 7nm and so on up and down the line; that's how they justify it.

~~~
AlexCoventry
How can they double the density without decreasing the feature size?

~~~
wmf
The feature side usually does decrease every generation; it's just that the
feature size for, say, a "7nm" process is not exactly 7nm.

~~~
ggm
The power of recursive reasoning. Induction tells us that Intel's 10nm process
probably wasn't 10nm features...

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nanosheet
Is Moore's Law still alive?

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seshagiric
To quote Intel CEO Robert Swan (on CNBC); the Moore's law is going to come
back live in the 5/3nm Fab capabilities. Intel is at 11nm, aiming for 7nm.
Whereas Texas Instruments is going for 5nm. Per Robert, they had lot of
learnings from 11nm to 7nm but expect the move to 5/3nm much faster.

~~~
marvy
But realistically it can't go on much longer, right? The diameter of a silicon
atom is like 0.21 nanometers, so we're almost within an order of magnitude
from rock bottom, right? I don't actually know anything about this stuff so I
could be hopelessly confused, but that's my impression.

~~~
PaulHoule
Past that, it is various forms of chiplets, 3-d stacking, high bandwidth
memory to intensify densification at some cost.

In the wings there are a few semiconductor materials, from Si-Ge to In-P and
Ga-A and Ga-N that are used in optical transceivers, cell phone base stations,
power electronics, and military electronics. Silicon is a good, not great
superconductor, and it dominates because we are good at making things out of
Silicon.

An In-P microprocessor as complex as a 6502 should be able to clock upwards of
80 GHz and could run with a fully populated address space of static RAM on the
chip and be able to react to fast events in real time like nothing else.

Such a chip would replace 16 5GHz cores for more mainstream computation, so if
cost gaps narrowed, the In-P part might compete with a Si part in a complex
chiplet architecture. (e.g. the In-P chip can be built at 1/16 the density of
the Si chip and not have all this multiple-patterning and lasers trouble that
Si is getting into)

~~~
hpcjoe
Hmm ... I wrote my Ph.D. thesis on low temperature grown III-V material (GaAs
to be precise) and studied InGaAs, and other variations.

GaAs would make for awesome switching systems, as it is a direct bandgap
semiconductor, as opposed to Silicon, which requires phonon mediation. While
this is a tremendous technological advantage, you have that minor problem of
fabrication.

For GaAs, you need ~5 atmospheres of As gas at 550C. Not something anyone
wants in their backyard, for good reason.

For InP, you need to worry about your supply of rare earth (In) elements, and
all the surrounding tech needed to grow ingots of an appropriate orientation
material for InP. You have to worry about the role of defects (which is what I
simulated), how to dope, how to build structures.

Its not simply that it is technologically better, its that there is a whole
massive ecosystem around Silicon, that for better or worse, pretty much
guarantees that we are going to be running silicon based units for a long ...
long time.

The joke, and there was one when I was in grad school, about GaAs and other
non-Si materials was, they are the materials of the future. And always will
be.

~~~
davidivadavid
How do industries typically break out of that kind of path dependence?

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AnimalMuppet
First, it's not really a path dependency. Silicon is easier to work with than
gallium arsenide, not just because we have more practice. We have more
practice because it's easier.

How do we break out? By gallium arsenide offering enough more than silicon
does to be worth the effort. So far, that hasn't happened. It may never,
except for small niches.

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vkaku
I don't think the 7nm one is complete yet.

~~~
skunkworker
I'm not entirely convinced that intel with their 10nm (equivalent to TSMC 7nm)
will be able to catch up in time to the transition to Intel 7nm,TSMC 5nm
unless that process is shortlived. The first 7nm processor, the iPhone XS's
A12 was shipped back in fall of 2018 but intel has yet to ship a widely
released 10nm so far.

The next process could flip for Intel or TSMC as each process has it's own
problems, but for now I would put TSMC much further ahead of Intel in the
Intel 10nm/TSMC 7nm battle.

~~~
georgeburdell
>but intel has yet to ship a widely released 10nm so far.

This is not correct. 10nm Ice Lake laptops have been in stores for a quarter
or more now. For example: [https://www.costco.com/hp-14%22-laptop---10th-gen-
intel-core...](https://www.costco.com/hp-14%22-laptop---10th-gen-intel-
core-i7-1065g7---1080p.product.100511530.html)

~~~
dehrmann
But where's Comet Lake? The fact that there aren't any 10nm non-mobile Intel
Core CPUs makes me think Intel's having production issues.

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xiphias2
I was looking for the type of device that the chips will be used for, but
couldn't find any mention.

Sadly laptops are always behind in the manufacturing queue when it comes to
knew technology.

I'm excited that Zen 2 is coming out on 7nm, but at the same time my mobile
phone is already good enough in energy efficiency, and I don't expect real
practical speed increase for the 5nm version.

~~~
rwmj
Smaller transistors use less power, it's not always about increasing speed.
Your smartphone, if it's anything like mine, would be better if it had a
longer running time between charges.

Having said that, the very first users will be high end servers. It's no
accident that IBM were the first to demonstrate 5nm wafers a few years ago[1],
because they'll use them in their top of the line POWER chips. Those chips
have incredible single thread performance, but also incredible prices (and
apparently very low yields). If you're the sort of person who wonders who
would pay money for that, then you're not the target customer :-) (Disclosure:
I now work indirectly for IBM)

[1] [https://www.ibm.com/blogs/think/2017/06/5-nanometer-
transist...](https://www.ibm.com/blogs/think/2017/06/5-nanometer-transistors/)

~~~
Fronzie
> Smaller transistors use less power.

Don't the smaller transistors also have higher leakage? I thought that below
10nm scaling down further would not give power benefits.

~~~
unlinked_dll
It's called Dennard Scaling [0] and it ran out about 15 years ago

[0]
[https://en.wikipedia.org/wiki/Dennard_scaling](https://en.wikipedia.org/wiki/Dennard_scaling)

~~~
Dylan16807
Having constant power density with continuous performance improvements broke
down.

But we're not yet at the point where power density increases as fast as
transistor density.

