
TSMC: First 7nm EUV Chips Taped Out, 5nm Risk Production in Q2 2019 - dmmalam
https://www.anandtech.com/show/13445/tsmc-first-7nm-euv-chips-taped-out-5nm-risk-in-q2
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ChuckMcM
From the article:

 _One of the factors that prevents smaller companies from designing FinFET
chips is development cost. Some estimates put the average cost to develop an
SoC at around $150 million in labor and IP licenses. With N5 generation, these
expenditures will rise to $200 – $250 million, according to EETAsia, which
will limit the number of parties interested in using the tech._

Ouch. A $250M NRE cost for an SOC, really puts pressure on guaranteeing the
volume of the part in order to recover any sort of margin on a part like that.

Pretty cool to see EUV seem to finally emerge out of the 'someday' status into
the 'some now, more next year' status.

~~~
AnimalMuppet
Of course, at those prices there will be fewer SOCs. That means, on average,
that each SOC will get more design wins, and therefore have higher volume...

~~~
russdill
It also means that each SoC will have more pressure to cater to more customers
which seems more dark silicon which will reduce the advantage of smaller
process sizes

~~~
ethbro
Wouldn't dark silicon help with both yield and heat though?

~~~
russdill
It's very difficult to save power with unused silicon on newer process nodes
due to high leakage. You actually have to turn it off. Putting each IP into
it's own power domain just isn't feasible. Not good for power sensitive
applications.

~~~
kingosticks
We were being asked to look at a design where we literally didn't have
anything in the middle of the chip in order to reduce local power
(specifically due to current limitations of the bumps)!

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dmoy
Does someone have an up-to-date table comparing the different fabs'
interpretations of "Xnm" process size? I recall them all having very different
values (to the point where one might actually be a whole process size behind,
but not admit it for marketing purposes).

~~~
tfha
Basically everybody is lying by 1 full step except Intel, who is only lying by
1 half step.

[https://en.m.wikipedia.org/wiki/7_nanometer](https://en.m.wikipedia.org/wiki/7_nanometer)

[https://en.m.wikipedia.org/wiki/10_nanometer](https://en.m.wikipedia.org/wiki/10_nanometer)

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monocasa
> By contrast, TSMC’s second-generation 7 nm manufacturing technology
> (CLN7FF+, N7+) will use extreme ultraviolet lithography for four non-
> critical layers

As in, "like everyone else, we haven't really figured out EUV shot noise yet".

Nice marketing though, lolz.

~~~
deepnotderp
Well the solution is simple: use longer exposures, of course, that has the
unpleasant side effect of annihilating your throughput on extremely expensive
machines...

~~~
BostonEnginerd
EUV is truly amazing in that it works at all. The shot noise is simple to fix
in theory - just get more photons. In practice, it's going to be really
challenging to get more light out of the molten tin droplets.

~~~
Itsdijital
IIRC the efficiency is hilariously bad. It's something like 100W of EUV light
takes 1,000,000W (1MW) to produce.

~~~
wbl
Free electron lasers didn't pan out?

~~~
baybal2
Not yet, 1 megawatt death ray is more economical than a freaking cyclotron+fel
combo for now.

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cmyr
What is "risk production"? I can't help but reading it as something like, "we
even risk producing some chips at some point!", which I presume isn't quite
it.

~~~
ip26
That's sort of right, basically it's the first real production runs, when you
think everything is ready & will work, but you haven't actually made a real
product yet.

 _At the start of risk production, by definition there have been no customer
designs put through the fab. Actually this is not quite true, Sun explained.
Before the start of risk production the company has already run a number of
shuttles with test chips from customers, so foundry and clients are already
starting to wring out the more critical structures in the first customer
designs. But these test shuttles are not full chips either._

\-- [https://www.edn.com/electronics-blogs/practical-chip-
design/...](https://www.edn.com/electronics-blogs/practical-chip-
design/4309335/TSMC-risk-production-what-does-it-mean-for-28nm-)

So, it's a point in the process where the foundry is taking a chance, and the
customer is also taking a chance.

I've also heard it applied to a customer design, e.g. the customer starts to
volume ramp production before they finish fully testing the design.

~~~
Taniwha
As a customer I've always heard it used as the latter when we tape out (or
spin from a bug) and think we're ready to go so we start some wafers down the
line behind the first ones to reduce time to market

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yoran
I remember when I was doing my master's thesis for ASML in Eindhoven in
Holland (their headquarters). They had a separate building on the campus just
for the development of EUV, which was the next new thing. This was in 2011 and
they had already been working on it for a couple of years. Happy to see that
chip manufacturers are now using this technology for their production. It
looks like the bet paid off!

~~~
smueller1234
Not quite yet. When I worked for Zeiss in 2005, it was also the next big
thing. Well. Maybe the next next big thing but still.

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partingshots
Just to help me clarify, the tariffs that are being levied between China and
America, do or do not also apply to Taiwan? I’ve never fully understood how
the separation of Taiwan and China is made since it seems to be such a touchy
subject.

~~~
DoofusOfDeath
Most of the world considers Taiwan (a.k.a. "Republic of China") to be a
distinct country.

The mainland Chinese government disagrees.

I don't know about these particular tariffs, but I believe the U.S. would not
consider tariffs aimed at (mainland) China to apply to Taiwan.

~~~
Symmetry
The RoC consider themselves the rightful "China" too. Some Taiwanese
politicians have advocated declaring themselves an independent country but
that's never been the official government position.

~~~
e3b0c
> The RoC consider themselves the rightful "China" too.

That's a minority/extremity opinion which isn't remotely prevalent even among
those who feel intimate with China. It used to be the 'political-correct'
belief held by the former authoritarian ruling party. But it's not considered
a rational worldview anymore after its democratic modernization.

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ajb
EUV has been the on the roadmap for what, 15, 20, years? It must be amazing
for your work to finally pay off after all that time.

~~~
astrodust
I figured they'd have done X-ray etching long before now, but somehow they
squeezed a lot of life out of UV.

~~~
simcop2387
My understanding is that with X-ray etching/lithography it's significantly
more difficult to produce the coherent beam and also to do the focusing of it
through a masking plate so you can etch a whole wafer at one time. That's the
main reason that they've been working on EUV because they can produce a
coherent pulse and focus it more easily. For X-rays you have to turn it into a
diffraction grating to make the mask and that ends up more difficult to
produce (probably not impossible but much more difficult).

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valarauca1
I wonder when the rapid erosion of Intel's technical lead in fabrication
technology be represented in decreasing evaluation of its market cap.

It was rumored TSMC's 7nm wouldn't be the same as Intel's 10nm. But if they
reach ~5nm then they'll likely be knocking on Intel's 10nm door. Combined with
the double whammy of 7nm Eypc servers from AMD it seems like Intel's technical
offerings are rapidly getting commoditized by the rest of the market.

~~~
ChuckMcM
At some level this situation was inevitable, as more and more companies
offload their fab capability to TSMC, that gives more and more money for TSMC
to invest in boosting their capability, and of course while their margins are
a lot less than Intel's with enough money that advantage goes away as well.

Intel's instruction set architecture dominance will keep it going for a long
time but ultimately it would probably make sense for Intel to spin off its
fabs into the US equivalent of TSMC and capture more margin revenue from their
designs versus their process.

~~~
deepnotderp
TSMC's gross margin is something like 50% iirc so it's not even that bad

~~~
ChuckMcM
50.9% on 32B$ for TSMC[1] vs 62.3% on 62.7B$ for Intel[2] That is closer than
I expected it to be. In terms of actual cash (if you are wondering) Intel
ended last year with $22B more of it than TSMC did.

[1]
[http://www.tsmc.com/download/ir/annualReports/2017/english/p...](http://www.tsmc.com/download/ir/annualReports/2017/english/pdf/e_all.pdf)

[2]
[https://s21.q4cdn.com/600692695/files/doc_financials/2017/an...](https://s21.q4cdn.com/600692695/files/doc_financials/2017/annual/Intel_Annual_Report_Final_corrected.pdf)

~~~
ksec
Would it not be better to compare Net Income?

TSMC ~ $11B Intel ~ $9.5B

TSMC has become more profitable than Intel since 2016.

~~~
ChuckMcM
[Disclaimer I own a small amount of Intel in my IRA account]

If you have ever been in an investment club (basically friends who get
together and exchange ideas on what stocks to invest in) you have probably had
the 'revenue/income' discussion.

Amazon is the poster child for 'net income doesn't matter' as it has
reinvested most of its margin in itself over the years to grow.

So it can go either way.

TSMC does pay a dividend which Intel doesn't so from a financial
trading/investing point of view you could argue that TSMC is a better stock to
hold long as it will generate income.

From the 'future of the business' point of view re-investing more would seem
to be the wiser strategy. Time will tell.

~~~
ksec
The problem is I haven't seen any major results from Intel's investment for
the past 4+ years. And I have no idea where are all of their R&D into. TSMC
has been building more Fabs every single year, higher expenditure, while Intel
has had little to no Fab capacity expansion ( Apart from the recent 14nm
shortage ). In terms of CAPEX TSMC is only second to Samsung, but Samsung is
the world largest DRAM and NAND maker.

In terms of roadmap TSMC has been extremely open about their progress all they
way down to 3nm and has been executing to perfection. They take pride to be
Apple's pure play Fab.

I do believe in re-investing for the future, the problem is I have trouble
seeing that future from Intel. And their management has been lying for far too
long doesn't bring me confidence.

Time will Tell.

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fizixer
What does even 7nm or 5nm mean at this point? And who verifies the claims made
by the manufacturer? You need almost as sophisticated equipment for
verification as needed for fabrication. The the fabrciation companies are the
only ones that have that capability.

node ratings are a marketing joke at this point. Actually most likely it
became a joke more than 10 years ago.

~~~
welterde
> You need almost as sophisticated equipment for verification as needed for
> fabrication. The the fabrciation companies are the only ones that have that
> capability.

That's not true. Imaging ICs (or other structures) down to sub-nm resolution
is much much easier than making them. Most physics labs will have no problem
doing that..

The various imaging techniques (AFM, STM, etc.) used can routinely achieve
sufficient resolution to verify these claims with fairly moderate amounts of
tweaking and cost. STM is often used to image things down to atomic
resolution.

~~~
johntb86
> That's not true. Imaging ICs (or other structures) down to sub-nm resolution
> is much much easier than making them. Most physics labs will have no problem
> doing that..

For example, see Chipworks's analysis of Intel's 14nm process:

[https://www.chipworks.com/about-
chipworks/overview/blog/inte...](https://www.chipworks.com/about-
chipworks/overview/blog/intel%E2%80%99s-14-nm-parts-are-finally-here)

~~~
fizixer
The link you shared only supports my point: either the claims are false, or
they're not verifiable independently.

"As yet we don’t have any detailed TEM imaging to look at the transistors or
fins in close-up"

And that's 14nm from years ago, not the 7nm or 5nm being claimed these days.

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syntaxing
Is the die mask one of the biggest challenges for the 5/7 nm chips? I would of
assumed it would of been the uniformity of the wafer process.

~~~
monocasa
For EUV, yeah. That shit's tricky.

The wiki page on EUV is uncharacteristically excellent.

[https://en.wikipedia.org/wiki/Extreme_ultraviolet_lithograph...](https://en.wikipedia.org/wiki/Extreme_ultraviolet_lithography)

~~~
pas
> Since the optics already absorbs 96% of the EUV light, [...]

WTF!? Why? Is there any hope for better optics?

~~~
baybal2
Mirrors on EUV machines are already the type that exceeds reflectivity of all
mirrors ever produced.

That's why you have to build fabs around a multi-megawatt laser source.

The only known hope going forward are photonic crystal mirrors

~~~
fermienrico
But, why does 96% of the energy gets absorbed?

~~~
dgacmu
Each mirror absorbs about 30% of the EUV incident upon it (and the mask counts
as a mirror). With about 9 total mirrors on the path, you're down to 0.7^9 ~=
4% of the initial light left.

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WhitneyLand
Why is Intel seemingly so behind?

Even if you account for feature size marketing and nomenclature differences,
it doesn’t look good.

And the $250MM mentioned, pardon my language but they crap that much for
breakfast. I don’t mean to overstate it, look at the financials, the net
profit available to them _after_ existing R&D investments is staggering.

~~~
franknine
Maybe it's because hiring Taiwanese R&D people cost way less than hiring in
the U.S. I live in Taiwan and I have friends with master degree in EE who work
for TSMC for 5-10 years and none of them getting close to 100k a year.

~~~
WhitneyLand
Normally thst could be a factor, but look at how insignificant it is.

Intel spent 13 billion on R&D last year, and had $26 billion left over ebitda
profit _still_. You can argue a different profit number than ebitda should be
used, but pick any one you want, they’re all massive.

Say your friends make 50k salary (just for arguments sake and let’s not
calculate a fully burdened salary for simplicity).

If 1,000 Intel engineers were averaging 150k in the US, the difference would
only be 100MM.

That is so insignificant to them, they couule use it as fire wood just for
fun. So it can’t be higher labor costs.

My best guess is they made a few “big bets” that went wrong and cost them
dearly. Or there’s always the old standby thst the wrong leadership is in
place at the EVP/VP levels and it’s had a negative ripple effect.

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tooltalk
Samsung is going mass production with their EUV in Q1 or 2 in 2019. I'm also
speculating that Qualcomm's next SD would be made by Samsung LSI. How does it
compare to TSMC?

