
HiFive1 – Arduino RISC-V Dev Board - prestonbriggs
https://www.sparkfun.com/products/15026
======
schaefer
If I'm not mistaken, this is the same dev board that's been for sale from the
manufacturer (sifive) for months and months [1]. Is the only news here that
the board is now in stock at spark fun?

[1]
[https://www.sifive.com/boards/hifive1](https://www.sifive.com/boards/hifive1)

~~~
ansible
> _If I 'm not mistaken, this is the same dev board that's been for sale from
> the manufacturer (sifive) for months and months._

Yes, this seems to be the case. The layout is only very slightly different
than the HiFive1, most of the major components are in the same locations.

I was thinking about buying one of these and porting Tock OS [1] (written in
Rust) onto it for a fun personal project. There's been a surprising amount of
work already in the embedded Rust space, and I believe the compiler support
for RISC-V is already sufficient.

[1] [https://www.tockos.org/](https://www.tockos.org/)

~~~
schaefer
that sounds like a really fun project.

I happen to have a hifive1 board laying around. If you get to the point where
you share your results (whether you're looking for collaborators or not),
could you follow up with a link here? I'd love to try it out (alpha/beta
versions are welcome).

~~~
ansible
Sure will. Though I'm super awesome at coming up with personal project ideas,
and significantly less awesome at finishing them.

I'm also working again on a space naval battle RTS game, which is entirely
command-line driven. Written in Rust, using an unfamiliar game engine, because
I can't make things easy for myself. :-)

~~~
gpm
Out of curiosity

\- What does a real time command line driven game look like?

\- What game engine?

Sounds interesting!

~~~
ansible
I'm currently looking at Amethyst (1), because it integrates an entity
component system.

The game is inspired by the Honor Harrington series of novels by David
Weber.(2) The ships in that universe can accelerate at 500g or more, so they
can scoot across a solar system in a reasonable amount of time (hours), but
need to accelerate/deaccelerate the entire time to do that. Consequently,
course selection and manuvering are significant decisions that can decide the
outcome before the fleets even engage in combat.

The individual units are intended to be as smart as possible, keeping proper
spacing, following the rules of engagement, and such. You, the fleet
commander, will be issuing orders much like a modern naval commander would.
And I will be appropriating as much of the lingo as makes sense. "Set course
126 mark 31", "engage at maximum range", "target group baker-3".

The game itself won't try to accurately represent the actual size of a typical
solar system, but instead have everything scaled to that scenarios can play
out in half an hour or so. I may also scale up the size of planets
considerably, to provide obstacles.

Initial plan is for a 2-D game with fairly simple tactical and strategic
views. But 3-D with a Homeworld style interface would be cool.

(1) [https://www.amethyst.rs](https://www.amethyst.rs)

(2)
[https://en.m.wikipedia.org/wiki/Honorverse#Setting](https://en.m.wikipedia.org/wiki/Honorverse#Setting)

~~~
taborj
Please please let us know when you have a need for testers. I'm literally
(like, have it up on my ereader next to me right now) reading through Honor Of
The Queen.

------
rwmj
Should note that these are similar in specs to Arduinos, ie. only a few
kilobytes of memory and a processor similar to a Cortex-M0. You won't be able
to run Linux on them.

~~~
microcolonel
> _similar to a Cortex-M0_

Granted, a very high clocked Cortex-M0+. The clocks are about two and a half
times the highest clocked M0+es on the market AFAICT. What it lacks is
peripherals (especially ADC).

~~~
mattthebaker
Except most M0 cores will have 1 or 2 cycle internal flash memory reads, and
this has slow external flash.

~~~
phkahler
>> Except most M0 cores will have 1 or 2 cycle internal flash memory reads,
and this has slow external flash.

With 16K cache. I'm not sure how you ensure consistent performance though -
make sure your code will all fit in 16K, but is that enough? And what about
the first time through?

~~~
simcop2387
Even on ARM with built in flash you can't ensure that easily. The only way to
do so is to copy code to ram and run from there (most of the M0-4 devices I've
seen don't have an icache). This is because of the way that flash ends up
being read from by them, (I can't remember the correct term, i want to say
something like stop-waits) where the processor ends up waiting for an
indeterminate time period waiting on the flash memory to read the next page.

16k cache is likely enough to ensure stable performance of any given function
and any tight loops you're using but will probably not be enough for the
entire program so you'll still have misses that cause slow downs but it'll
probably not be terribly noticeable unless you're trying to ensure timing over
large functions.

~~~
ctz
"Wait-states" is the term you're looking for.

------
simias
This looks fun. I'm a bit surprised that they went with the Arduino "standard"
with its weirdly spaced headers given that I assume that most of the Arduino
software won't run on the chip. Or did they make a compatible SDK?

Also looking at the specs it seems that the SoC has PWM, UART and QSPI but no
I2C or DAC/ADC. That might make it a bit annoying to port some Arduino designs
to it (although you can always bitbang the I2C). There's also no USB or MAC
unless I missed something. So basically if you want to get data in and out
fast QSPI is your best bet and even that doesn't seem to have a DMA so you'll
have to use CPU cycles to copy everything in and out.

So in summary it's definitely a cool board if you're interesting in hacking on
RISC-V specifically but if you're just looking for a controller for your next
DIY project there are more fully-featured options for cheaper.

~~~
moron4hire
IIRC, most Arduino shields run at 5V logic level, and this is a 1.8/3.3V
device. While I've worked with a few shields that could automatically switch
logic level, I don't think it's the norm.

~~~
Zagitta
It says "IO Voltages: Both 3.3 V or 5 V supported" under the features tab.

------
matoro
Kind of a tangent, but unfortunately Microsemi seems not to be shipping any
further batches of [https://www.crowdsupply.com/microsemi/hifive-unleashed-
expan...](https://www.crowdsupply.com/microsemi/hifive-unleashed-expansion-
board) . For a hardware noob, does anybody know if there's another board that
can be substituted to get PCIe/accessories with the same preconfigured setup?
I saw Xilinx mentioned at a significantly higher price tag ($3500+) but not
sure what sort of work would be required.

------
brianolson
If you want a 320 MHz GPIO focused Arduino board for $60, this is great. Might
be great for open-loop or encoder based motion control. This could probably be
a good 3d printer control board.

~~~
fipple
What are open loop and encoder based motion control, and why is a regular
Teensy etc. Insufficient for it?

~~~
TaylorAlexander
Motion control is control of actuators, like motors for example. Open loop
means driving the motor with no feedback source. Closed loop, alternatively,
means using a feedback source like an encoder or other sensors to measure the
position or velocity of the motor, and then using software that monitors that
sensor and adjusts the control parameters to ensure that the desired position,
velocity, and/or acceleration is achieved. This is referred to as “closing the
loop” because you have the controller going to the motor as one half of the
loop, and the encoder going back to the controller (and the control system
code) as the other half of the loop.

Precise motion control often uses control loops (the loop of code that checks
the sensor and adjusts the output) that run at 20 kilohertz, 40 kilohertz, or
higher. Since the control loop is a bunch of lines of code, this means you
want to execute a bunch of lines of code repeatedly at this high rate of
speed. For example on an 8Mhz micro controller clock running a 40 kilohertz
loop, there’s only enough time to run 200 instructions per loop!
(8Mhz/40kHz=200) 200 instructions isn’t a lot, so it would be tough to run a
complex motion control loop in that space. And if you want to run multiple
control loops to control multiple motors - forget it.

The teensy 32 bit micro controllers are a lot faster - I see a 72mhz and
180mhz option. Either of those would be solid for motion control. However if
you want to control multiple motors and possibly perform some other functions,
such as computing motion commands from G code in the case of a 3D printer
control board, you need all the speed you can get. In that case, these new
boards offer plenty of clock speed to play with!

~~~
fipple
Thanks

------
shittyadmin
Interesting - not quite going for the normal Arduino market. $60 is a pretty
high price tag, but it has a quite high clock rate and should get better
performance.

Tempted to buy one just for making some toy cryptographic applications as the
open architecture makes an appealing feature for those applications.

Ultimately though I think it'd be best if they can get China sold on this
architecture. $2 Arudino compatible boards or $7 espressif boards with wifi
are hard to argue with for most people messing around in the microcontroller
space.

~~~
rwmj
_> Ultimately though I think it'd be best if they can get China sold on this
architecture._

This is happening. There are a few embedded RISC-V cores coming out of China
now. It seems if you have the choice of paying to license an ARM Cortex-M core
or downloading Rocket chip off github, then people are going the download
route.

[https://riscv.org/2018/07/eefocus-article-on-the-progress-
of...](https://riscv.org/2018/07/eefocus-article-on-the-progress-of-risc-v-in-
china/)

[https://github.com/SI-RISCV/e200_opensource](https://github.com/SI-
RISCV/e200_opensource)

[https://www.electronicsweekly.com/news/business/china-
risc-v...](https://www.electronicsweekly.com/news/business/china-risc-v-
consortium-50-members-2018-10/)

Edit: This is _not_ to say that RISC-V is more popular than ARM in the
embedded space. ARM obviously has a huge momentum and vast (billions)
installed base.

------
mkesper
Sounds much faster than an arduino, but not the affordable Linux-capable board
everybody's waiting for

~~~
jpablo
What kind of board is everybody waiting for than the Raspberry Pi(zero) isn't
providing?

~~~
kevin_thibedeau
Documented hardware that works without binary blobs.

~~~
peatmoss
I let OpenBSD’s level of support be my litmus test. If everything on the board
works out of the box with OpenBSD, it probably acheived a high degree of
openness.

~~~
sigjuice
So which boards fit the bill? Thanks!

------
sprash
I don't understand the hype around RISC-V. The single most important
bottleneck in general Computing nowadays is memory latency. However code
density of RISC-V is absolutely underwhelming and does not even beat ARM-Thumb
which is literally decades old.

If it has to be RISC and open why not using something that already has an
existing infrastructure and is well established. E.g. Fully open source
implementations of the SPARC architecture exist for a long time already.

~~~
rwmj
Code density is claimed to be similar to x86 and better than ARM with thumb,
see the bottom of this slide:
[https://www.youtube.com/watch?v=Ii_pEXKKYUg&feature=youtu.be...](https://www.youtube.com/watch?v=Ii_pEXKKYUg&feature=youtu.be&t=13m55s)

More information on the original design (not quite the final design) of the
Compressed extension can be found in the original research paper:
[https://people.eecs.berkeley.edu/~krste/papers/waterman-
ms.p...](https://people.eecs.berkeley.edu/~krste/papers/waterman-ms.pdf)

And ... SPARC. Seriously? Register windows were a failed experiment.

~~~
sprash
In the research paper it literally says that Thump-2 is 7% smaller than RVC,
which is in agreement with my personal experiments.

Also, how are register windows a failure?

~~~
jecel
The Sparc V8 running Solaris took hundreds of clock cycles to handle traps, so
some languages actually performed better by ignoring the register windows and
avoiding the overflow/underflow traps. This one bad implementation hurt the
reputation of the idea in general even though Sparc V9 improved this
significantly.

People also like to point out that the original NIOS processor from Altera had
register windows but they were eliminated from the NIOS II. What they forget
to mention is that Altera claimed this allowed them to make a smaller core
"without hurting performance too much". Which means that the register windows
version was faster, not slower like they want to imply.

