
Low-Power And RF Design Heighten Signal-Integrity Concerns - J3L2404
http://chipdesignmag.com/sld/blog/2010/01/28/low-power-and-rf-design-heighten-signal-integrity-concerns/
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westbywest
A topic not adequately covered in this topic, IMO, is corner-case testing.
E.g. testing across temperature, supply voltage, and especially Si process
variation, in the simplest example. EDA tools of ever-increasing
sophistication definitely help economize on time-to-market, assuming you
understand your tool chain adequately, but it is still actual unit testing, in
temp chambers and similar apparatus, that is your most loyal ally in catching
flaws before production. Indeed, a large video graphics company I interacted
with recently would run their newest cores through corner-case testing across
something like 20 different axes. (Imagine a chip with several voltage
domains, e.g. core, GPIO, memory, and some sort of GHz-domain serialized
interface, now multiply the number of domains by additional factors such as
operating temp and Si process variation, and you get a hypercube representing
all possible corner cases.)

Testing across corner cases is exhausting, and yes, proper design discipline
coupled with EDA proficiency give you a sporting change of avoiding a
reduction in performance goals (at best) or even a re-spin (at worst).

But sending a bad chip to market is often a company-ending act for anyone not
in the Fortune 500.

