

Cache Coherency Primer - BobbyVsTheDevil
http://fgiesen.wordpress.com/2014/07/07/cache-coherency/

======
willvarfar
If you liked this excellent overview, and you're not too tired of me going on
about the new Mill CPU architecture already, you may like that Mill loads
specify their retire cycle and represent memory at retire time rather than
issue time. The Mill is therefore immune to aliasing races. And this works
between cores too!

~~~
zxcdw
Thanks for your hard work on the Mill CPU. It is truly fascinating to learn
about it! I've been waiting for the Pipeline talk for the past week, checking
the website few times a day. :)

And for those who are interested in this type of thing, here's a talk about
the Mill CPU memory system which also touches caches:
[http://millcomputing.com/docs/memory/](http://millcomputing.com/docs/memory/)

------
alain94040
Not very accurate with respect to recent cpus. But decent overview of cache
coherency.

EDIT: apologies for the harsh comment. I'm not aware of public information
regarding recent cpus. I tried to give some more technical details in an
answer below.

~~~
bla2
What do recent cpus do differently?

~~~
alain94040
Just to pick a few statements:

 _by default, loads can fetch stale data_ . No, not really.

 _everything gets even more vague when Out of Order execution is involved_ .
OOO is the new normal. Not to mention prefetching, which completely destroys
any mental model of in-order memory access you could have.

 _Architectures with a weak memory model do the minimum amount of work
necessary in the core_ . I wish. weak memory is very complex. Look up
synchronization barriers for an idea of how messy it gets.

But again, for software developers, that article is good enough.

~~~
jblow
Sorry, but you are drastically underestimating the knowledge and experience of
the author of the article for no other reason than to try and make yourself
look smart, which is failing.

