
RISC-V Pros and Cons - englishm
http://semiengineering.com/risc-v-pros-cons/
======
Nokinside
> It tries to undercut the ARM model of establishing how CPUs or other cores
> should work and how they should be valued.”

Companies are not going for ARM just to license professor ISA's. They also
license and value the underlying efficient and high performance architecture
ARM has developed.

What can happen with RISC-V is that there are several competing IP companies
that develop competing RISC-V architectures and ask royalties and license fees
for their IP. This competition can bring down the cost somewhat. If ARM
royalty is 1.5% today, the cost may be 0.77% in the future. It's also possible
that one company will dominate others with superior design, price and foundry
connections. That company might be ARM, AMD or Intel.

~~~
_yosefk
> Companies are not going for ARM just to license professor ISA's. They also
> license and value the underlying efficient and high performance architecture
> ARM has developed.

Depends on the company. Apple, Qualcomm, Samsung, AMD and Nvidia in fact do go
to ARM just to license the ISA and implement the CPU entirely on their own.
However, the ARM implementations are licensed by a whole lot of smaller
companies. The bigger players are thus pretty much forced to forever chase
ARM's changes to the ISA and implement these. I doubt they mind ARM's price
but I suspect that they might be concerned about ARM's influence.

One big change from RISC-V, if it materializes, would be a standard ISA not
controlled by a single company like ARM, and not evolving through a knife
fight between a few companies racing to extend it, like x86. Will it
materialize? Not sure which way I'd bet.

~~~
Nokinside
>and not evolving through a knife fight between a few companies racing to
extend it, like x86.

Apple others you mention have an architecture license agreement with ARM. It
means that they can develop their own cores but they must have full compliance
with the ARM architecture.

Does RISC-V require fully compliance? If not, RISC-V might be evolving through
a knife fight between a few companies racing to extend it just like x86. When
one company gets large market share, their extensions become de facto
standards.

~~~
nickpsecurity
Probably no compliance requirement given all the derivatives. SPARC is another
open ISA where you might have to comply if saying it's SPARC-compatible along
with a sub-$100 fee. I don't think there's a requirement if you give it a
different name or say SPARC-like.

------
gumby
I'm excited by RISC-V. It has some interesting architectural decisions.

Remember the ARM started in the 1980s was solid but not a breakout
architecture until the early 2000s. The x86's roots lie in the 70s and it took
a killer app ( _IBM_ PC) to make it dominant. GCC took about a decade to get
any traction.

So it's early days for RISC-V

~~~
ShannonAlther
The article says that the developers expect companies to add their own
features and support, so I guess we're just waiting for some established
player or startup to pick up the ISA and roll something out with it?

But it specifically says "same model as Linux", and that bothers me because
RISC-V is not an operating system, and I'm not sure that Linux's business
model is appropriate here...

~~~
komon
Maybe the Chromium->Chrome/Iron/Opera comparison would be a little neater?
That's the way I read it. An open source core with different vendors adding
closed source components as value adds.

------
tgragnato
An issue that's not mentioned is memory consistency. It's not something that's
going to solve without $$, and may pose a serious economical obstacle.

EDIT: coherence -> consistency (sorry)

~~~
jackyinger
RISC-V is just an ISA, which can be thought of a s a very low level API. The
memory (and most other subsystems') architecture is not tied to the ISA.
Rather it has to do with load/store instruction implementation and cache
organization.

~~~
topspin
"RISC-V is just an ISA"

tgragnato wasn't clear enough to be certain about what he/she has in mind, but
the RISC-V ISA specification -- as presently written -- has been shown to have
memory consistency flaws. This emerged in April when Princeton published their
TriCheck findings. RISC-V foundation has since responded by promising
revisions to the ISA specification to close the holes.

[https://www.electronicsweekly.com/open-source-
engineering/ri...](https://www.electronicsweekly.com/open-source-
engineering/risc-v-bugs-found-princeton-2017-04/)

[https://www.electronicsweekly.com/news/design/eda-and-
ip/ris...](https://www.electronicsweekly.com/news/design/eda-and-ip/risc-v-
foundation-replies-princeton-bugs-2017-04/)

------
sweden
People like to compare RISC-V to Linux, which I think it is just wrong.

Linux is something that you can download from kernel.org, compile it and bring
it up over night. It's a package with a bunch of scripts that compiles a
working kernel for your machine. All the work is already done for you.

RISC-V, on the other hand, it is just a document describing an ISA. It is far
different from a working implementation.

RISC-V might shine on micro-controllers and on power management control units,
since those applications are more simple and more affordable to implement from
scratch.

But on high-end applications, it will be no different from ARM's path.
Implementing an high performant CPU costs money, someone will have to cater
those costs, either by hiring a full team of highly specialized engineers
(which will cost a bunch of money) or by licensing to third parties (which
will also cost money through licenses or royalties).

~~~
throwaway40483
As the article (and you) point out, the datacenter and mobile space is already
lost to Intel and ARM respectively. The only path forward is through the IoT
space. It's the only area where you might need something even smaller than
ARM.

~~~
PeCaN
ARM Cortex-M is quite likely much smaller and more power efficient than RISC-V
will be for the foreseeable future.

If RISC-V is going to go anywhere, it's going to have to start with hobbyists
and RaspPi-like devices.

~~~
tnorgaard
Krste Asanovic in
[https://www.youtube.com/watch?v=KxuQW8HWBXI](https://www.youtube.com/watch?v=KxuQW8HWBXI)
shows numbers that the Berkeley Rocket implementation of RISC-V is both faster
and has smaller die size than the ARM Cortex-A5 and that the Berkeley BOOM is
faster and smaller than the ARM Cortex-A9.

~~~
Thrillington
The Cortex-A series are big processors. They're generally used when compute
power is more important than power consumption. While it's a promising
benchmark, the RISC-V will need to compete with the M-series (and other 8/16
bit cores) to break into the IoT market.

------
morio123
"Not everything exists for RISC-V that exists for the other ones, but that is
filling in at incredible pace."

The RISC-V project is now 7 years old. Remember that the 6502 and its
supporting hardware went from proposal to final silicon in 2 years. And that
was done using a hand drawn layout.

~~~
yjftsjthsd-h
The 6502 was also far more primitive; doesn't seem like a useful comparison
point.

~~~
tyingq
~3500 transistors vs millions (tens of millions? hundreds?)

~~~
Flow
But the tooling is much better today. I read that the layout of the 6502 was
mostly made by one person.

[https://research.swtch.com/6502](https://research.swtch.com/6502)

~~~
nickpsecurity
They also weren't working in contraints of 1000+ design rules today's nodes
would need for custom design.

------
redtuesday
Could a chip based on the SuperH ISA (off which the patents expire) [0] like
JCore compete with RISC-V if similar effort would be put into it?

[0]
[https://en.wikipedia.org/wiki/SuperH](https://en.wikipedia.org/wiki/SuperH)

~~~
CalChris
_SuperH_ is 32b so that would need to be updated.

Another worthy contender to be rehabilitated is _DEC Alpha_. Indeed, the
Sunway Taihu Light supercomputer (fastest the on TOP500 list) uses the Sunway
SW26010 which is based on the Alpha 21164.

~~~
redtuesday
From what I have read [0] the j-core people have that on the roadmap for
2019+.

Seeing that Sunway TaihuLight still uses DDR3 I wonder how much power they
could save by going with DDR4 and it's lower voltage.

It's cool to see so many older ISAs coming back.

[0] [http://j-core.org/roadmap.html](http://j-core.org/roadmap.html)

------
mjevans
I didn't read the article, but I have been trying to stay vaguely informed off
and on.

The two 'cons' that really need to be addressed:

* Average consumers need /access/ to purchase working solutions (which means some prosumers and some developers will).

* Working solutions probably need to include: DisplayLink, USB, Ethernet, and /maybe/ WiFi (the later two /could/ just be USB devices) ports on the hardware. Standard bulk IO (like SATA, PCI(e) bus) would be nice to have, but not required.

~~~
Nokinside
Issues you mention have nothing to do with RISC-V ISA.

RISC-V Is just open source ISA, hopefulĺy without any patent issues.

Nobody is going develop open source high performance RISC-V processor
architecture IP and give the design away free. You pay licenses and royalties
just like before.

~~~
tyingq
The RISC-V BOOM project looks like it might do something like that. Or am I
missing something?

~~~
Nokinside
BOOM is something like that. But it's essentially prototype reference design
that is automatically compiled to 45 nm (10-year old process platform).

