

Intel Lifts the Hood on its "Single-Chip Cloud Computer" - ajdecon
http://spectrum.ieee.org/semiconductors/processors/intel-lifts-the-hood-on-its-singlechip-cloud-computer

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jws
• Research chip

• IA-32

• 48 cores, 24 tiles of 2 cores each

• ☞ Caches are not coherent ☜

• On chip message passing system between tiles

• Application level voltage/frequency control to manage power

• 25 to 125 watts, 1.3B transistors

• Has booted Linux

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merijnv
The chip is (in theory) very interesting to work with, but in practice it
suffers a lot due to lack of cache control. Since the L2 cache is writeback
(instead of write-through) and because there is no cache flush instruction you
are forced to manually flush your cache by reading from memory...

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jws
I think that is the point. If people are willing to program in this paradigm
(message passing), then 1000+ core chips are possible.

I think the question becomes: For problems decomposed into a message passing
solution, is a 15x speedup for on die message passing a win at the 1000 core
scale? Or another way around, for the scale problems that work at 1000 cores,
is the message passing overhead is negligible and you can just as well stick
them on separate dies/modules/blades/racks.

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merijnv
I agree that no cache coherency is the entire point of the chip, but the lack
of manual control over things like flushing the cache is entirely unrelated to
cache coherency and a significant issue in some of the things we've been
trying to do on the chip.

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ajays
Dated: 9 February 2010

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patrickgzill
This doesn't seem so exciting once you realize that AMD and Intel are already
shipping 12-core CPUs.

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zmanian
Beyond approx 32 cores, cache coherent architectures don't scale. Intel faces
enormous pressure to find consumer applications for message passing chip
architectures otherwise the post 32 cores chips will be low volume products.
Intel has been working very hard to find collaborators with application
concepts for this era. Having this product permitts Intel to give them
hardware rather that just FPGA simulators

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wmf
_Beyond approx 32 cores, cache coherent architectures don't scale._

It's not clear that this is true. Tilera is shipping 64 cores and working on
100.

