
Intel Reinvents Transistors Using New 3-D Structure - brewski
http://newsroom.intel.com/community/intel_newsroom/blog/2011/05/04/intel-reinvents-transistors-using-new-3-d-structure
======
pilom
Again one of those "I bet AnandTech has the best description out there" and I
go check and am pleasantly surprised.

[http://www.anandtech.com/show/4313/intel-announces-
first-22n...](http://www.anandtech.com/show/4313/intel-announces-
first-22nm-3d-trigate-transistors-shipping-in-2h-2011)

~~~
dreish
Ah, but PC Magazine has "9 things you need to know" about it, which includes
an incorrect explanation of what a nanometer is. I think it's in a sidebar
next to their "38 makeup tips for the summer" article.

------
sjtgraham
This is the sort of thing I read and think to myself "go check HN comments
where someone smart will explain this in layman's terms"

~~~
svjunkie
Agreed. It's all magic to me but it seems like, if this breakthrough can keep
Moore's Law chugging, it's worth a pretty penny. I'm surprised their stock
isn't up more today.

~~~
sliverstorm
The funny thing about silicon is a breakthrough is only worth anything if it
doesn't cost practically anything! (on a per-chip basis)

~~~
eru
Yes, and that's already included in Moore's law, which explicitly talks about
costs per transistor.

------
Symmetry
Awesome! The current a transistor can put out is porportional to the width
over the length and chip designers usually want wide transistors[1], but wide
transistors take up space which causes more line capacitance. This innovation
will let people put more, wider transistors in a given area which will both
increase the current they're putting out and decrease the capacitance they're
fighting against, leading to higher frequencies[2].

[1] Wider transistors also cause more capacitance for the other transistors
that are driving them, but for most modern designs this is smaller than line
capacitance.

[2] Having transistors closer together can also help overcome speed-of-light
delay. This can be important in caches.

EDIT: Also, some stuff I didn't notice until reading the Anandtech article is
that the thinness of the silicon will give you the same artificial limitation
of the depletion region that SOI does, leading to the same accelerated
inversion. Oh, and better isolation from the base too. I don't think that I
can explain that succinctly for non-EEs so go read Wikipedia on MOSFETs if
you're interested.

~~~
daeken
> Having transistors closer together can also help overcome speed-of-light
> delay. This can be important in caches.

But in this case, while they take up less space, the distance is the same --
they're simply traveling up and over, rather than just over. Unless I'm
missing something here.

~~~
Symmetry
The number of things of a given size you can fit on a plane within distance R
of you is proportional to R^2. The number of things you can fit in a three
dimensional space is R^3. So as we utilize 3D more and more things will tend
to be closer together.

~~~
daeken
They're closer together, but the distance traveled in total is the same.
Imagine the transistors are pieces of paper, and you're drawing a line over
them. If the paper is flat, then you're drawing a line of distance _n_ , and
the points are _n_ apart. If you fold the ends of the paper together, then the
points are _0_ units apart (or near enough to make no matter), but that line
still has a distance of _n_.

~~~
Symmetry
Oh, I think I get what your confusion is now. The signal doesn't have to
travel up and over now any more than it did when everything was flat. The
signal will travel up a few gate widths to the low resistance metal
interconnect layers, travel a few tens or hundreds of gate widths sideways to
get to the next transistor, then goes down again to make the connection. Going
to 3D doesn't change this except to make the up and down slightly longer and
sideways much shorter.

~~~
daeken
Ah hah, I see what you're saying now. Thanks for clearing that up.

------
jws
This Intel R&D paper sums the technology up and has a picture that makes it
clear what they are doing:
<http://www.intel.com/technology/silicon/integrated_cmos.htm>

In a nutshell, the drain/source is a tall trace, the gate approaches from the
side and climbs over the drain/source, covering it on three sides.

~~~
ableal
The good stuff (discretely linked from the press release) is here:
<http://newsroom.intel.com/docs/DOC-2032> . In particular, this PDF has color
drawings of the devices, and SEM pictures:
[http://download.intel.com/newsroom/kits/22nm/pdfs/22nm-
Detai...](http://download.intel.com/newsroom/kits/22nm/pdfs/22nm-
Details_Presentation.pdf)

It is as you said - instead of the gate controlling the flow in a shallow
ditch (the old "2D" does have some depth ;-), they built up a pipe and the
gate is the choke around it.

Well, that should help stem the pesky leakage current problems that plague the
deep sub-micron technologies ...

------
tspiteri
The New York Times has an article:
<http://www.nytimes.com/2011/05/05/science/05chip.html>

The article links to some graphics:
[http://www.nytimes.com/imagepages/2011/05/05/science/05chip_...](http://www.nytimes.com/imagepages/2011/05/05/science/05chip_graphic.html)

------
sosuke
I liked Engadget's coverage of the release
[http://www.engadget.com/2011/05/04/intel-will-mass-
produce-2...](http://www.engadget.com/2011/05/04/intel-will-mass-
produce-22nm-3d-transistors-for-all-future-cpus/)

I'm a sucker for videos. This Tri-Gate tech was first announced in 2002, I
love seeing pie in the sky technology come into reality and widespread usage.

~~~
riffraff
the videos are at the same time incredibly good and incredibly bad, thanks :)

~~~
ot
They are even better than the "get perpendicular" video by Hitachi
<http://www.youtube.com/watch?v=-xPvD0Z9kz8>

------
stephenjudkins
From what I've heard, using 50% as much power for the same performance as the
previous generation still will not be sufficient to bring Intel's Atom
performance/energy consumption ratio to that offered by ARM chips. However,
it's a huge leap in the right direction. Add better-designed power-saving
features on the next generation of Atom chips, and future process shrinkages,
and it's easy to see ARM's lead getting chipped away until it's gone.

~~~
ajross
This is orthogonal. An ARM Cortex (or GPU, or whatever) on this process would
see similar gains.

It's also worth pointing out that current Atoms in the market are still 45nm
parts, not even 32nm. Intel, for obvious reasons, tends to prioritize
production of high-margin desktop and server CPUs over low-margin embedded
parts.

Really, this announcement isn't about ARM-based vs. Intel-based SoC designs. I
think it's clear that Intel has some catching up to do there. This is about
Intel cementing and extending its _complete and total dominance_ of high end
digital logic fabrication. At this point they look to be about a full two
years ahead of everyone else. AMD, IBM, Samsung, TI, TSMC and the rest of that
crew have to be more than a little worried.

Objectivity disclaimer: my wife is at Intel working on precisely this 22nm
process. So I'm about as biased a source as you can find.

~~~
tesseract
> This is about Intel cementing and extending its complete and total dominance
> of high end digital logic fabrication.

Given that, (and given that Intel has been dominant in process technology for
some time now) I've always wondered why Intel doesn't do fabrication for third
party, high-performance/high-margin/high-power-budget products that don't
directly compete with Intel's main CPU product line. Networking/telecom
processors, top-end FPGAs, DSPs, and so forth. Is it just that they are at
capacity making CPUs and don't see any need to get into that business? Or do
they do it already and I'm just not aware?

~~~
nitrogen
They are going to fab some FPGAs for a company called Achronix:
[http://www.eetimes.com/electronics-news/4210263/Intel-to-
fab...](http://www.eetimes.com/electronics-news/4210263/Intel-to-fab-FPGAs-
for-startup-Achronix)

<http://www.achronix.com/>

I've worked with audio equipment that uses FPGAs, CPLDs, and DSPs for various
purposes, and being stuck on relatively-ancient processes makes that equipment
generate a lot more heat and fan noise than would be necessary with DSPs and
FPGAs on a modern process.

------
bradly
Anyone know if the 3D structure is patented by Intel? If so, wouldn't this
give Intel a monopoly on transistors given how much better this new design
performs?

~~~
megaframe
No this design was developed back when I was in college, the revolutionary
change here is that Intel has a process to actually manufacture these things
effectively and get decent yield. IBM had these things built in test cases
back in 2007 but didn't have a manufacturing method.

Intel will likely not patent or reveal the manufacturing method thats how most
semiconductor manufacturing technologies go. They tend to be trade secrets
that are a combination of process and machinery which your competitors are
unlikely to ever reproduce exactly, so no point in patenting it.

~~~
bradly
Thanks, that makes sense. I did find this patent from Intel about
manufacturing the 3D transistor:
[http://www.google.com/patents?id=1D2gAAAAEBAJ&printsec=a...](http://www.google.com/patents?id=1D2gAAAAEBAJ&printsec=abstract&zoom=4#v=onepage&q&f=false)

------
FrojoS
Looking at these pics
[http://www.nytimes.com/imagepages/2011/05/05/science/05chip_...](http://www.nytimes.com/imagepages/2011/05/05/science/05chip_graphic.html?ref=science)
its almost impossible to not get the feeling, that we are still in the stone
age and a bright future lies ahead of us.

------
nextparadigms
I think this will mostly help increase the life expectancy of the Moore's Law
by another 10 years or so. When we'll get to 11nm or whatever is the limit,
we'll just start stacking layers of transistors on each other. That will only
work until the chips become too thick, though.

~~~
SlipperySlope
Intel is projecting to be at 10nm in 2015, way ahead of the industry
lithography roadmaps published five or ten years ago.

Below 10nm, Intel and other fabricators will start looking beyond CMOS,
perhaps to carbon based structures.

~~~
nextparadigms
I wouldn't say way ahead. They are about a generation ahead.

When Intel was at 45, the ARM makers were 65. Intel at 32, ARM makers at
40/45.

When Intel will be at 22. ARM makers will be at 28/32. When they'll be at
10nm, ARM will be at 14nm using IBM's foundry.

~~~
SlipperySlope
I agree with what you said, but I'm sorry you misunderstood my point. The ITRS
lithography roadmaps for years have assumed that lithography would advance at
the rate of 36 months between nodes, e.g. between 45nm and 32nm. But in
response to AMD competition in the previous decade, Intel introduced their
"tick-tock" cycle in which Intel advances the lithography node every 24
months. Other CPU fabricators have been forced to keep up with Intel's pace,
and as you point out they have been a process generation behind.

As a result, 10nm will be released in 2015, rather than 2020 as ITRS predicted
in much earlier roadmaps.

What gets real interesting in just a few years is how Intel and others will
get below 10nm. Could be a shift to carbon based structures will be necessary.

------
SlipperySlope
Curious as to what clock speeds will be available when Ivy Bridge is released
in the first half of 2012? If one expects a 37% performance increase at low
voltages, then what would be the performance increase at standard voltage? 20%
or so?

~~~
SlipperySlope
Anantech gives a gate-delay chart and explains that Ivy Bridge will be 18%
faster at the standard voltage compared to Sandy Bridge. That might mean Ivy
Bridge CPU parts at 4 GHz as compared with Sandy Bridge parts at currently at
3.4 GHz.

------
vondur
I often wonder at the incredibly small size of these chips (22nm) if the have
to worry about relativistic effects of electrons "jumping".

~~~
nightlifelover
The quantum tunneling effect [1] is what you are referring to, right?

[1] <http://en.wikipedia.org/wiki/Quantum_tunnelling>

~~~
vondur
Yes, sorry, been a while since I took P-chem.

------
deweller
A couple of highlights from the article:

"The key to today's breakthrough is Intel's ability to deploy its novel 3-D
Tri-Gate transistor design into high-volume manufacturing."

"The 22nm 3-D Tri-Gate transistors provide up to 37 percent performance
increase at low voltage versus Intel's 32nm planar transistors."

------
acgourley
"Moore's Law" is mentioned 14 times.

~~~
JacobAldridge
I wonder if Gordon Moore had worked for IBM instead of being an Intel founder,
whether that number may have been a _slight_ bit smaller.

~~~
SlipperySlope
Absolutely! IBM's was never motivated to improve performance for their
mainframe and minicomputers as quickly as Intel improved performance for
microprocessors.

Really, Moore's law is a sort of management principle rather than any kind of
physical law. Simply, Intel introduces new fabrication process technology at
the pace which optimises their profits.

Advance too slow and competitors will take the business, advance too fast and
capital costs are higher, plus customers need payback on their current
purchases. Advance at just the right pace and customers are motivated to
replace perfectly good products just a few years old.

------
bryanallen22
I don't mean to trivialize this, but "reinvent" sounds a little strong to me.
This is a modification on silicon design, and a great one, but is just another
notch in the miracle of Moore's law. It's more evolutionary than
revolutionary.

See 2007 for a similar announcement and reaction:

[http://hardware.slashdot.org/story/07/01/27/1614207/Intel-
IB...](http://hardware.slashdot.org/story/07/01/27/1614207/Intel-IBM-Announce-
Chip-Breakthrough)

------
schmittz
Although not the link for this story, the fact that this story broke in the
NYT (not that surprising), with an explanation to attempt transistor design
and functionality (incredibly surprising) is really uplifting. A good piece of
purely anecdotal evidence against those who claim America is in perpetual
intellectual decline. The general populace IS interested enough to try to
understand complex ideas.

------
slackerIII
Will this allow them to increase clock speeds? They mention a 37% perf
increase, but I don't know what exactly they mean by that.

~~~
riledhel
Clock speed is just another metric, not the most important one. You also have
chips that do several operations per clock cycle, low power consumption chips,
chips that do parallel processing. All these factors affect performance as
well.

~~~
tspiteri
That may be true for a processor, but when talking about transistors, I think
that clock speed and power consumption are the metrics to measure.

~~~
repiret
I would argue that neither of those things are metrics to measure for a
transistor, since they are affected by how its used. Properties of the
transistor itself are what matter: size, drain and source capacitance, leakage
current when off, drain-source voltage drop when on, and probably a dozen
things I don't really know about.

~~~
tspiteri
The properties you mention are mainly "low level" properties, which in the end
affect the "high level" properties that are speed and power consumption. For
example capacitance limits clock speed and also has an effect on power
consumption, and leakage current reduces power efficiency. Capacitance and
leakage current themselves depend on size. I think that the physical
properties you mention (and maybe others) may be used to create a model, which
can then be used to estimate clock speed and power consumption at different
operating points.

------
makmanalp
"the world's first 3-D transistors, called Tri-Gate, in a production
technology"

I wonder if this is truly Intel's invention or not:

[http://scholar.google.com/scholar?hl=en&q=tri+gate+trans...](http://scholar.google.com/scholar?hl=en&q=tri+gate+transistor&btnG=Search&as_sdt=0%2C22&as_ylo=&as_vis=0)

~~~
zosi
All of those papers either post-date Intel's announcement from 2003 regarding
tri-gate transistors, or are written by Intel employees. That search also
brings up multiple patents held by Intel on the technology.

------
DonnyV
Its funny how at the end of the day basic shapes are still an important rule
in technology :-)

------
GavinB
It will be interesting to see whether patents will make this a defensible
innovation. Will AMD et all have to invent a similar but materially different
technology in order to keep pace?

~~~
sosuke
Considering Intel first announced the Tri-Gate tech in 2002 AMD would have to
had been working on something for 9 years to be launching a competitor anytime
soon.

~~~
marshray
Why wouldn't they have been?

------
rbanffy
After watching the video I have to wonder: why not use the shrinking ray to
reduce the transistors themselves?

------
helium
Great, now I won't have to learn Erlang for a few more years

------
pcora
Anyone care to explain this to a normal person? :)

~~~
andrewcooke
It's building electronic components vertically instead of laid out flat (think
of a book stood on an edge rather than laid down, kind of). That has two
advantages - they take up less room and they don't leak so much electricity to
the silicon that they're sitting on.

~~~
pcora
Thank you! :D

------
PawelDecowski
Who at Intel thinks type set at 12px is legible?

------
rkon
Intel stock is up 2% and ARM is down 6% (was down 7.7% in London trading).
Looks like their Apple-esque announcement strategy has had some impact.

~~~
illumen
Apple obviously had a heads up on this - since they announced the switch to
intel not long ago. Which means they had insider information. I wonder if
anyone made billions off it.

------
kin
sometimes i feel like intel should space out their chips more. as a consumer i
feel like i can't keep up.

~~~
absconditus
Why do you need to keep up?

~~~
wtracy
As a consumer he might not have any good reason to do so, but look at it from
Intel's perspective: They're potentially not getting the best return on their
R&D investment by encouraging customers to regularly skip generations.

~~~
space-monkey
Most people don't upgrade their CPUs. Most people don't know what generation
their CPU is from when they buy.

------
espeed
This is a big win for graph DBs that need to scale up rather than out.

