

Intel at ISSCC 2015: Reaping the Benefits of 14nm and Going Beyond 10nm - DiabloD3
http://www.anandtech.com/show/8991/intel-at-isscc-2015-reaping-the-benefits-of-14nm-and-going-beyond-10nm

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toufka
This article proposes that the naming convention of using feature size is
becoming more and more marketing and less and less connected with an actual
distance. [1] Does anyone around here know what the state of the resolution of
these chips' features actually is? I'm curious about the actual precision of
these modern lithographic techniques. I presume at some point you get into
Heisenberg's territory and things get much (differently) harder.

[1] [http://spectrum.ieee.org/semiconductors/devices/the-
status-o...](http://spectrum.ieee.org/semiconductors/devices/the-status-of-
moores-law-its-complicated)

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nhaehnle
Here's a report of a scan of Intel's 14nm technology:
[http://www.chipworks.com/en/technical-competitive-
analysis/r...](http://www.chipworks.com/en/technical-competitive-
analysis/resources/blog/intels-14-nm-parts-are-finally-here/)

A good example for the problem with naming conventions is that Intel's 14nm M1
has lower pitch (i.e., lower distance between wire centres) than the 14nm
technology of competitors; at least as claimed by Intel some time last years
and apparently confirmed by the linked article.

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minthd
One way around this problem(of different densities for transistors and wires),
is a new metric that multiplies the resolution of both(lower is better).
Intel's metric is 3640, Samsung is 4990.It's from [1].

So Intel has 27% area advantage over Samsung. Although of course it's very
design dependent.As for cost, there are other parameters, so it's a bit harder
to tell.For example, today's 28nm is cheaper than the denser 20nm because it's
a simpler process.

[1][https://www.semiwiki.com/forum/content/3884-who-will-
lead-10...](https://www.semiwiki.com/forum/content/3884-who-will-
lead-10nm.html) \- if i'm not mistaken samsungs's 16nm should be 14nm.

