
5th RISC-V Workshop Preliminary Agenda - cheiVia0
https://riscv.org/2016/10/5th-risc-v-workshop-agenda/
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microcolonel
Very excited to see the V extension is already in a proposal-quality draft.
It's the last big piece separating RISC-V from data-heavy consumer and server
workloads.

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phkahler
>> Very excited to see the V extension is already in a proposal-quality
draft...

And Go on RISC-V, and a JVM, and video decode instructions, and security work,
VM work, thousand core concepts, dev boards, multiple hardware
implementations, better simulators, and all the rest. This shit is getting
real very quickly.

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rwmj
Any more details available on this SiFive development board?

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microcolonel
By the numbering, it seems like it would be one of their embedded form-factor
platforms as a dev board.
[https://www.sifive.com/products/freedom/](https://www.sifive.com/products/freedom/)

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rwmj
I wonder if it will be FPGA based or use an ASIC. Also if it will have a block
device and network, which are the drawbacks of the current platform.

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rjsw
It wouldn't be that hard to have a network interface for the FPGA
implementations. The Zynq SoCs have two network interfaces, though most dev
boards only connect one of them to a connector.

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erichocean
RISC-V has serious momentum.

