
Open Source FPGA Toolchain Builds CPU - jamesbowman
http://hackaday.com/2015/07/28/open-source-fpga-toolchain-builds-cpu/
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nickpsecurity
It would be interesting to see someone put JOP on FPGA through the toolchain:

[http://www.jopdesign.com/](http://www.jopdesign.com/)

Then maybe academics in INFOSEC can try to put JX OS on it for secure,
embedded apps:

[http://www4.cs.fau.de/Projects/JX/](http://www4.cs.fau.de/Projects/JX/)

Native Java means no breaking out of JVM's model down to weird native code.

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sklogic
Icestorm and yosys are cool!

Since then even more CPUs are working on ICE40:

[https://github.com/cliffordwolf/picorv32](https://github.com/cliffordwolf/picorv32)

Or a really small and slow one (smaller than J1, but needs more RAM):
[https://github.com/combinatorylogic/soc/tree/master/backends...](https://github.com/combinatorylogic/soc/tree/master/backends/tiny1)

~~~
listic
But does it use an open source toolchain? Also, where does it say that it runs
on ICE40?

~~~
bri3d
PicoRV32 absolutely runs on iCE40 and the open toolchain. Check out
scripts/icestorm and [http://www.clifford.at/papers/2015/yosys-icestorm-
etc/slides...](http://www.clifford.at/papers/2015/yosys-icestorm-
etc/slides.pdf)

~~~
gluggymug
The target is the iCE40 HX8K according to the slides (p17) not the icestick
unfortunately.

It uses 1521 LUTs with Yosys. The icestick is a HX1K which has 1280 LUTs I
think.

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ZenoArrow
Will put this here just in case anyone is interested, it's a FPGA Hat for the
Raspberry Pi, based on the iCE40 FPGA.

[https://github.com/xesscorp/CAT-
Board/blob/master/README.md](https://github.com/xesscorp/CAT-
Board/blob/master/README.md)

------
grandalf
I was looking at IceStick kits the other day and they appear to be backordered
> 11 weeks.

~~~
xellisx
I bought one a while back ago, then I realized the number of I/O's was very
low for what I wanted to do. Would have been nice to have access to all the 95
I/O's of the iCE40HX-1K instead of just 16 (or is it 26?)

~~~
grandalf
I agree. The FleaFPGA has GPIO IO but still not all the IOs.

[http://www.fleasystems.com/fleaFPGA.html](http://www.fleasystems.com/fleaFPGA.html)

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placeybordeaux
I always thought the advantage of a FPGA is that they are very fast when
programmed for a specific task. This seems like an interesting project, but is
there a case where this would be preferred over any given CPU?

~~~
blackguardx
You can add instructions on the fly or switch CPU architectures on the fly. Go
from a MIPS clone to an ARM clone. The main advantage of FPGAs is flexibility.

~~~
nickpsecurity
Flexibility and lower development costs. ASIC developments cost hundreds of
thousands to tens of millions. FPGA's give you low development cost but
relatively-high, unit price.

~~~
vvanders
Also at a higher power usage as well.

~~~
nickpsecurity
Yes. There's been good work in that space to make some of them use hardly any
power where unnecessary and asynchronous ones (eg Achronix) could take it even
further. Yet, always will be behind on ASIC's on power usage. I don't see them
getting around that.

~~~
ZenoArrow
There's also the idea of 'baked' FPGA's, which are a middle ground in
performance between FPGAs and ASICs, but at a much lower cost than ASICs.

EDIT: Looks like Altera no longer offers the HardCopy option, do any of its
competitors offer something similar?

[https://www.altera.com/products/general/asic.smartphone.html](https://www.altera.com/products/general/asic.smartphone.html)

~~~
0xcde4c3db
Xilinx advertises "EasyPath" as an ASIC alternative, but I'm pretty sure
that's just a form of cost reduction for the exact same FPGA chips (by
enabling them to use defective chips where the specified bitstream doesn't hit
the defect?) rather than an actual "hard" option.

~~~
nickpsecurity
Now _that_ is interesting. Ive neither heard of nor though of that in FPGA's.
It's a proven trick given it was used by AMD for Tri-Core processors which
were Quad-Core processors with a faulty, disabled core. Now I'm wondering if I
should ask more vendors about for discounts haha.

