
10nm versus 7nm - jsnell
http://semiengineering.com/10nm-versus-7nm/
======
dmarcos
I've been following the semiconductor news in the last year closer than ever
before. It really feels that the 7nm node will be the end of Moore's law. As a
software engineer it intrigues me the constrains is going to impose to our
craft in the next decade. We've been riding the performance exponential growth
that allowed us to be sloppy programmers and still produce increasingly
complex software. I work on the VR space and the conventional wisdom is that
headsets and GPUs are going to get drastically smaller and powerful every
year. I think this is not a given anymore and as a software practitioners we
will have to step up the game and be much more careful about using resources.
How is the end of Moore's low going to affect the cost of Software
Development? The top software companies will be those that best use the
hardware. Performance optimizations usually makes software more complex and
increases the rigor you operate in. Many people have been able to got from 0
to make relevant contributions after learning programming in a few months or
going through a coding bootcamp. That might get harder and harder since you
will need deeper knowledge to produce competitive software. Is this going to
increase the barrier of entry for developers? Is the developer pool going to
shrink? Salaries go up? Is it going to be more a and more expensive to produce
competitive software? Will it make software startups more capital intensive,
since gluing 4 pieces of existing code around a good idea won't be enough to
be successful?

~~~
thesz
Moore law is about number of transistors per chip (IC). You can make
transistors smaller, you can make chips larger, you can stack chips and you
can make integrated circuits from several parts.

I think your feeling is wrong.

~~~
speeder
What you are saying is PRECISELY why Moore Law ended with 7nm.

Mind you, performance improvements didn't ended, we can still find other ways
to do things...

But 7nm is the smallest physically possible transistor (well, theoretically it
is 5nm, but that one can't be actually manufactured).

So, you hit 5nm, then what? Your only choice would be make chips larger... but
if you do that, you limit your maximum clock (example: a 5cm processor, if it
allowed data to travel at light speed, and had perfect cooling, would still be
limited to 6ghz)

Or make them taller, but then you can't cool them easily.

That is the problem, Moore Law, as in transistors per chip, ended with 7nm,
there is nowhere to go after that, the only thing you can do is add more chips
and make them communicate with each other (ie: multi-cpu... see what AMD has
been doing in their recent research, trying to figure how to make an API to
allow infinite amount of GPUs in the same calculation in a way 100%
transparent to the developer).

But making more chips is not improving Moore's Law.

The only thing that can be done now, is invent something else, silicon
transistors are done for, you can't improve them much anymore, you can only
change the tech (use something else other than silicon transistors) or find
novel ways to use current silicon tech (better architectures, multi-chip
systems, better code, etc...)

~~~
logicallee
>Or make them taller, but then you can't cool them easily.

Haven't you answered your own question? Your other points are about
impossibility - the one I just quoted, about making chips taller, is about
difficulty.

If I were the head of Intel I would say "Well. Hmmm. All right. I guess we'd
better start making them taller."

Moore's law is not a question of "how hard can it be". As you've pointed out,
on the current approach it's a question of "It is physically impossible for us
to increase transistor count without dropping the clock rate or moving out of
roughly a plane. No thanks to Einstein. (My favorite link on this subject:
[https://www.google.com/search?q=c+%2F+4+ghz](https://www.google.com/search?q=c+%2F+4+ghz)
)

You say "Or make them taller, but then you can't cool them easily." Well then,
make them taller and cool them with difficulty. Nobody said it would be easy.
Off-hand you could:

-> Immerse the taller chip in insane cooling

-> Fabricate little duct work between layers and liquid cool at high velocity

-> Figure out a way to reduce heat waste usage, e.g.: different substrate, not silicon (pretty insane)

-> Possibly combining some of the above points, make it a superconductor.

These are insane ideas from me. But then again, I'm not the head of Intel and
you've heard a few minutes of thought on me on this topic, where I'm not a
chip designer.

"When you have eliminated the impossible, whatever remains, however
[difficult], is your [roadmap.]"

~~~
NegativeK
Without getting into semantics, Moore's Law roughly assumes that things will
get cheaper or you'll get significantly greater bang for your buck. "Nobody
said it would be easy" is a casual dismissal of the fact that consumers won't
pay for this, unless someone conjures a materials revolution.

And no, we can't just assume the head of Intel will conjure up a materials
revolution solely to adhere to an industry observational law.

~~~
logicallee
I don't know, man:

[https://en.wikipedia.org/wiki/Moore's_law#Moore.27s_second_l...](https://en.wikipedia.org/wiki/Moore's_law#Moore.27s_second_law)

This talks about an _exponential_ increase in R&D costs which is expected by
Moore. With stuff like cloud computing, I don't see the need for denser and
denser CPU's going away any time soon.

------
kbob
> “It will take chip designers about 500 man-years to bring out a mid-range
> 7nm SoC to production,” Gartner’s Wang said. Therefore, a team of 50
> engineers will need 10 years to complete the chip design to tape-out. In
> comparison, it could take 300 engineer-years to bring out a 10nm device, 200
> for 14nm, and 100 for 28nm, according to Gartner.

My mental model of this process is completely wrong. I thought they'd have a
Verilog code base, and moving to a new process was basically a recompile.

What are they doing for 100/200/300/500 man-years, and why do the smaller
processes take longer?

~~~
sweden
If you are speaking of the digital designs, yes, what you say is absolutely
right.

But you need to keep in mind the analog designs. While a typical CPU, a
typical GPU or a typical cryptographic IP chip (for a example) can be
developed in just Verilog since they are just pure logic, when you move to the
Mixed Signal IP, you can't use only Verilog, you have to manually design parts
of the chip (creating the schematics of the designs at the transistor level
and converting them to layouts).

Examples of mixed signal IP are USB, HDMI, MIPI, Ethernet, PCIe, and so on.

We don't have tools capable of synthetizing really fast PLLs, DCOs, Band Gaps,
most of the high speed analog blocks.

But I think the article was exaggerating on the "50 engineers will need 10
years to complete the chip design to tape-out". I work at Synopsys and we are
already working on the latest process nodes (10nm, 7nm, 5 nm) and we already
have some solutions ready for silicon and it didn't took us 10 years.

All these articles make it sound so dramatic that it's nowhere near the
reality. The process of designing the analog blocks again in 10nm, 7nm, 5 nm
and so on, it's exactly the same every time. It is very much like porting your
C++ code to Python: sure you have to do it from scratch but the process and
the fundamental concepts are exactly the same.

It's not rocket science nor quantum physics, it's easier than it sounds. The
main problem is the huge cost of the tools and of the technology from the
foundry. If you are past that, you just need time and some knowledge in micro-
electronics.

Don't be fooled by these over dramatic articles, the hard part of digital and
analog design is not getting the knowledge to do it, it's getting the money to
have the proper tools to do it.

~~~
bhouston
Great response. Got a question for you then: are we actually hitting the end
of Moore's law here or are we just before a new technology transition for
CPUs, such as away from silicon.

~~~
sweden
We are indeed hitting the end of Moore's law.

The companies that provide IP are watching the market splitting into two: the
companies that want the latest process node to show off technology (for
example, Apple, Samsung, Huawei, etc) and the companies that want older but
stable process nodes (IoT companies and the automotive industry).

When most of the articles speak of the newest process nodes (for example, the
5nm process node) they only touch the economics part of it: "it's expensive,
it's costly". But they don't mention the many problems that come with it: it's
unstable, there is much more current leakage which increases power consumption
unexpectedly, it is not suitable for long longevity and the architecture of
your analog blocks have to take into account all these problems which don't
exist in the older process nodes.

It is possible to produce solutions in 5 nm, but the question is no longer
about if we can do it or not. The downsides os these nodes go beyond the
engineering resources and the economic resources that are needed to achieve
them.

That is why the automotive industry is not interesting in these kind of nodes.
They want the stable and cheap nodes like 28nm and 40nm, they know that these
nodes are well tested and have long longevity.

We are also reaching a point in which we already have enough advanced
technology for our needs, we need to start to get rid of the need of reaching
the next process node in order to have better hardware.

------
wallacoloo
> TSMC is moving from a 2D layout scheme at 16nm to 1D technology at 10nm. 1D
> layouts are easier to make in the fab, but they involve more restrictive
> design rules.

What is a 1D layout? Surely it must be something of a misnomer, as the only
way I can visualize it is as a barcode, where each material you place has to
span the entire width of the chip - and that seems utterly worthless.

~~~
Panoramix
Some high end processes only allow you to pattern a bunch of parallel, narrow
lines (hence 1D). These are subsequently "cut" in a useful way, and you can
connect to them using a different layer above or below.

------
mjrpes
Could anyone help me understand why is it 9 times more expensive to design a
chip at 7nm than 28nm?

I would have naively thought chip design is fairly automated, but a 9x
increase makes is sound like every gate and path is delicately hand-stitched
like a Persian rug.

~~~
deegles
I think it's because at that point they can't use a single "mask" for the
lithography and have to do multiple exposures with different masks. The
equipment is also fabulously more expensive. The D1X site will have $6 billion
invested: [http://www.bizjournals.com/portland/news/2012/10/24/intel-
pl...](http://www.bizjournals.com/portland/news/2012/10/24/intel-plans-
massive-expansion-to-3b.html)

~~~
mjrpes
I can understand the dramatically increased costs with chip production. But
the article makes it sound like the 9x increase is with the design of the chip
(e.g., with an HDL simulator).

~~~
yaantc
The design cost is increasing. It's not as in software where you write high
level code (Verilog for IC) and let the compiler do its job, and in most cases
you're done. For IC design, there's a two part process: the front-end design
in Verilog, and then the back-end design to map this to the process
implementation. With old nodes, the back-end was a simple affair and mostly
automated --- software like. But with more advanced nodes it's no longer the
case. The tools need proper constraints to generate something that will work
(like timing constraints), and this need human input. And at the most advanced
nodes, it's common that when you reach the back-end work one realize that the
design is not good enough and need to be tweaked to let the tool generate a
good implementation. This creates round-trips between back-end and Verilog
level design. And these are slow and expensive round trips (synthesis, tests
in the loop are heavy).

So it's far from fully automatic. There's a lot of work done on the tools, but
there are also a lot of additional constraints to deal with with each new
nodes. It's a real complexity explosion, and this is what makes designs on
advanced nodes so much more expensive. This a highly simplified description
but hopefully enough to get a feeling for what's going on.

~~~
adapteva
Simply not true as a general statement. There is a completely automated path
from Verilog to GDS through modern EDA tools. While the back end complexity
has increased, the folks at Synopsys, Cadence, Mentor have solved all of the
problems for the designer (IR drop, cross talk, DFM, OCV, etc). Good designs
have fully automatic flows with a turnaround time from RTL to tapeout of less
than 24hrs.

~~~
KSS42
In theory but not in practice. 24hr RTL to GDS has been the promise, but the
design and process complexities keep growing.

Depending on the complexity of the chip, the backend process takes several
months. It's an iterative process. A reasonable complex chip has to be split
into several partitions. The size of the partition determines the turn around.
In the designs that I have worked on, we try to limit the turnaround time
(RTL->GDS) to be one week for the larger partitions.

I would change your statement to say that the EDA vendors have created tools
that allow Physical Design engineers to address the design challenges. It is
still a gruelling, iterative, painstaking process.

~~~
adapteva
Agree with you. Taping out chips is still like going to the dentist for a root
canal. Still, we may have to disagree regarding the absolute numbers. For
every one of our chips so far, we made RTL changes less than 24 hours before
tapeout. (clearly this means our basic blocks are very small and we don't have
a lot of them).

------
Animats
Smaller line size doesn't mean more compute power any more. Clocks maxed out
around 3GHz some years ago. For CPUs, getting rid of the heat has become the
limiting factor. (Yes, with aggressive cooling you can go faster, but most
systems don't go there.) Electromigration is starting to limit component
lifespans.

But that's for CPUs. Memory, especially mostly-inactive memory such as flash
devices, still has a few iterations ahead. Memory devices can tolerate and
recover from bad cells and bad rows. There's also the option of going 3D and
stacking memory. That doesn't work for CPUs because getting the heat out of
the middle is very tough.

The other big problem is cost. Fabs have become multi-billion dollar projects.
The article says that designing an SOIC for 7mm costs upwards of $200 million.
(Why? Design tools? Mask making?) If cost per gate declines, we can still get
more compute power by making bigger parts with more CPUs. Single CPU
performance probably isn't going to climb much more, though.

Fortunately, most of the things we want to do in machine learning and AI can
be done in parallel. This problem isn't going to keep us from getting to AI.

------
aexaey
Wait, did I read this right - Intel is going to be the last one to get 10nm?

> Samsung, for one, plans to ship its 10nm finFET technology by year’s end.

> TSMC will move into 10nm production in early 2017

> Intel will move into 10nm production by mid-2017

~~~
eloff
Yes, that's what a lay reading gets you - and why I was disappointed with the
article. Is the author just clueless or are they trying to make one of Intel's
competitors look better? Everyone who follows these things knows that the
other guy's 14nm node is more comparable to Intel's 22nm node. Apparently a
nanometer is not always a nanometer...

~~~
i73668012
The only thing you should be disappointed with is your reading comprehension.
There are three paragraphs dedicated to your complaint.

>“Not all 10nm technologies are the same,” said Mark Bohr, a senior fellow and
director of process architecture and integration at Intel. “It’s now becoming
clear that what other companies call a ‘10nm’ technology will not be as dense
as Intel’s 10nm technology. We expect that what others call ‘7nm’ will be
close to Intel’s 10nm technology for density.”

>It wasn’t always like that. Traditionally, chipmakers scaled the key
transistor specs by 0.7X at each node. This, in turn, roughly doubles the
transistor density at each node.

>Intel continues to follow this formula. At 16nm/14nm, though, others deviated
from the equation from a density standpoint. For example, foundry vendors
introduced finFETs at 16nm/14nm, but it incorporated a 20nm interconnect
scheme.

~~~
eloff
Missed that, I withdraw my complaint. The snark is not necessary though, not
everyone has time to read the entire article, I read the top and skimmed the
rest.

~~~
testrun
And you start your comment with:

 _Yes, that 's what a lay reading gets you - and why I was disappointed with
the article._

------
martinald
I think people are really underestimating how poor CPU performance improvement
has been recently; it's been totally masked by I/O (SSD) and RAM improvements.

Before SSD it was common to see a CPU wasting >50% of its time waiting for IO.
Now you rarely see iowait being a problem.

------
abecedarius
> For a 10nm chip, it takes $120 million for the design cost, plus 60% for the
> embedded software.

I don't understand: 60% of what? What embedded software?

~~~
adapteva
Put simply "stuff". Take a look at Fred Brooks, mythical man month if you
haven't ready it already. The projects that cost $250M will have over 1,000
engineers involved. Running a tightly coupled engineering project of that size
is impossible in my opinion, thus the cost. Figure that 50% of the budget goes
to communication overhead, 25% to management overhead, and you are left with
25% of true engineering costs.

------
Lind5
Pain Points at 7nm also an interesting read [http://semiengineering.com/pain-
points-at-7nm/](http://semiengineering.com/pain-points-at-7nm/)

------
cft
One interesting consequence is that this will probably impose a ceiling on
Google's growth.

------
MichaelBurge
> Then, there is the cost-driven decision. This is for foundry customers who
> may have lower volume products. They may not recoup their investment at
> 10nm. So, it makes more sense for them to skip 10nm and move to 7nm.

Why is it cheaper to design a 7nm chip for a given performance than to design
a 10nm chip? The article mentions the yields on newer processes are lower, so
I would've expected them to be the performance option not the cost option.

~~~
quickaccount
It isn't. But if you move straight to 7nm you only need to recoup the costs
for 7nm, not 10nm + 7nm.

------
freekh
I wonder if this will create create a market asics and FPGA when the lasts
drops of perf has been squeezed out of the cpus (and GPU)?

~~~
zanny
Once we hit the wall of general CPU performance we will probably retrace a lot
of old school custom hardware design. Expect a lot of the parts integrated
into a CPU today to move back out, but simultaneously we will have to start
shipping more sophisticated cooling solutions for denser CPU chips (since the
main reason bridges were integrated were because dense cores were getting too
hot for copper / aluminum fin heat transfer like most heatsinks).

It will take a really long time to actually squeeze out CPU optimization. We
are still contending with most software not even properly scaling to four
cores, let alone well implemented job queue systems for arbitrarily scaled
cores. And once the chips start dropping in price as the node standardizes and
companies can lay off the intense R&D investments, we can start introducing
more heterogeneous compute clusters to drive performance cheaper even when the
silicon itself is stuck until graphene takes the market.

------
amirhirsch
"Moore's law is dead" is mostly false every time it's written. I would expect
fixed costs to drop for 7nm so that more designs can go ASIC and benefit from
lower cost per transistor and higher performance. Seems like even if we were
locked at 7nm, decreasing NRE for custom SoCs will yield performance
improvements for a long time coming.

~~~
monocasa
I mean, that's like saying it's not really a car accident because even though
the front of the car is crushing into the divider wall, the rear of the car is
moving at almost the same speed.

------
dc2
Anyone else getting a 404?

~~~
nuand
Yea, I am too

