
Verilator: Fast, Free Verilog HDL Simulator - steven741
https://www.veripool.org/wiki/verilator
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bpye
Verilator is an awesome tool. I suggest if you are interested in open-source
EDA this you also check out Icarus Verilog [1] - an event based Verilog sim,
Yosys [2] - a Verilog synthesis tool and formal solver, and NextPNR [3] - a
place-and-route tool. The set of these provide a pretty reasonable set of
tools for developing hardware (that is HDL) with fully open source software!

[1] - [http://iverilog.icarus.com/](http://iverilog.icarus.com/) [2] -
[http://www.clifford.at/yosys/](http://www.clifford.at/yosys/) [3] -
[https://github.com/YosysHQ/nextpnr](https://github.com/YosysHQ/nextpnr)

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bem94
There's a longer curated list of general HDL languages and tools here:
[https://github.com/drom/awesome-hdl](https://github.com/drom/awesome-hdl)

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analognoise
Verilator has some serious limitations:

    
    
      The driving test bench is C/C++
      It is a cycle simulator, not a delta-time simulator: it will 
      only simulate synthesizable code (not test bench code) 
      It cannot do back-annotated timing simulations
      It cannot use encrypted vendor libraries (no simulations with Xilinx IP, for example)
      It has no mixed-HDL language capabilities
      It requires Gtkwave to view waveforms with (opinion, but I hate the UI)
    

It is a terrible recommendation for beginners - you'd be much better served by
using Xilinx Vivado's inbuilt simulator and waveform viewer.

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q3k
The first two are a feature for me. Not to mention not being crippled by
Xilinx 'IP Core' DRM.

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analognoise
Crippled by extant, available code which is shipping in millions of devices?

Is it perfect? Hell no. But it's a bit _drastic_ to throw out an entire
catalog of the most battle-tested HDL code in the world, isn't it?

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qalmakka
During my short experience with hardware design at the university I never had
the chance of using Verilog. Are there advantages in using it instead of VHDL?

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Cyph0n
In my experience, it's:

1) Less verbose and easier to write, but slightly more "error" prone (think:
Java vs. Python).

2) More widely used in industry. VHDL is more heavily used in the defense
industry (it came out of DoD).

3) Better support for verification (e.g., SystemVerilog).

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TD-Linux
One cool thing you can do with Verilator is use the API to simulate other
hardware. For example, here's a Verilog Gameboy being simulated realtime by
simulating the display attached to it:
[https://twitter.com/zephray_wenting/status/11126917323936645...](https://twitter.com/zephray_wenting/status/1112691732393664512)

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analognoise
You can do this with any simulator that has a FFI interface - just use the
SystemVerilog DPI.

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celeritascelery
The verilator team also wrote the verilog mode for emacs. Very well done.

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jdsully
I met the author at a conference about 6 months ago. Very nice guy. Verilator
is a really good way to test your designs if your building something non
trivial.

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amann11
Does anyone have links to free analog design tools?

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fest
Free as in beer-free or free as in Stallman-free?

Former: LTSpice (also runs under wine).

Latter: ngspice

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fxfan
And how does one get a cheap FPGA board out of it? China? Any recommendations?

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TD-Linux
Verilator is only a simulator, once you want to run it on a fpga you use yosys
+ nextpnr. The icestick is a popular and cheap choice to get started, there is
also the TinyFPGA BX and iCEBreaker if you would like a few more features.

