
An open source Xilinx Spartan 6 miniPCIe development board - polysome
https://github.com/polysome/aggregate-1
======
TD-Linux
Really nice design! Impressive routing, I was surprised you were able to fit
two DDR chips on there as well.

It's still too bad that all the tooling for this is closed source (Altium,
Xilinx ISE / Vivado, with the latter being far more offensive). But the
Spartan 6 is a really nice chip otherwise.

It seems like the target application is compute acceleration. Do you have any
particular applications in mind?

~~~
mng2
It should be mentioned that the '100T device pictured actually requires the
full paid version of ISE. The free-as-in-beer ISE Webpack only supports up to
the '75T. Thankfully Xilinx implemented compatible packages through the device
family, so lower devices are a drop-in replacement (mostly).

Maybe one day we'll have a Free toolchain, but FPGA tools are much closer to
chip design tools than to compilers, and the space is fraught with patent
concerns. However I did read on Deep Chip that some fundamental synthesis
patents have been invalidated, which might open up some breathing room.

~~~
mindcrime
Supposedly, a lot of key FPGA patents are set to expire Real Soon Now, or just
did, or something along those lines. I'm holding out hope that we'll have a
true Open Source FPGA environment sooner or later, but it sure is taking it's
time... :-(

~~~
Tomte
Are patents really what's blocking it?

I only have a passing understanding of the FPGA world, but I thought that
everything in that space in shrouded in trade secrets. Do patent claim
descriptions really have enough detail to help you produce a working
bitstream?

~~~
analognoise
No - it's the massive investment in tooling.

I see comments like these all the time about 'open source bitstream
generators' and whatnot. If you have a very simple, regular architecture, then
P&R (place & route) is relatively simple, and has been done (there is an open-
source bitstream generator for the Lattice iCE40 chips, see
[http://www.clifford.at/icestorm/](http://www.clifford.at/icestorm/)). This
line from that page in particular: "It has a very minimalistic architecture
with a very regular structure. "

For anything close to a modern FPGA, the P&R is only the start of the problem
- timing is the next big one. Having a large design not meet timing can be a
nightmare, but the tools take delay (extracted from the design) into account
for routing, so you'd have to add that; also, I think the amount of effort to
get the "hard macros"/specialized in-silicon blocks configured correctly would
be amazing. You'll notice that even in the iceSTORM project, PLL's and timing
analysis are not yet implemented. I use the Xilinx Zynqs at work, and they
contain high speed serdes, dual-core ARM processors, and a boatload of other
items.

There are large teams who are employed full-time, and frequently get their
Masters/PhD with a specialty in VLSI/EDA, developing these algorithms, testing
them extensively, and then implementing them. With the money someone like
Xilinx brings to the table, they can pick those individuals out from school
directly.

It isn't a CPU, and it never will be. I'm amazed at what free software can do,
but I just don't think a team without substantial financial backing and
extreme expertise could ever even approach the problem.

All of this is without even considering errata that might exist for the FPGAs,
or security features at the silicon level - items which will become different
immediately after a free solution is announced. Why? There's zero incentive
for Xilinx to allow a free software competitor, and they have the IC designers
- BOOM! The next generation adds something goofy that means a team would have
to decap a chip, and start probing it. Also, said team has to be able to probe
something at 28nm or below. The freaking optics for that kind of work start to
get expensive by themselves, let alone the lab you need with floating tables
and microsteppers (depending). A team might have to install a special floor to
even get the kind of mechanical precision necessary - let that sink in. Who
the hell has the money for that? I'll tell you who - other nations. We've used
the security features on FPGAs (from Actel and Xilinx both) to prevent another
NATION from figuring out our algorithms. The goal is to make it so costly to
reverse-engineer as to make development of your own entire system seem like a
saner approach.

No. There will never be an open-source bitstream generator for a modern FPGA
for the same reason the Apollo project required a nation's financial backing -
SpaceX can get to LEO (Low Earth Orbit). They just don't have the money, time,
or manpower to get people to the moon. And if they did, they still wouldn't be
"free software" \- I guess a better comparison than SpaceX would be Copenhagen
Suborbitals.([https://en.wikipedia.org/wiki/Copenhagen_Suborbitals](https://en.wikipedia.org/wiki/Copenhagen_Suborbitals))

TL;DR - No, there will never be a free software bitstream generator for any
kind of modern FPGA, for a multiplicity of reasons.

EDIT: If anyone is interested in trying to do a free software FPGA, you'd have
to design it from scratch and try to be a fabless semiconductor company. 1
seat of the EDA tools for IC design (on a modern node) vary - but at the last
place I worked they used Mentor Calibre, and I think it was somewhere between
50/100k? It would be fun to design one on an older process, but it would be
laughably expensive, slow, and power hungry compared to more modern FPGAs.
Bonus though: it will have better TID (total incident dose) radiation
hardness, although it wouldn't be a serious contender unless you implemented
scrubbing/error detection or a unique rad-hard transistor setup (then you'd
need to pay to have it sent to a reactor and tested, which is a PITA - trust
me).

~~~
TD-Linux
Wow, that's a ridiculously defeatist attitude. Comparing reverse engineering a
FPGA to landing on the moon?

First of all, it's a relatively new field for open source. The icestorm
project only got a complete synthesis to bitstream pipeline working last
month. So although you see "comments all the time", it's not like development
is stagnating. In fact, it got off the ground for the first time. It's not
surprising it lacks support for hard peripherals at this point in development.
Lack of timing analysis is a showstopper for any serious design as well, but
it's not like it's an unsolvable problem.

>There's zero incentive for Xilinx to allow a free software competitor What?
How is another system that sells their chips a competitor? AMD reacted to open
source driver development by providing documentation for their GPUs. The exact
opposite seems kind of an extreme position. Xilinx is already pretty open
source friendly on the software side with their Linux kernel contributions.
And it's not like they are the only vendor in existence.

The security features on FPGAs right now are to prevent people from getting
the bitstreams out. Just like on virtually every modern microcontroller. That
hasn't stopped open source toolchains one bit.

FWIW I've done designs on the Zynq too, it's certainly one of the most
complicated cases and I doubt it will have open source support any time soon.
But most of the critical stuff is in the hard blocks (e.g. ddr timing and the
like), and it's actually the easiest because there is not really any p&r work
to do there, it's just figuring out what the configuration bits are.

(sorry if I sound overly defensive, I work on free video codecs and get a very
similar attitude out of many other people who feel that performant video
codecs are not possible outside of MPEG. it gets incredibly frustrating)

------
imrehg
Oh, nice! On the other hand, seeing this on HN now I feel really inadequate,
having just finished the prototype of my miniPCIe Arduino clone last
weekend... Really need to level up too!

KiCad source of the PCIeDuino:
[https://github.com/moonpunchorg/pcieduino](https://github.com/moonpunchorg/pcieduino)

Pictures: [http://imgur.com/a/XiJ12](http://imgur.com/a/XiJ12)

~~~
adisbladis
Which ARM-board you are using in those pictures?

~~~
imrehg
It's a VIA VAB-600 Springboard. There are some other VIA ARM boards that can
do mini-PCIe (though some just USB, some do PCI too)

VAB-600: [http://www.viaspringboard.com/](http://www.viaspringboard.com/) or
[http://www.viaembedded.com/en/boards/pico-
itx/vab-600/](http://www.viaembedded.com/en/boards/pico-itx/vab-600/)

VAB-820: [http://www.viaembedded.com/en/boards/pico-
itx/vab-820/](http://www.viaembedded.com/en/boards/pico-itx/vab-820/) (better
software, Freescale SoC)

VAB-1000: [http://www.viaembedded.com/en/boards/pico-
itx/vab-1000/](http://www.viaembedded.com/en/boards/pico-itx/vab-1000/) (at
the moment Android only)

I hope to try other vendors' ARM boards too, I've made a list a few weeks ago
of those that have mini-PCIe connectors, so plenty to experiment with....

(disclaimer, I'm currently working at VIA)

------
Smushman
[http://polysome.io/](http://polysome.io/)

The manufacturer.

What purpose is this useful for?

Can someone elaborate?

~~~
polysome
Originally we built this board for a custom security enhanced SoC design based
on OpenSPARC T1. It was to run OpenBSD from the microSD card and operate as
the baseband controller for a new type of wireless network node.

The board could be repurposed for the lowRISC project. It is also suitable for
use with embedded routers and laptops as a crypto coprocessor or HSM.

We are pairing the first batch of prototypes with the PCengines apu1d4
(w/coreboot) and will provide these reference platforms to developers.

To be considered for a unit you need to compile a bitstream of the OpenSPARC
T1 for the LX150T variant of this board.

Email development@polysome.io for more details

Thanks for all your encouragement !

Just wait till you see what's coming.

------
vardump
So there's a serial flash on board? How many milliseconds max it takes to load
the bitstream to FPGA after power on? Can you load PCIe endpoint within PCIe
spec alotted time, 100 ms?

Is partial bitstream reprogramming possible?

~~~
duskwuff
The FPGA is an XC6SLX100T, so the bitstream could be up to 26.7 megabits. It
could take up to two seconds or so to configure the part with a large design.

~~~
vardump
So is it possible to load bitstream in parts, enough for basic PCIe endpoint
within 100 ms to conform to PCIe spec and then load a bigger design
afterwards?

~~~
jeff_marshall
Ugh, that time window.

I once had to work with a hardware team to debug a "boot issue" where we were
right on the margin due to a two-phase boot process (boot initial bitstream,
check journal in flash, load active bitstream) and didn't even realize going
into the debugging that we were close to the margin.

It's nice to be doing plain-old software again...

~~~
vardump
Which platforms are the most demanding regarding PCIe time window? Which ones
caused you problems?

------
userbinator
The FPGA itself is around $160. Not cheap, but not expensive either (look at
some of the high-end Virtex devices for an idea of how much _expensive_ FPGAs
cost...)

------
aceperry
Excellent looking design. This could become a big deal for the maker
community. I'm glad to see so much open source stuff coming out for hardware.

------
vineeth
Pretty cool. Does the board show up as PCIe endpoint if it's plugged into a
laptop?

~~~
duskwuff
Not on its own. You'd have to implement an endpoint on the FPGA to make it
show up. (Same as most USB microcontrollers won't show up on the bus until
there's appropriate code running on them.)

------
AdieuToLogic
Way cool hardware! Kudos to the team putting this out.

------
acd
What is the speed of a Xilinux Spartan 6 compared to an recent Intel i5-i7
series cpu?

~~~
throwaway7767
What is the cruising altitude of a Boeing 787 compared to a VW beetle?

You cannot compare these things in this way, it's apples and oranges.

