
Intel's 14nm Technology in Detail - jsnell
http://anandtech.com/show/8367/intels-14nm-technology-in-detail
======
Osmium
> Intel for their part is nothing short of extremely proud over what
> advancements they have made over the last several years to make their 14nm
> process a reality

And so they should be. From the outside looking it, this slow creep of
progress might seem inevitable, but it's anything but. Every new process node
they hit is a huge achievement, and I greatly admire Intel not just for
managing it, but doing it on a timetable planned years in advance too. The
fact they're only missing their goals by a few months here and there is
nothing short of incredible (in my personal opinion).

To put it another way, some things you can put a price tag on, but fundamental
research isn't usually one of them. Pouring billions in and getting steady
results out is something that sounds easy, but really isn't, from what I've
seen of it.

~~~
rm999
Completely agreed, and it's hitting a dangerous point where not enough
companies are putting in the necessary investment. I studied quite a bit of
both VLSI/chip design and economics in college, but I never fully understood
what was behind Moore's Law until I read this quora comment:
[http://www.quora.com/Moores-Law/For-how-long-will-Moores-
Law...](http://www.quora.com/Moores-Law/For-how-long-will-Moores-Law-continue-
to-hold/answer/David-Crawley-1)

Here's a snippet:

>The limits of Moore's Law is not driven by current technology, after all if
we knew how to go smaller we probably would have done it. The limits of
Moore's Law are really a matter of cost. Each new node shrink increases the
technology development cost in a fairly predictable way by about 40%. The
result is that Moore's Law is limited by economics.

> ...

> When [Intel] figures out that they don't have invest so heavily to stay
> ahead then Moore's Law will slow

Moore's Law doesn't exist in a vacuum - the cost to keep Moore's Law going has
been increasing exponentially, and fewer and fewer companies have been able to
keep up.

~~~
JoachimS
The semiconductor industry is that - an industry with numerous companies
providing the materials, equipment, operations etc needed for Intel, TSMC,
Samsung to build and run their fabs.

In order for this to work, there is a need for coordination. The manufacturers
of steppers for example must be able to deliver a stepper that can draw
features with the needed resolution at a given time. Since the development
takes time, they and everybody else needs to communicate and decide how fast
Moores law progress.

Moores law thus represents what all parties agree to are what can be achieved
and can meet the end user requirements over time. The industry organisation
responsible for this is ITRS - The International Technology Roadmap for
Semiconductors:

[http://www.itrs.net/](http://www.itrs.net/)

If one wants to see the predictions for Moores law, ITRS have documents
available that are well worth studying. When I worked on ASIC design for
mobile handsets we looked at these documents for product roadmaps since we
could predict the power consumption, gate density etc for future process
nodes.

Intel can to a higher degree than many others move forward at their on pacing.
But they don't make their own fab from scratch nor produce their materials all
by themselves. This means that even if Intel is able to develop a process in
the lab that provides smaller feature size, efficiency and whatnot than what
is agreed upon. But they can't move that much faster than the rest of the
industry if they want to manufacture chips in commercial quantities.

~~~
zokier
> But they can't move that much faster than the rest of the industry if they
> want to manufacture chips in commercial quantities.

Maybe not, but on the other hand Intel began mass-producing 22nm CPUs in 2011,
while TSMC has began volume production on their 20nm process this year.

------
omegaham
Oh hey, that's my job.

I work in the Failure Analysis division; my job is to take an electron
microscope and look for defects in wafers that come out of the fab. Our
results get sent to the engineers, who make the changes in the fab and make
more wafers for us to tear apart. I don't think I'm allowed to say much about
it, but it's a pretty cool process, and I'm happy that I decided to move up to
Hillsboro to work for them.

~~~
williadc
I worked on Broadwell and other 14nm projects and would be interested in
chatting with you. My IDSID is dwilli2, please drop me a note.

------
readerrrr
Webcast( recorded ):

[http://intelstudios.edgesuite.net/140811_intel/event.html](http://intelstudios.edgesuite.net/140811_intel/event.html)

[http://www.intc.com/eventdetail.cfm?eventid=149021](http://www.intc.com/eventdetail.cfm?eventid=149021)

------
el_duderino
"The end result is that while Intel’s cost per transistor is not decreasing as
quickly as the area per transistor, the cost is still decreasing and
significantly so."

Maybe... The problem is, is Intel saying this as (honest) engineers or as
(somewhat less honest) business people? Every IP business has enormous
flexibility in how it defines costs and where it places them. nV's complaint
reflects the cost it pays, which ultimately reflects some sort of aggregated
cost for TSMC over not just per-wafer manufacturing costs, but the costs of
R&D, of equipment, of financing, of various salaries, etc etc. Intel, in a
graph like this, has the flexibility to define basically whatever it likes as
"$/transistor". On the one hand, it could be an honest reckoning (basically
the TSMC price), but on the other, it could be a bare "cost of materials and
processing", omitting everything from capital expenditures to prior R&D.

------
shmerl
Hopefully Intel 14nm SoCs will be competitive in handsets at last. And open
GPU drivers will enable native Linux + Wayland on them.

~~~
pjc50
_open GPU drivers will enable native Linux + Wayland on them._

I too would like a personal handheld unicorn, but I don't think it's likely to
happen.

~~~
shmerl
libhybris + Wayland have already happened (in Jolla handset). So having Linux
+ Wayland on native drivers would be even better.

------
blt
Anyone got a reference for the number of atoms in the pitch of 14nm
transistors? I recall it was pretty low for 22nm and it's surprisingly hard to
find this information.

~~~
zokier
Wikipedia says the following:

> Silicon, like carbon and germanium, crystallizes in a diamond cubic crystal
> structure, with a lattice spacing of 0.5430710 nm

So I suppose that means 14nm feature would be 26 atoms?

~~~
danbruc
The order of magnitude is correct. The interconnect pitch being 52 nm means
that the width of a wire plus the isolation to the neighboring wire is just
under 100 atoms.

------
typon
Very low on details...but I guess that is to be expected.

