
Arm brings custom instructions to its embedded CPUs - lelf
https://techcrunch.com/2019/10/08/arm-brings-custom-instructions-to-its-embedded-cpus/
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cesarb
This sounds like an answer to RISC-V, which was designed to have custom
instructions since the beginning (to the point of reserving large blocks of
the instruction encoding space for custom instructions). AFAIK, most current
RISC-V designs target the same product space as the Cortex-M mentioned in this
article.

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panpanna
I would not say this is on response to riscv. First of all, ARM was one of the
very few vendors not supporting before but mainly due to their co-processor
model. Second, the reason arm in giving in now is due to new performance
requirements for v8-m due to crypto and ml usecases.

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olliej
My interpretation of this (based on what the article says) is that you are
providing an opcode->[instructions or microcode?] mechanism?

Which seems unlikely to be correct, because they already have licenses that
allow new instructions/features.

So is it actually "this instruction should be turned into these signals to
these ports"?

(I'll try to read the white paper once I'm not on a phone)

~~~
olliej
Ok, so based on [https://www.arm.com/why-arm/technologies/custom-
instructions](https://www.arm.com/why-arm/technologies/custom-instructions)

It sounds like this is that you get to specify custom RTL for a given opcode,
you are still restricted to whatever functionality is in the standard ALU.

The problem I'm having with the public docs is that they all seem to say "you
can replace this [hand coded assembly example] with [a custom opcode]", but
don't give an example of the actual implementation of the opcode. That would
at least show some sense of what is possible.

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teddyh
What is old is new again:

“I guess it is one of the disadvantages of VLSI that it's no longer so
feasible to add instructions to your machines.”

— Richard Stallman, 1986 ([https://www.gnu.org/philosophy/stallman-
kth.html](https://www.gnu.org/philosophy/stallman-kth.html))

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teh_klev
Here's a direct link to their white paper:

[https://pages.arm.com/rs/312-SAX-488/images/Arm-Custom-
Instr...](https://pages.arm.com/rs/312-SAX-488/images/Arm-Custom-Instructions-
for-Armv8-M_.pdf)

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saagarjha
How exactly does this work? Is it a poor man’s FPGA?

~~~
detaro
It's a standardized design for chip manufacturers to make it easier for them
to add custom instructions in hardware to an ARM core and provide toolchain-
support for it, not something software-programmable for the end-user.

~~~
panpanna
Since op mentioned FPGAs:

Do you recall NIOS custom instructions? It's similar to that in many aspects.

