

FPGAs for fun & hacking - jacquesm
http://www.fpga4fun.com/

======
alain94040
<http://university.eve-team.com/> has a university program by now through
which you can access some real high-end hardware, you can try to contact them.

The nice thing with using an emulation system versus a raw FPGA board for
learning is the same as debugging software with a source code debugger versus
only having access to the disassembly.

In my experience, great hardware designers automagically write Verilog but
think schematics.

A classic:

    
    
      always @(posedge clk) begin
        q1 <= d;
        q2 <= q1;
      end
    

Do you visualize the back-to-back flip-flops, and immediately double-check
that the code uses non-blocking assignments? If so, you're fine. If the code
used blocking assignments, you'd have a major bug.

And finally, most senior designers still get puzzled by one of my favorite
quizzes:

what is the functional difference between those pieces of code, that both
represent a flip-flop with async set/reset, one expressed in Verilog and one
expressed in VHDL:

    
    
      always @(posedge clk or negedge rst or posedge set) begin
        if(!rst) q <= 0;
        else if(set) q <= 1;
          else q <= d;
      end
    
      process begin
      if(not rst) q <= 0;
        else if(set) q <= 1;
          else if(clk'posedge) q <= d;
      end process;

~~~
CamperBob
I give up. Something to do with the use of literal ints without width
designators?

~~~
djf
Assuming the second one is supposed to be VHDL, there are so many syntax
errors that I can't figure out what the OP's intent is...

~~~
djf
After a think, ignoring the VHDL syntax,I think the Verilog example has edge
sensitive set/reset, whereas the VHDL has level sensitive set/reset? I don't
write Verilog mind so I'm guessing a bit...

~~~
nwomack
You are correct in the edge sensitive set/reset from a simulation standpoint.
If reset is asserted, then set is asserted, then reset is de-asserted, then
the flip-flop will remain in reset. It's not truly asynchronous from a
simulation standpoint.

This could be fixed by using:

always @(posedge clk or rst or set)

I am guessing the thing that throws a verilog designer off the trail is that
"always @(posedge clk or negedge rst)" is commonly used for asynchronous reset
in ASICs (if you are using it in FPGA's except for the DCM's and as input to a
clk-rst module.... stop), and this works just fine but if you want to do a d
flip flop with an asynchronous SR condition, you can't use "negedge" on the
rst signal.

However, synthesis will probably treat it asynchronously. Of course this is
also bad because there will be a simulation/synthesis mismatch.

At any rate, the question is a bit ambiguous due to the unclear vhdl code.

~~~
alain94040
You found the problem, congratulations.

Both code samples are the recommended way to generate an asynchronous
set/reset flip-flop for an ASIC flow (minus my bad memory about details of the
VHDL syntax).

For years, Design Compiler has forced ASIC designers to describe level
sensitive pins (set or reset) as if they were edge triggered, which is correct
in most cases, except the case you outlined.

So those two codes generate the exact same logic after synthesis, but you can
have mismatches with simulation. And there is actually nothing you could do
about it to fix the Verilog since you need your synthesis tool to understand
your intent. The correction you propose is the correct one from a simulation
viewpoint, but DC would reject it.

Luckily, the case where you assert both set and reset on a flop to then
deassert reset are fairly rare...

I was on the IEEE standardization committee for VHDL synthesis: since then I
know why [some] standards don't make sense.

------
krisneuharth
Does anyone here know a good entry-level book on FPGAs and VHDL or Verilog
that covers best practices and implementing real world designs? In school I
did some work with FPGAs and may have to brush up for an upcoming work
project. I have "HDL Chip Design" by Douglas J. Smith from school but I am
hoping there is something else out there that has helped people here.

~~~
CamperBob
I've heard good things about that book by Douglas Smith but haven't looked at
it yet.

Out of several (expensive) books I _do_ have, these are the ones that've been
most helpful:

\- Verilog HDL Synthesis by Bhasker \- FPGA Prototyping by Verilog Examples by
Pong P. Chu \- Advanced FPGA Design by Kilts \- The two "Learning By Example
using Verilog" books by Richard Haskell (these are actually written
specifically for use with the Digilent Nexys2 board I mentioned in an earlier
post)

Many of the others are impractical, academic junk that waste your time with
things like gate-level design, Karnaugh maps and the like that are handled by
the synthesis tool nowadays. Unless you are writing a synthesis tool you don't
need 75% of what's in most HDL textbooks.

~~~
CamperBob
Well, thanks for swallowing carriage returns between lines that begin with
"-". Maybe an elementary book on C programming would be a better starting
point for whoever wrote this forum software.

~~~
prodigal_erik
<http://news.ycombinator.com/formatdoc>

Blank lines separate paragraphs. Leading hyphens don't do anything. And asking
Paul Graham to rewrite a web forum _in C_ is like sending Lance Armstrong to
Paris on a unicycle.

------
kqr2
Also, does anyone recommend a particular FPGA development board?

~~~
guicifuentes
I've bought recently a <http://www.xilinx.com/products/devkits/HW-SPAR3E-SK-
US-G.htm> (Xilinx Spartan 3E starter kit).

Those Mac OSX users, what do you use for development? The Xilinx development
software seems to work only in Windows and Linux.

~~~
philwelch
There's fairly little choice in FPGA development software. Xilinx is what I've
used, and it's easily the among the worst software I've ever encountered. But
I've heard that the alternatives are no better. The fact that it works at all
is no small accomplishment but it still lacks all elegance, usability, or
reliability on the user end.

