
Report: TSMC's 3nm Fab Could Cost $20B - baybal2
https://www.eetimes.com/document.asp?doc_id=1332419
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toufka
Is 3nm an actual measure of a distance, or is it entirely a marketing term
like 3G cell phone service? I can't quite get a straight answer. As far as I
could tell from outside the field it felt like at ~15nm the measure stopped
being a measure of a feature, and more a measure of precision, and then a
'version' to be decremented rather than relating to a 'meter' in any way. When
I look at electron micrographs of the transistors they don't appear to be 3nm
in size... Anyone able to help here?

At 3nm, you get smaller than a biological protein and have features with
countable numbers of atoms. And as far as my education went, quantum effects
start to dominate, and bulk material properties start to (mis)behave very
differently.

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Waterluvian
Oh god. Their versioning system uses a unit of measurement that is
decrementing towards zero. Those poor souls!

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hinkley
At this point a measure based on some number of average gates per square
millimeter (won't that be fun to get everyone to agree to) would be better
advertising, and more truthful.

Working on an areal density works better in an era where improvements are
going closer to linear.

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jlebrech
why not just use more millimeters. if you don't invest $BNs in making smaller
dies you can just sell bigger chips. and also charge more for a BIGGER and
BADDER chip every year. then when it gets out of hand use a smaller process
intel has abandoned already.

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pg314
Price is proportional to die size. Processing one wafer is a fixed price, so
the more chips you can fit on one wafer, the cheaper each individual chip.

Additionally, the number of defects is proportional to the area. The bigger
your chip, the more chips you will have to throw away because of defects. E.g.
say you have one defect per wafer on average, if your chip takes up the whole
wafer, you will have no good chips. If you can fit 100 chips on one wafer, you
will have 99 good ones and one bad one.

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jlebrech
yes, i'm aware. but i'm sure the "processing cost" also factors in R&D to get
to that node size up to that point.

you also don't need to double the die size just double the size of the package
(what AMD seem to have done), that way you can swap broken dies out.

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darkmighty
Correct me if I'm wrong, but I don't think AMD physically swaps out defective
cores. I believe they're disabled individually in some kind of firmware.
That's effective because the interconnect region is significantly smaller than
the core area (and possibly made more reliable through feature size
manipulation?). I think this has been standard practice almost dating back to
multi-core introduction, where they sell high end multi-core chips as low end
with some cores disabled.

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gsnedders
Note parent was talking about _die_ and not _cores_.

AMD are shipping multi-chip modules with ThreadRipper (with two die) and EPYC
(with four), and then because they are separate die you can trivially swap
them out.

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jlebrech
i believe this is a way for them to maximise yield, say their threshold is at
least 3 dies must be good, and only 1 can be passable, then when they do tests
and only 2 are good, they can swap out one of the passable ones, they can also
rate the cpus differently too, they could also just swap out dies when all
fail the test, i.e with threadripper and replace with another 2, then rate
those.

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mmanfrin
3nm is hugely smaller than anything else I've heard of. I know Intel is stuck
at 14nm, and Samsung is at 10nm for their ARM chips (? someone correct me on
that) -- could someone educate me on what 3nm chip technology means? Would it
be 3x the speed density/possibility compared to 10nm chips?

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vorotato
Would it even work I think is the more meaningful question. Last I heard we we
having trouble with electrons tunneling across the gates as we got smaller.

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tankenmate
You have to start wondering if they will use quantum behaviour like Anderson
localisation that sets up a standing wave effectively stopping electrons from
tunnelling in certain places (design it to bias against and/or stop gate leak
tunnelling). Svitlana Mayboroda discovered a lanscape function that allows you
to predict (and hence design) this kind of behaviour. As to how actively using
these kinds of quantum behaviour affects feature size / speeds / feeds /
yields will probably eat several tens of millions / years as well.

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ChuckMcM
One wonders how "real" this announcement is and how much of it is positioning.
The press releases from TSMC isn't very informative[1].

As interesting as it is to consider that someone might actually be putting
money on the table today, given the pains people seem to be having with the
7nm node I would not expect to see even a 5nm node until 2022 - 2023.

That said, if they _do_ get to a 3nm node, assuming that actual circuit
elements are 3 - 9nm that is still a lot of billion transistor chips on a
wafer. I'm guessing 30% of the wafer would be consumed with die pads rather
than actual chip :-)

[1]
[http://www.tsmc.com/uploadfile/pr/newspdf/THWQGOHITH/NEWS_FI...](http://www.tsmc.com/uploadfile/pr/newspdf/THWQGOHITH/NEWS_FILE_EN.pdf)

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gwern
GlobalFoundries was estimating $14-18b would be needed for the next generation
of chip fabs: [https://venturebeat.com/2017/10/01/globalfoundries-next-
gene...](https://venturebeat.com/2017/10/01/globalfoundries-next-generation-
chip-factories-will-cost-at-least-10-billion/view-all/) Their CEO notes that
the 3nm or 5m numbers being tossed around aren't really too meaningful, but
the budgets speak for themselves.

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manigandham
Side note, for anyone interested in how chips are produced, this is one of my
favorite videos:

 _Indistinguishable From Magic: Manufacturing Modern Computer Chips_

[https://www.youtube.com/watch?v=NGFhc8R_uO4](https://www.youtube.com/watch?v=NGFhc8R_uO4)

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abpavel
Atomic radius of Silicon atom is 0.11nm, which results in width of about
0.22nm. So even tightly packing atoms will make the barrier only ~13 atoms
thick. Van der Waals radius is about twice that, resulting in 7-atom-wide
barrier. Quantum tunneling [0] is apparent at 3nm, and gets worse from there,
so I don't see how they would be preventing electrons leaking through the
barrier, unless "3nm Fab" would have a shovel of marketing salt to boot.

[0]
[https://en.m.wikipedia.org/wiki/Quantum_tunnelling](https://en.m.wikipedia.org/wiki/Quantum_tunnelling)

~~~
typon
None of the technology node names have corresponded to actual physical gate
length since probably the 45nm node.

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phyller
The eetimes article is just a short summary of the actual article at
[https://www.bloomberg.com/news/articles/2017-10-06/tsmc-
read...](https://www.bloomberg.com/news/articles/2017-10-06/tsmc-ready-to-
spend-20-billion-on-its-most-advanced-chip-plant)

~~~
amelius
I thought this article was more interesting, and also has interesting
comments:

[https://www.eetimes.com/document.asp?doc_id=1330971](https://www.eetimes.com/document.asp?doc_id=1330971)

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cromwellian
3nm isn't even on the international semiconductor roadmap (that stops at 5nm,
and 4nm half-node) How can they build a fab for a process node that isn't even
designed yet? Has anyone even produced prototype chips at this node yet?

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valarauca1
The International Semiconductor Roadmap was properly tossed out the window at
the 28nm node. In the past year they're more or less retconned the industry's
current node system _into_ the road map.

Modern pitch measurement is more a marketing term then a _real_ measurement of
engineering precision. A smaller/newer value is roughly equal to 1/2 power
consumption, it no longer implies 2x density.

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lquist
So am I correct in understanding that Moore's Law marches on? If we see 5nm in
2020 and TSMC is seeing 3nm in production in 2022, this is on track, correct?

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deepnotderp
PSA: 3nm doesn't actually mean ANYTHING except that it's smaller than 5nm (and
larger) nodes from the SAME FOUNDRY. If you want a general benchmark now, TSMC
"7nm" ~= Intel "10nm". Note that this isn't because Intel is pious and
searching for the true node name or anything, their nodes used to be less
dense than the industry standard (back above ~45nn) but just turned out denser
now.

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nmz787
Why don't these numbers ever list the width AND height AND length... I'd
really like to know how many atoms each transistor was composed of.

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auvi
And who is making the lithography equipment for TSMC for its "3nm" Fab? I
guess ASML?

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ksec
This is in Intel's terms 5nm.

We know real Intel's 10nm / TSMC 7nm has finished and is matter of yielding.

We know TSMC Intel 7nm / TSMC 5nm is pretty close to complete. This is coming
out to market in roughly 2020.

We know 3nm is coming in 2022 / 2023.

But what comes after 3nm?

Will we need some material science breakthrough? Process and Material that can
run at 10Ghz with the same power usage.

More transistor hasn't given us more performance. IPC, Core Count, Clockspeed,
Special Instruction Set (Its funny how we swing from RISC to CSIC again ), and
larger cache. It seems we have reached a plateau where we cant have more
performance from CPU Hardware. GPU is different since it scaled very nicely
with transistor count, and is more limited by bandwidth.

And fast, simple, high performance, easy to programmed for Programming
languages + framework hasn't really come along.

But cost for Fabs, Wafer and Designing is rising.

Or have we reached a stage, performance no longer matter for majority of
people?

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jlebrech
we're merely hitting 1.2ghz mean use and 4ghz peak usage. 10ghz is very fast.

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Animats
3nm. Wow. Synchrotron, or laser tin vaporization soft X-ray source?

