
Intel’s Manufacturing Roadmap from 2019 to 2029 - hkmaxpro
https://www.anandtech.com/show/15217/intels-manufacturing-roadmap-from-2019-to-2029
======
huffmsa
5 and 10 year plans are _always_ over optimistic projections by people who
can't deliver in the present to reassure investors faith.

They might ship 1.4nm, but it has a good chance of having Soviet tractor
quality.

~~~
perceptronas
I usually hear the opposite: people tend to underestimate what they can do in
10 years and overestimate what they can do in 1-3

~~~
eyegor
You might want to check out intels historical roadmaps. They've been missing
their own marks since about 2015 iirc.

~~~
jl6
Sounds broadly consistent with the parent poster’s point?

~~~
SimbaOnSteroids
Not if they meant they missed their 2005 roadmap for 2015.

~~~
onlyrealcuzzo
Someone please correct me if I'm wrong.

Intel unveiled their infamous "Tick-Tock Model" around 2007 [1]. It went
according to plan for all of four years, and then it COMPLETELY fell apart. If
anything, I'm willing to bet they KNEW they could hit the first few
iterations. I'm guessing for hardware, you've probably got a really good idea
if you're going to be able to even manufacture something in two years, let
alone mass-distribute, produce, and sell it at the price point you want. I'm
also pretty certain they KNEW they wouldn't hit the rest of the roadmap.

Honestly, I think it was purposefully misleading investors. I heard from
dozens of engineers at the company around 2008 that there was NO WAY they
would have 10nm chips around 2012 -- what the roadmap was more or less
promising. And surprise, we didn't get them until 2018. Now they're promising
1.5nm in a similar time frame. I'm skeptical.

[1]
[https://en.wikipedia.org/wiki/Tick%E2%80%93tock_model](https://en.wikipedia.org/wiki/Tick%E2%80%93tock_model)

~~~
kllrnohj
> I heard from dozens of engineers at the company around 2008 that there was
> NO WAY they would have 10nm chips around 2012 -- what the roadmap was more
> or less promising.

Where did they promise 10nm in 2012? This presentation from 2011 shows 10nm in
2017: [https://www.nextbigfuture.com/2011/06/intel-roadmap-from-
jun...](https://www.nextbigfuture.com/2011/06/intel-roadmap-from-
june-2011-with-7nm.html) and in 2011 tick-tock was still going strong.

I think you messed up your math. Tick/tock was a process shrink every 2-3
years. Using the more aggressive 2 year cadence:

    
    
        45 nm – 2007
        32 nm – 2009
        22 nm – 2011
        14 nm – 2013
        10 nm – 2015
    

Using a more conservative 3 year cadence:

    
    
        45 nm – 2007
        32 nm – 2010
        22 nm – 2013
        14 nm – 2016
        10 nm – 2019
    

And if we look at what actually happened:

    
    
        65 nm – 2005
        45 nm – 2007
        32 nm – 2010
        22 nm – 2012
        14 nm – 2014
        10 nm – 2018/2019

(Cannon Lake-U 10nm technically shipped in 2018, but I don't think anyone
really considers it volume-enough to count?)

They pretty much nailed tick/tock flawlessly up until 10nm, 10 years out from
when tick/tock was first announced. Expecting perfect 10 year predictions is
some insane expectations for any company/person. There's no way in hell
tick/tock's 2007 unveil could possibly be considered "misleading investors."

~~~
ksec
>Where did they promise 10nm in 2012? This presentation from 2011 shows 10nm
in 2017:

Your link shows 7nm in 2017, 10nm was for 2015.

>Tick/tock was a process shrink every 2-3 years. Using the more aggressive 2
year cadence:

You are confusing "Tick Tock" with "Process, Architecture, Optimization". Tick
Tock is strictly 2 years cadence.

So yes 10nm missed by a large margin.

> 10 nm – 2018/2019

Intel has been making 10nm chip irrespective of yield, the current batch were
months of stock piling chip before the rush to roll out in Xmas. In reality
they barely got it out of the gate in 2019. And if you count Cannon-Lake as
2018, you might as well count TSMC 5nm in 2019.

>There's no way in hell tick/tock's 2007 unveil could possibly be considered
"misleading investors."

There were not misleading in 2007, the executed their plan flawlessly, Intel
had decent people back then. Pat Gelsinger left in 2009. It was still doing
great up to 2012, Otellini retired, BK became CEO in 2013, still promising
Tick Tock. That is the point where misleading investor began.

And I forgot to mention during _All_ investor meetings Intel continue to
reiterate 10nm is on track all the way until BK was gone. If that is not
"misleading investors" I am not sure what is.

------
soygul
I know that past performance does not indicate future results but looking at
their 2013-2016 roadmap [1] which promises 10nm at Q1 2016 (which never
happened!), I strongly doubt their future roadmap will hold.

[1] [https://wccftech.com/intel-processor-roadmap-leaked-10nm-
can...](https://wccftech.com/intel-processor-roadmap-leaked-10nm-cannonlake-
skylakee-arrives-q3-2016-skylake-muy-chips-q4-2015/)

~~~
bryanlarsen
And for the previous 40 years Intel was always about 1 year ahead of their
competitors. I would never bet against Intel, that's been a losing game for
far too long.

~~~
hrktb
AMD was already poised to eat their lunch last time, Intel had to go to
illegal lengths to keep their commercial lead.

I'd expect AMD to have learned the lesson and get away with their lead this
time.

~~~
seanmcdirmid
Irrelevant. AMD doesn’t own its own fabs anymore, and I think they rely on the
expertise for whoever happens to be fanning their chips, allowing them to
simply choose the fab with the best process while they focus on architecture.

~~~
undersuit
Maybe that's the lesson AMD learned?

~~~
seanmcdirmid
No. It’s just the reality of the situation. Perhaps intel would do better to
separate their fab and architecture divisions, or maybe they are already
sufficiently separated internally anyways.

------
nightcracker
Reality: 14nm,14nm,14nm,14nm,14nm.

~~~
huffmsa
With a few one off demo 10nm releases here and there.

~~~
AgloeDreams
Meanwhile TSMC is out there shipping 10nm equivalent for a year now, including
in Threadripper and Apple's AX chips. Wonder if AMD will ship a next gen TSMC
fabbed product prior to 10nm Shipping en Masse.

~~~
boatswain
TSMC's 5 nm node is on track for high volume in Q2 2020[1]. They also have the
announced 6 nm which they expect most clients to transition to[2]. If Intel's
10 nm is equivalent to TSMC's 7 nm then their 6 nm should be noticeably better
even before 5 nm starts shipping.

[1] [https://www.anandtech.com/show/15016/tsmc-5nm-on-track-
for-q...](https://www.anandtech.com/show/15016/tsmc-5nm-on-track-
for-q2-2020-hvm-will-ramp-faster-than-7nm)

[2] [https://www.anandtech.com/show/14290/tsmc-most-7nm-
clients-w...](https://www.anandtech.com/show/14290/tsmc-most-7nm-clients-will-
transit-to-6nm)

------
eyegor
So if Intel actually stayed on track for this roadmap, they're saying "we only
have 10 years left to advance our fabs". Unless 1.4nm is actually meaningless,
they'd be edging up to electron tunneling issues with a contacted gate pitch
of ~10 atoms across.

I'm being optimistic with this guesswork. Intel's historical naming is that
cpp = 3-5x node name [1]. Silicon lattice spacing is ~0.54nm.

[1]
[https://en.wikichip.org/wiki/intel/process](https://en.wikichip.org/wiki/intel/process)

~~~
gsnedders
> "we only have 10 years left to advance our fabs"

Well, only 10 years left to advance with silicon wafers; once improvement
truly becomes impossible there presumably we'll see even more resources go
into trying to find practical replacements.

------
wadkar
I really liked the last quote:

> It’s worth also pointing out, based on the title of this slide, that Intel
> still believes in Moore’s Law.

> Just don’t ask how much it’ll cost.

I once got an opportunity to ask something similar to an Apple executive
during a presentation on their hardware capabilities (it was a university
event).

He laughed and answered another part of my question.

~~~
Shorel
Moore's Law is about cost per transistor, so they have it wrong somewhere.

~~~
boatswain
Moore's law is about density of transistors.

~~~
lorenzhs
That's not quite correct. It's about the number of transistors per integrated
circuit that minimises per-transistor cost. From the actual 1965 paper:

> _" The complexity for minimum component costs has increased at a rate of
> roughly a factor of two per year (see graph on next page). Certainly over
> the short term this rate can be expected to continue, if not to increase.
> Over the longer term, the rate of increase is a bit more uncertain, although
> there is no reason to believe it will not remain nearly constant for at
> least 10 years. That means by 1975, the number of components per integrated
> circuit for minimum cost will be 65,000."_

There's also the 1975 speech where he revised it down from a yearly doubling
to once every two years.

------
baybal2
A poorly held secret in the semi industry is that transistors have stopped
scaling at around 30nm - the practical limit of 193nm litho.

What has been scaling was the amount of free space in between them, metal
layers, design rules, cell designs and such.

Before transistor scaling stalled, any process node shrink was an automatic
performance gain without any side effects, but not so much after. Some designs
may well be seeing net losses with process shrinks these days.

From 10nm on, higher density is actually hurting your performance, not adding
it. For a process technologist, you have now to work on both performance, and
density in parallel, and not solely on the last one thinking that gains in it
will automatically translate into gains in performance.

So its a tricky business now to both squeeze more transistors into a design,
and have a net gain from it.

------
andy_ppp
Just as an interesting aside does anyone have a list of weird engineering
hacks used in these processes to get smaller and smaller transistor densities?
There must be some very clever stuff to jam them in there and still be able to
etch the lines.

~~~
yaantc
It's a vast and complex topic. I once stumbled on the following presentation
from ARM:
[https://community.arm.com/developer/research/b/articles/post...](https://community.arm.com/developer/research/b/articles/posts/the-
ics-of-2030)

The first part covers EUV, which is key to advanced nodes. Then it moves on to
more futuristic and tentative techniques. But the EUV part is a nice
introduction for non specialist, with pointers to dig if one is interested.

~~~
Dylan16807
EUV is an amazing nightmare, but the etching part of the process is pretty
straightforward. The difficulty is in finding materials that don't absorb it
all and/or break constantly. In my mind, the really interesting tricks and
hacks are all the ways they've managed to take 193nm light and etch things
that are _so much smaller_ than the wavelength.

------
PedroBatista
You can always count on Intel's marketing team for top notch slide
presentations.

However, Intel is closer to 22nm than 7nm let alone anything smaller than
that. ( I'm talking about consistent product lines that anyone can buy at a
store ), not some Houdini show.

On the commercial side they have a huge footing and large tentacles so they
don't need to worry too much about time-frames, let's hope they also don't
worry too little..

------
kuu
How is it possible to have 1.4nm transistors?

~~~
fungicide
Because "nm" doesn't mean nanometer anymore. Not in the context of CPUs
anyway. Some time back, around the 34nm era, CPU components stopped getting
materialy smaller.

Transistor count plateaued. Moore's law died.

To avoid upseting and confusing consumers with this new reality, chip makers
agreed to stop delineating their chips by the size of their components, and to
instead group them in to generations by the time that they where made.

Helpfully, in another move to avoid confusion, the chip makers devised a new
naming convention, where each new generation uses "nm" naming as if Moore's
law continued. Say for example in 2004 you had chips with a 34nm NAND, and
your next gen chips in 2006 are 32nm, then all you do is calculate what the
smallest nm would have been if chip density doubled, and you use that size for
marketing this generation. So you advertise 17nm instead of 32nm.

Using this new naming scheme also makes it super easy to get to 1.4nm and
beyond. In fact, because it's decoupled from anything physical, you can even
get to sub-plank scale, which would be impossible on the old scheme.

Edit: Some comments mention that transistor count and performance are still
increasing. While that is technically true, I did the sums, the Intel P4
3.4Ghz came out 2004, if Moore's law continued, we would have 3482Ghz or 3.48
TERAHERTZ by now.

~~~
Erlich_Bachman
Do you have any sources for this? Where could one learn about this more
carefully? I mean isn't this a major marketing fraud?

~~~
fungicide
Plenty of info here. Enjoy
[https://en.wikichip.org/wiki/technology_node](https://en.wikichip.org/wiki/technology_node)

"Recent technology nodes such as 22 nm, 16 nm, 14 nm, and 10 nm refer purely
to a specific generation of chips made in a particular technology. It does not
correspond to any gate length or half pitch. Nevertheless, the name convention
has stuck and it's what the leading foundries call their nodes"

..."At the 45 nm process, Intel reached a gate length of 25 nm on a
traditional planar transistor. At that node the gate length scaling
effectively stalled; any further scaling to the gate length would produce less
desirable results. Following the 32 nm process node, while other aspects of
the transistor shrunk, the gate length was actually increased"

~~~
kllrnohj
That's some pretty bullshit quote-mining there. You stopped right before the
important part:

"With the introduction of FinFET by Intel in their 22 nm process, the
transistor density continued to increase all while the gate length remained
more or less a constant."

I'll repeat it for you see you seem to keep missing it: _transistor density
continued to increase_

------
nootropicat
For comparison, Intel's roadmap from IDF2013:
[https://files.catbox.moe/psgnbp.jpg](https://files.catbox.moe/psgnbp.jpg)

------
diegoperini
What kind material science improvement would make non-marketing, real ~10nm
scales a reality? I literally have no idea how RnD works in this field. Is it
trial and error? How do these scientists come up with ideas that increases the
transistor density? Do our current gen CPUs have 2d or 3d curcuit layout? How
one can learn about these stuff without working in the field?

~~~
kristofferR
This is a great watch about how EUV works:

[https://www.youtube.com/watch?v=f0gMdGrVteI](https://www.youtube.com/watch?v=f0gMdGrVteI)

~~~
diegoperini
Watched it, thanks a lot!

------
baybal2
Adding to my previous post, a lot of people don't understand where 10nm EUV
litho stands in the grand plan of thins.

"If EUV doesn't make a more performant chip, what it does?" EUV is there to
alleviate _extreme_ process costs associated with multiple patterning, and
process cycle time.

Even if EUV tool does 1 exposure a little bit slower than quadruple
patterning, it can do 4 patterning steps in one — a very huge thing in process
technology.

You have then lessen the amount of thermal processes performed on the device.
You may have more defects, but on overall higher quality, higher performance
devices in the end.

~~~
vardump
> Even if EUV tool does 1 exposure a little bit slower than quadruple
> patterning, it can do 4 patterning steps in one — a very huge thing in
> process technology.

Would that also remove some patterning constraints? Give the pattern "more
freedom".

~~~
baybal2
Yes, this is another big thing about it

------
josteink
> Intel expects to be on 2 year cadence with its manufacturing process node
> technology, starting with 10nm in 2019 and moving to 7nm EUV in 2021

Not to say it could _never_ happen, but given how many years Intel has spent
on 10nm with it always been 'next year' tech year after year, 7nm in 2021
seems overly optimistic for me.

I guess time will tell if they got it right this time.

~~~
thunderbird120
It seems reasonably likely that they will succeed. Intel's 10nm and its 7nm
are very different beasts with 7nm arguably being a lot simpler thanks to EUV
and a 2x density transistor improvement goal (vs 2.7x for 10nm). The lack of
EUV and very high density goals for 10nm meant they had to do a lot of multi-
patterning which ended up screwing their yields. That plus the uncharted
waters of using cobalt interconnects rather than copper meant it was basically
Intel getting overconfident and being too ambitious for their own good.

~~~
Symmetry
There were also a whole laundry list of other technologies Intel was trying to
put into 10nm. Contact over active gate, COAG, was heavily used in the GPU
portion of the die and its failure is why none of the very few 10nm parts
released in 2018 had any GPU at all.

------
HelloNurse
The "backporting" doctrine clearly implies total lack of faith in process
roadmaps, to the point of compromising processor designs and increasing cost
and time to market to avoid committing to a millstone around the neck.

------
randyrand
I've read that as chips get smaller, their working life gets shorter. Anyone
have more info?

~~~
opwieurposiu
I think you are talking about Electromigration

[https://en.wikipedia.org/wiki/Electromigration](https://en.wikipedia.org/wiki/Electromigration)

------
dmos62
A beginner question: what's the motivation behind reducing chip size? Less
power consumption?

~~~
marcosdumay
Smaller transistors bring everything. They have lower resistance and
capacitance resisting a switch, you can build more of them at the same time
(so, approximately by the same cost), a signal takes less time to pass through
them (and to get from one to another), and they have a larger surface/volume
ratio for cooling down.

That said, transistors actually stopped shrinking a while ago. They are
getting packaged nearer to each other, they have changed from horizontal to
vertical, and they are changing the width/length ratio, but they are not
really shrinking.

------
metalforever
Sounds like bullshit.

------
HocusLocus
Measure with micrometer. Mark with chalk. Cut with an axe.

------
RosanaAnaDana
So, long AMD?

Edit: oof with the down votes. Jesus people; comma added for clarity.

~~~
fooker
Nice one

------
bullen
All change requires energy, and we're going to have less energy, so the speed
of change inevitably has to go down.

Because the only energy added to the planet comes from the sun and the only
viable option to collect that energy are trees and plants.

(I'm going to post this comment on every naive technology optimist post, you
can downvote me all you want, I have to do this to be able to sleep at night,
fake karma is not more valuable than real karma)

------
lachlan-sneff
What perplexes me is that neither Intel, AMD, IBM, or any other company, as
far as I can tell, is pursuing the bootstrapping path of self-assembling
nanotech. Once someone does it, every other company is going to be left
several orders of magnitude in the dust, so it surprises me that no one is
going for it.

~~~
ttsda
Yeah, I wonder why all these companies are investing billions on chip
fabrication if they can just tell the tiny robots to build them

~~~
lachlan-sneff
Well, you can laugh, but it's legitimate stuff. Right now, all we have is
self-assembling dna structures, but there's a bootstrappable path towards
"tiny robots".

~~~
ttsda
We have self-assembling dna structures, which we don't even fully understand
and which are the result of millions of years of evolution. The steps are
being made towards such tiny robots, but it's preposterous to mention them as
a viable alternative to the current chip fab strategy.

