
One Instruction Set Computer - lelf
https://en.wikipedia.org/wiki/One_instruction_set_computer
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legulere
So like x86 mov?

[https://github.com/xoreaxeaxeax/movfuscator](https://github.com/xoreaxeaxeax/movfuscator)

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lloeki
Came in to mention that, but the crazy stuff I was thinking about is
surprisingly not mentioned in the main readme. Behold:

[https://github.com/xoreaxeaxeax/movfuscator/blob/master/vali...](https://github.com/xoreaxeaxeax/movfuscator/blob/master/validation/doom/README.md)

Yes, Doom running with just MOV.

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teddyh
“Running” might not be the best word for it: “ _The mov-only DOOM renders
approximately one frame every 7 hours_ ” I.e. about 0.00004 FPS.

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jzwinck
Transport Triggered Architecture seems not only isomorphic but essentially
equivalent to a conventional architecture if you notice it is effectively just
relocating/packing the opcode bits into the operands. This seems to be an
implementation detail of the hardware (which bits does it gather opcodes from)
and not an essential difference in the ISA. Am I missing something?

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guidoism
If you had a writable control store then yes. But most processors these days
don’t expose that API.

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dang
A thread from 2015:
[https://news.ycombinator.com/item?id=9388137](https://news.ycombinator.com/item?id=9388137)

2011:
[https://news.ycombinator.com/item?id=3046980](https://news.ycombinator.com/item?id=3046980)

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mysterydip
Semi-related, I just learned about this 1-bit microprocessor the other day:
[https://en.m.wikipedia.org/wiki/Motorola_MC14500B](https://en.m.wikipedia.org/wiki/Motorola_MC14500B)

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qubex
Daniel Hillis’ famed Connection Machine architecture (until the radically
revised CM-5) featured hypercube-geometry “one-bit processors” which were
really “definable logic gates”.

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zzo38computer
This is good, although I study esoteric programming so have known a few of
these things.

I have also once designed a schematic for a transport triggered architecture
without knowing that it was called that; I just had the same idea. (But, many
people will have similar ideas, and not always know what it is called.)

TOGA computer is like a presettable binary counter, NOT gate, memory, some
logic for timing (so that it does not interfere with itself), and not much
else.

But what is not mentioned is Muxcomp, which is something I am much more
interested in, and is also with only one instruction. (Although, I thought of
using it as part of a user-programmable VLIW microcode.)

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rambojazz
Every example under "Instruction types" looks like a combination of 2 (or
more) instructions. "Do this AND do that".

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int_19h
Whether something does one or several things largely depends on your
perspective. You might think of ADD as a single instruction, but it fiddles
with a lot of bits...

This is "one instruction" in a sense of having only a single opcode.

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cellularmitosis
I’ve just recently started looking into implementing a minimal ALU, and I’ve
been having trouble finding good resources to answer the question “other than
a one-instruction computer, what is the smallest number of instructions needed
in a Turing-complete RISC?”

I’m guessing it would be NAND, ADD, increment, and some sort of branch?

NAND covers all of the bitwise ops. If you have ADD, NOT and increment, you
can get SUB. If you have ADD and SUB, you can get MUL and DIV.

Am I missing anything?

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f00zz
This (educational) ISA has just NAND and ADD:
[https://user.eng.umd.edu/~blj/RiSC/RiSC-
isa.pdf](https://user.eng.umd.edu/~blj/RiSC/RiSC-isa.pdf)

~~~
cellularmitosis
Exactly what I was looking for, thanks so much!

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nomorerul
Is this the era of microcomputers like we have microservices?

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jes5199
that word already means something, and it describes probably every computer
you’ve used in your life. so... yes? but the era of microcomputers started in
1974

