
The vintage 74181 ALU chip: how it works and why it’s so strange (2017) - bcaa7f3a8bbc
http://www.righto.com/2017/03/inside-vintage-74181-alu-chip-how-it.html
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CalChris
I suppose if you used a minicomputer in the 70s or 80s then you used this or
something like this chip. This is another site giving some more history and
data sheets of the 74181 [1].

The carry-lookahead adder used in the 74181 was patented by IBM in 1957 [2].

Carry-lookahead is O(log n) in time and 0(n log n) in space. Carry-skip and
carry-save are O(sqrt n) in time and O(n) in space [3].

I couldn't figure out what Intel or ARM or even RISC-V use. But according to
this [4], full-lookahead for 32b is 5 gate latency while only being 4 times
larger than ripple.

[1]
[https://apollo181.wixsite.com/apollo181/about](https://apollo181.wixsite.com/apollo181/about)

[2]
[https://patents.google.com/patent/US2966305](https://patents.google.com/patent/US2966305)

[3]
[https://booksite.elsevier.com/9780123838728/references/appen...](https://booksite.elsevier.com/9780123838728/references/appendix_j.pdf)

[4]
[http://www.cs.cornell.edu/courses/cs3410/2010sp/lecture/topi...](http://www.cs.cornell.edu/courses/cs3410/2010sp/lecture/topic08-performance-i.pdf)

Does anyone know what Intel's Tiger Lake or ARM's A77 or RISC-V BOOM (and I
looked at the Chisel source) use?

~~~
analognoise
You're confusing ISA with an implementation detail.

~~~
CalChris
No, I _really_ am not interested in ISAs at all. I'm interested in how various
current microarchitectures (Tiger Lake, A77 or BOOM) implement add at the gate
level.

~~~
rjsw
I don't think that RISC-V is specified at the gate level. You don't want that
if you are targeting FPGAs as the tools can't look at a tree of logical
expressions in Verilog or VHDL and decide "oh you are designing an ALU" and
map it onto the ALUs in a collection of slices.

~~~
CalChris
RISC-V is an ISA. However, Berkeley BOOM is a microarchitecture, an out-of-
order superscalar RISC-V core. It is synthesizable and parameterizable. _While
BOOM is primarily ASIC optimized, it is also usable on FPGAs._

[https://boom-core.org/](https://boom-core.org/)

But what I'm really interested in is which adder modern microarchitectures
use.

~~~
tntn
BOOM uses the rocketchip ALU, which uses the Chisel `+`, which probably
compiles down to the verilog `+`, which probably gets synthesized to the
appropriate width adder in the standard cell library of the vendor (e.g. TSMC
or Xilinx). So for synthesized microarchitectures, it isn't determined in the
RTL.

