
Intel forges ahead to 10nm, will move away from silicon at 7nm - 0xb0
http://arstechnica.com/gadgets/2015/02/intel-forges-ahead-to-10nm-will-move-away-from-silicon-at-7nm/
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ChuckMcM
Makes me sad I'm not going to ISSSC.

There is an interesting debate about feature size though. Devices on silicon
for a long long time were essentially 2D, patterns on the top surface of
Silicon. "Feature size" in this environment directly translated into area
which directly translated into the die size.

As features got smaller you started getting 'trench fets' and other tricks to
increase the effective size of the gates so that leakage current wasn't
insane. So at what point then do the circuit elements become fully vertical,
which is to say that viewed from the 'top' the transistor is 10 nm on a side
but vertically its 22 nm 'tall' ?

And other tricks where the silicon layers are separately tested and 'thinned'
and then packaged as a sandwich for final testing with ion implanters creating
the vias between the connecting layers.

Really interesting work in that sort of stuff going on.

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bsdpython
Moore first made his claim in 1965. Assuming we have at least 5 more years
wringing out efficiencies with the move to 10nm that's 55 years of continuous
innovation. It's mind boggling. Maybe there will be a gap until the next major
breakthrough but an entirely new process will come along eventually.

~~~
higherpurpose
My guess is we'll probably need something like graphene. Gallium Arsenide
seems more like a 10 year stop-gap than a 50 year revolution. The problem is
we can't get any "smaller", because we enter the quantum world and that's
something entirely different. However, with graphene we can keep the
transistors the same, but raise the clock speeds each generation, perhaps up
to 1 TeraHerz or more, with a Moore's Law-like rate of improvement in
performance.

~~~
IanCal
There's still a big problem with just upping the speed. If we have a chip
running at 1THz then in each clock cycle light can only travel 3mm.

Moving to more complex 3d chips could help improve performance, but there are
limits to the number of dimensions we have too.

~~~
eloff
Yeah, I don't think 1 THz is achievable, but we can likely do substantially
better than 4 Ghz, even when we can't go smaller. Then there are also gains to
be made from building bigger, building in 3 dimensions, decreasing waste heat,
etc. I suspect that innovation with chips will get bumpier, but likely overall
maintain the pace of innovation for a couple decades more - which is all we
need to get into really interesting territory re AI and other things.

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manigandham
If anyone is interested in the manufacturing of these chips, this is an old
but fascinating video:
[https://www.youtube.com/watch?v=NGFhc8R_uO4](https://www.youtube.com/watch?v=NGFhc8R_uO4)

~~~
rwmj
And here's a video from the 1970s, probably the first and last time Intel let
anyone inside one of their fabs with a camera:

[https://www.youtube.com/watch?v=HW5Fvk8FNOQ](https://www.youtube.com/watch?v=HW5Fvk8FNOQ)

~~~
TazeTSchnitzel
26 minutes in, and this may be the best documentary on the then-future use of
computers I've seen.

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wcoenen
For comparison, bond lengths are on the order of 0.2 nm.

[https://en.wikipedia.org/wiki/Bond_length](https://en.wikipedia.org/wiki/Bond_length)

The lattice constant of unstrained silicon is 0.543 nm.

~~~
TheLoneWolfling
So ~18-19 atoms across, then?

~~~
toufka
I asked about this yesterday [1], and I found this article[2]. I can't speak
to the validity, but it appears that the 'distances' used in these marketing
concepts are not the same distances that are used to measure things. I'm still
curious what the actual controllable resolution of the feature sizes are in
the '7nm process'. I get the feeling that it's more like 30nm, but the
effective feature density is greater than yesterday because there is more
control vertically, and diagonally, etc. and so they need a smaller number
than yesterday. But still just ~30nm (not actually 7nm).

[1]
[https://news.ycombinator.com/item?id=9092506](https://news.ycombinator.com/item?id=9092506)

[2] [http://spectrum.ieee.org/semiconductors/devices/the-
status-o...](http://spectrum.ieee.org/semiconductors/devices/the-status-of-
moores-law-its-complicated)

~~~
nhaehnle
When Intel say they have 52nm wire pitch, this means that they produce wires
that are 26nm wide, with 26nm distance between wires. Producing wires that are
thinner, or that are closer together, is unreliable.

That said, they are probably able to _position_ those wires at a higher
precision. Without being involved in the manufacturing myself, I deduce this
mainly from looking at optical proximity correction[1], for example, it's
clear that the final masks used for production have more detail. Another
indication is the fact that different masks seem to be aligned to basically
nm-level precision (otherwise, the different parts of transistors and the
vertical interconnects (vias) between wiring planes would not match up
properly). The photographs one sees of the final product also indicate this.
This means that the _location_ of wires could theoretically be controlled very
precisely, but for a mixture of wavelength and other (chemical? surface
tension?) reasons, the _size_ of the wires cannot be made smaller reliably.

I'd be curious to know how precise this alignment really is, and I've never
seen numbers for it, but it must be incredibly precise. Given that a large
part of it can be done optically, this is not even that surprising, compared
to some of the other magic that's going on here.

[1]
[http://en.wikipedia.org/wiki/Optical_proximity_correction](http://en.wikipedia.org/wiki/Optical_proximity_correction)

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dcsommer
As someone nearly irrationally annoyed by the collective inefficiency of all
the Javascript being run in the world, I kind of wish the computational "free
lunch" ends sooner than later so the frontend world has to move towards the
zero-cost abstractions and techniques being adopted server side. Too bad these
hardware engineers are really good at their jobs!

~~~
ajuc
Last I've checked java and .net were the most popular server-side languages,
and they are all about costly abstractions. Dependency injection, reflection,
AbstractFactoryBuilderManagerBean etc.

In fact I've yet to see java server-side stacktrace that's less than 100 lines
long. Usually it's more like 1000 lines, with a few RMIs inside. On the other
hand, the js stacktraces I've seen (mostly hobby projects, so I may be biased)
are usually less than 50 lines, often just 10 or so. Not good, but much
better.

~~~
iopq
Yet Java servers often come out on top in benchmarks, even beating C
implementations.

~~~
tormeh
The JVM is an insane thing, and with clever enough programmers a lot can be
done on top of that.

Were those Java servers written in standard Java, though? Because it's
possible to write pretty low-level code in java if you're willing to
compromise on standards compliance. Non-GC'ed, direct memory access is
possible, I think.

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stcredzero
Gallium Arsenide? If that's true, then it will be like a sign of the
apocalypse. The old saw has been: "Gallium Arsenide: Technology of the Future!
Always was. Always will be!"

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wyager
Do they know what they're going to move to?

~~~
TaylorAlexander
"More interesting than 10nm, though, is the news that Intel is looking to move
away from silicon FinFETs for its 7nm process. While Intel didn't provide any
specifics, we strongly suspect that we're looking at the arrival of
transistors based on III-V semiconductors. III-V semiconductors have higher
electron mobility than silicon, which means that they can be fashioned into
smaller and faster (as in higher switching speed) transistors."

~~~
sliverstorm
To those unfamiliar with "III-V": Think GaAs (Gallium Arsenide) and friends.

 _gallium arsenide (GaAs) has six times higher electron mobility than silicon,
which allows faster operation... Conversely, silicon is robust, cheap, and
easy to process, whereas GaAs is brittle and expensive, and insulation layers
can not be created by just growing an oxide layer; GaAs is therefore used only
where silicon is not sufficient._

    
    
      -- Wikipedia

~~~
eclipxe
Gallium Arsenide Valley doesn't have quite the same ring to it does it...

~~~
sliverstorm
Better than "Gaas Valley", at least.

~~~
1123581321
How abou Gall Arse Valley?

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sireat
I keep reading how 22nm, 20nm, 16nm, 14nm and so on are not true measurements
anymore but mostly marketing speak. This is true of all fab companies.

That is the move from 22nm to 14nm did not give you double the transistor
count from the same area die.

So has anyone done a comparison of transistor count on the same size die over
the years depending on the process?

~~~
marcosdumay
Feture size never had a completely linear relation to transistor density.
Recently that non-linearity is just becomming worse.

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spunwasi
Witchcraft!

