
ARM Launches DynamIQ: big.Little to Eight Cores Per Cluster - randta
http://www.anandtech.com/show/11213/arm-launches-dynamiq-biglittle-to-eight-cores-per-cluster
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DiabloD3
I wonder when Intel is going to attempt their own version of big.little.

I think there is a market for laptop and thin-desktop x86 CPUs that are
asymmetric 2 core/4 thread big + 2 core/2 thread little, and they already have
a small version of their modern cores[1], so a 2 full Skylake + 2 little
Goldmont cores (or 4+4) could be extremely interesting, especially on a future
115x socket.

    
    
      1.
      * Silvermont (Bay Trail/Avoton/Rangeley) == "atomfied" Haswell
      * Airmont (Braswell/Cherry Trail) == "atomfied" Broadwell
      * Goldmont (Apollo Lake/Denverton) == "atomfied" Skylake
      * ???mont (Gemini Lake) == "atomfied" Kaby/Coffee Lake.

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Symmetry
The problem with Intel doing this is that, for marketing reasons, they tend to
enable different sets of instructions on different cores and an OS would have
a really hard time scheduling threads when some the Skylake cores can execute
AVX instructions but the Goldmont cores can't. Normally the scheduler wants to
assume that it can just move a thread from one core to another but if the
thread started off on the Skylake and was taking an AVX-enabled code path that
would cause problems.

Not that the idea isn't appealing or even infeasible. It just runs afoul of
Intel's marketing.

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microcolonel
This is one of those interesting cases where RISC-V could eat their (and maybe
ARM's) lunch on implementations like this. The wide vector instructions (i.e.
not the packed SIMD, but the -V extension) are width-independent, so you could
just make the vector machine narrower on the little core, and switch it to
low-frequency in-order.

~~~
pertymcpert
ARM did it first with SVE. The RISC-V vector extension is just a draft while I
believe SVE silicon is being developed now for exascale HPC.

~~~
microcolonel
Cray did it first, that's why there's no patent dispute right now.

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pjmlp
A better source of information than Anandtech, including a reference to the
presentation slides.

[https://community.arm.com/processors/b/blog/posts/arm-
dynami...](https://community.arm.com/processors/b/blog/posts/arm-dynamiq-
expanding-the-possibilities-for-artificial-intelligence)

[https://community.arm.com/processors/b/blog/posts/arm-
dynami...](https://community.arm.com/processors/b/blog/posts/arm-dynamiq-
technology-for-the-next-era-of-compute)

~~~
Narishma
I'm not sure about 'better'. Those links are full of buzzwords and marketing
speak.

~~~
pjmlp
Anandtech's article is basically copy-paste from ARM blog, without the links
for the relevant information, hence why the ARM site is better.

~~~
borandi
No copy-paste there. Ultimately there's not that much information, so the
analysis is going to read similar. But claiming it's basically a copy-paste is
a bit much.

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patrickg_zill
So to tie this in to an application of these chips:

Smartphone that has this - when idle (no phone calls, user is either not using
or just looking at static screen such as e-reader or non-interactive web page)
only low power chips run, doing the bare minimum housekeeping tasks, updating
the screen, etc.

When something happens, the low-power chips wake up the more powerful chips
and hand off the task to them.

Is that the basic idea?

Intel's POV seems to be to have 1 powerful CPU with different power states,
while ARM is explicitly breaking up the power levels with different CPUs on
the same SoC.

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Symmetry
I'm very curious how they work the cache hierarchies of these hybrid clusters.
You really want to be tuning the latency and throughput of the cache to the
consumers attached to it and that wouldn't be straightforward in this case.

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robert_foss
Will the proper OS support take 3 years to land like it took for bigLittle?

Probably.

Will individual manufacturers using the IP stumble and fall like Samsung did
with their A15 bigLittle hardware implementation?

Presumably.

