
Intel Prototypes Low-Power Circuits - duck
http://www.technologyreview.com/computing/24843/
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terminus
What the article doesn't mention is how the errors are detected -- in a fool
proof fashion and cheaply. I can think of error detection schemes that might
be cheap to implement but are not foolproof. For instance for an integer
multiplication the parity might be cheap to calculate (and without redoing the
whole calculation.)

Thus, the error detection algorithm checks the actual parity with the
"correct" parity. That of course falls down for multi bit errors.

Researching the literature a bit:

A different approach (tradeoff precision for power) in GPUs: Energy-precision
tradeoffs in mobile Graphics Processing Units
(<http://iccd.et.tudelft.nl/2008/proceedings/060pool.pdf>). Another one
(probabilistic chips): <http://www.technologyreview.com/energy/20246/>.

Edit: Added more detail, formatting.

~~~
wmf
Razor works by latching a signal twice at different times and comparing the
two values; if they differ, the signal must have arrived at the primary latch
late which is an error. It specifically detects timing errors which are caused
by negative voltage margin, not other types such as soft errors caused by
cosmic rays.
[http://portal.acm.org/citation.cfm?id=956417.956571&coll...](http://portal.acm.org/citation.cfm?id=956417.956571&coll=ACM&dl=ACM&type=series&idx=SERIES366&part=series&WantType=Proceedings&title=MICRO&CFID=34085365&CFTOKEN=33998412)

I wouldn't be surprised if Intel's work is similar.

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redmage
One-page version here:
[http://www.technologyreview.com/printer_friendly_article.asp...](http://www.technologyreview.com/printer_friendly_article.aspx?id=24843&channel=specialsections&section=smarterit)

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proee
This is really innovative and I suspect it will force the rest of the industry
to adopt similar technologies.

