
Open-source chip RISC-V to take on closed x86, ARM CPUs - jumpkickhit
http://www.computerworld.com.au/article/618724/open-source-chip-mimics-linux-path-take-closed-x86-arm-cpus/
======
wyldfire
I thought that microprocessor production and design was fraught with risk of
infringing on other designers' patents (even for original ISAs). I can see
that industry heavyweights have arrived to support RISC-V, so hopefully that
comes with a team of professors/lawyers that could defend them. But, why now?
Why couldn't this have happened sooner? Didn't Sun try to create an open SPARC
processor design? What does RISC-V have that it didn't?

Is the intent for RISC-V to compete with modern high-end CPU designs, or do we
just want to have royalty-free microprocessors for our embedded devices?

You might be surprised (at least I was) to learn that peripherals like hard
drives and PCI-add-in cards usually have their own CPU executing their own
software. Those processors are often MIPS/ARM/etc based and the manufacturer
has to shell out to someone to be able to use that, even if they designed the
processor themselves. I can see how this particular market is ripe for
something like RISC-V. But does anyone expect RISC-V to really go head-to-head
with Xeon, Opteron, ThunderX, Centriq?

I sound incredulous because this seems surprising to me, but I have no
evidence to suggest whether it's as unlikely as I think. I've certainly seen
open source software designs far superior to closed source ones, so maybe
hardware design is no different?

~~~
indolering
The RISC-V team was very careful in establishing prior art for every design
decision. The patents on ISAs tend to be on their quirks, so keeping things
truly minimal helps avoid all of that complexity.

Like a lot of what Sun did, prior open chip designs weren't good enough.
Academics starting with a clean slate and a 20+ years of additional experience
gives RISC-V real advantages over MIPS and ARM.

The primary advantage is that RISC-V is truly RISC: they have a core ISA that
is frozen but extendable. This means that they can have application-specific
CPUs with intelligent fallback and full compatibility.

As to why now, well, they came up with RISC-V as a teaching ISA and started
getting emails from industry asking why it had changed from last semester. It
turns out that chip manufacturing has gotten cheap, with custom runs on 28nm
processes going for $30K.

You are correct in that their early target market are co-processors and other
niche components. Just getting a license from ARM is 10+ million dollars. But
the biggest cost in building your own ISA is investment in software and
tooling. RISC-V gives a common foundation for everyone to build on.

However, their intent is indeed to bring competition at every level. Their
licensing scheme was chosen specifically to allow big players to create IP and
keep the secret sauce to themselves, unlike SPARC V8 and OpenRISC.

Apple creates their own CPU and GPU designs, Google has custom hardware for
machine learning, and Samsung is about to overtake Intel as the world's
largest chip manufacturer. Why should they keep shelling out billions to ARM,
Intel, and AMD _just_ to use their ISA?

~~~
dom0
> Just getting a license from ARM is 10+ million dollars.

 _Which_ license? ARM offers several different models.

> Apple creates their own CPU and GPU designs, Google has custom hardware for
> machine learning, and Samsung is about to overtake Intel as the world's
> largest chip manufacturer. Why should they keep shelling out billions to
> ARM, Intel, and AMD just to use their ISA?

The Google hardware we know (TPU) for learning does not use ARM at all, so
they would obviously pay nothing there. BigCo's like Apple or Samsung are
probably ARM partners, so no per-design/unit fees.

Samsung _Electronics_ may become the biggest chip manufacturer soon, but much
like with smartphones that's only by turnover, not profit. But profit is what
ultimately finances your R&D.

An interesting titbit is that even Intel and ARM are, at least on paper,
partners.

~~~
raverbashing
Well, a 10 million dollar license is nothing of you factor the Fab costs

~~~
yaantc
Apples and oranges. The companies that design the chips and pays royalties for
IP are mostly fabless (with rare exceptions like Intel). The fabs are owned by
separate entities like TSMC, Samsung, SMIC that specialize in the production
itself. The fabs don't pay for CPU IP (they sometimes pay for some other basic
IP to be able to offer them as standard to their customers, but that doesn't
cover CPUs/GPUs).

About Samsung, they're on both sides but with separate legal entities.

The licensing cost IS usually significant to most fabless companies, who come
in many sizes. Most are not as big as Apple or NVidia. The fabless model comes
from the very high cost of a modern fab, it allows sharing a fab through many
fabless design houses.

ARM has the reputation of being cheap, because the typical IT/software people
compare them to Intel. And yes, compared to Intel most anyone is cheaper ;)
But in the embedded space, which is cost sensitive, ARM is not cheap. It's
like what IBM and Microsoft were in IT: nobody got fired for choosing them,
and they come with a very powerful ecosystem. Something they make client pay
for.

In front of ARM, one can find good technical competitors depending on the
target market (MIPS, Cortus, Andes, Beyond Semi...). But MIPS ecosystem is
smaller, and for the others waaaaay smaller.

RISC V has an opportunity in time to provide a good technology, backed by a
strong ecosystem, for lower costs. In the embedded space at least, this is a
very powerful combination.

~~~
makomk
The older OpenRISC had already found a few niches. For example, the management
core in some of Allwinner's newer ARM SoCs is apparently OpenRISC, presumably
because they didn't want to license another lower-end ARM core or something.
Similarly, some Samsung TVs apparently use it.

------
filereaper
Many people claim to want an open-source chip, but end up balking at its price
tag, this is exactly why Raptor Engineering's Talos failed. [1]

I've pretty much given up hope on a non-x86 based chip hitting our desktops,
the closest to reach will be ARM.

The economies of scale aren't there, I pretty much end up rolling my eyes at
each of these articles.

[1]
[https://www.raptorengineering.com/TALOS/prerelease.php](https://www.raptorengineering.com/TALOS/prerelease.php)

~~~
nickik
The hole point of a free ISA is that many different people can produce them so
that it will reach a economy of scale and chip producers will face competition
making dirving down price.

Its not garantied to work but its a worty target.

~~~
jeffdavis
Free is about freedom, not price.

~~~
TheAceOfHearts
So, freedom is only for the rich?

~~~
jeffdavis
Freedom is sometimes efficient enough that it costs nothing to have freedom.

Other times, there are real or artificial barriers that mean freedom has a
cost. In those cases, someone has to bear the cost or forego freedom.

------
faragon
AFAIK, most advanced RISC-V design includes superscalar and OoOE (e.g.
comparable to a MIPS R10000 (1995) or an Intel Pentium Pro (1995)), while the
RISC-V for the IoT is comparable to a typical single instructions per clock
RISC CPU, e.g. MIPS R3000 (1988).

The success in the IoT will depend not only in a cheaper price because of no
royalties, but also in the "ecosystem": peripherals, buses, etc. Running Linux
is a huge start, so I have no doubt it can be a success in this field.

Regarding the use in mobile and desktop, it will have to wait until SIMD
extensions are introduced, and software being adapted (e.g. ffmpeg/libav
including RISC-V assembly SIMD implementation for the codecs).

Anyway, realistically, for the RISC-V getting enough traction, some big player
should bet on that, which is currently highly improbable, unless some
Apple/Samsung/Huawei/Google gets crazy enough for doing it.

~~~
Nokinside
>Regarding the use in mobile and desktop, it will have to wait until SIMD
extensions are introduced

I'm little confused about this talk and comments in here relating to open
source in high performance applications (desktop, servers etc).

The RISC-V ISA is open source, I get that. There can also be open source
Verilog/VHDL designs available. They are probably good for small low
performance IoT applications and old processes.

But there is long way from ISA to silicon in high performance VLSI processor
design for a new processes and foundries. Architecture, logic synthesis,
timing analysis, floor planning, routing and placement, and ungodly amount of
testing .. I don't see anyone spending hundreds of millions of chip design for
RISC-V ISA and open sourcing it.

In other words, if you want competitive RISC-V chip, some company must spend
hundreds of millions to develop their own RISK-V chip architecture and they
will not open source it.

~~~
peatmoss
> In other words, if you want competitive RISC-V chip, some company must spend
> hundreds of millions to develop their own RISK-V chip architecture...

I wonder if a country like Russia, wanting something that they can deploy
without worrying that the NSA & Intel are cooperating on state spying, will
eventually try and take something like this and bootstrap a domestic
semiconductor line of business.

~~~
Nokinside
Russians have build their own processors for decades. They have used SPARC
instructions sets and they also have their own VLIW Elbrus 64-bit ISA and
processors are made by TSMC for 28 nm process. It has Intel x86 comparability
with system-level dynamic translation.

Just adopting new Instruction Set Architecture (ISA) is not going to help to
magically boost semiconductor business.

~~~
srett
The Russians have Baikal (T1), the Chinese have Loongson (3A/B). Both are MIPS
based. Unfortunately, even though both announced that there will be consumer
hardware available over a year ago, it did not happen. So I'm not too
optimistic regarding RISC-V.

------
DonbunEf7
I want to buy RISC-V, both to play with and to support the cause. What are my
options like and should I buy something now or wait for the next generation?

~~~
ktta
Apart from buying an actual dev kit like HiFive from SiFive, a great way to
get into it is to buy SiFive's FPGA kits

[https://dev.sifive.com/freedom-
soc/evaluate/fpga/](https://dev.sifive.com/freedom-soc/evaluate/fpga/)

The FPGA board can be used for other things too. If you are really
adventurous, I'd suggest buying a FPGA board with better chip so you can fit
in larger IP blocks in the future. It will work perfectly fine as a
replacement for the above FPGA kit I've linked to.

My suggestion would be this[1]. It has a pretty large LUT count so you can go
nuts. The RAM and Ethernet will be pretty useful if you want to run linux[2]
and test out stuff. It'll be a bit hard to run linux on it right now.

On the other hand, you can choose a Parallela board[3] which comes with a FPGA
chip along with a new (soon to be retired) arch called epiphany. Here[4] is a
GSoC project which runs linux on that board using the FPGA.

[1]: [http://store.digilentinc.com/nexys-4-ddr-artix-7-fpga-
traine...](http://store.digilentinc.com/nexys-4-ddr-artix-7-fpga-trainer-
board-recommended-for-ece-curriculum/) [2]: [https://github.com/riscv/riscv-
linux](https://github.com/riscv/riscv-linux) [3]:
[https://www.parallella.org/](https://www.parallella.org/) [4]:
[https://github.com/eliaskousk/parallella-
riscv](https://github.com/eliaskousk/parallella-riscv)

~~~
e12e
I see that what they recommend for the freedom platform

[https://www.sifive.com/products/freedom/](https://www.sifive.com/products/freedom/)

today, is a dev board

[https://dev.sifive.com/freedom-
soc/evaluate/fpga/](https://dev.sifive.com/freedom-soc/evaluate/fpga/)

that costs around 3500 USD:

[https://www.avnet.com/shop/us/p/kits-and-
tools/development-k...](https://www.avnet.com/shop/us/p/kits-and-
tools/development-kits/xilinx/ek-v7-vc707-g-3074457345626227804/)

Do anyone here know what kind of "classic pc" performance one is likely to get
out of a board like that? Could you get on the order of low-end pc (~500
dollar soc / netbook with real gigabit ethernet, sata6 and usb3) from
something like that, if paired up with a reasonable cpu design?

~~~
q3k
A somewhat speed-optimized IP CPU core [1] runs at 600DMIPs on a Virtex7. I
would hope that SiFive is in the same ballpark, but it's probably slower.

Even in a best-case scenario, this is nowhere near a low end consumer PC.

edit: For reference, my 5 years old Thinkpad x230 does around 7400 DMIPs per
core.

[1] - [https://www.xilinx.com/products/design-
tools/microblaze.html](https://www.xilinx.com/products/design-
tools/microblaze.html)

~~~
e12e
Well, that actually sounds a lot better than I feared - I have a aging aspire
acer one that works fine as a lightweight Linux desktop.

------
webaholic
RISC-V is atleast 10 years away from competing with x86 and ARM. It is just
now getting to a point where it can power arduino class hardware. Long way to
go... but looks promising.

~~~
jbarham
The Freedom E310 chip in the HiFive1 board is shipping today and is already
competitive with embedded ARM:
[https://www.crowdsupply.com/sifive/hifive1/#comparisons](https://www.crowdsupply.com/sifive/hifive1/#comparisons).
It's comically faster (i.e., 100x) than the AVR chip in the Arduino Uno board,
but the similar form factor makes it cheap & easy for early adopters to play
around with.

I'd bet that within five years a good proportion, even the majority, of Amazon
& Google servers, will be running on RISC V chips.

~~~
nezza-_-
Is there a power consumption comparison?

~~~
nezza-_-
(I know there is DMIPS/mW, but looking for a direct power consumption
comparison)

------
pubby
As someone not knowledgeable about hardware, I really enjoyed reading Agner
Fog's message board where he and others discuss creating a new open source
instruction set:
[http://agner.org/optimize/blog/read.php?i=421](http://agner.org/optimize/blog/read.php?i=421)

RISC-V is discussed some, and part of the discussion is how to improve it.

------
blitmap
I look forward to a RISC-V proc powering my laptop with some ridiculous Nvidia
GPU. We must escape x86 :(

~~~
zanny
There is some gentle irony in wanting an open source ISA CPU paired with a GPU
so proprietary the ISA is not even public knowledge.

~~~
blitmap
I'm looking forward to the day we can operate dedicated, proprietary GPUs like
black boxes we can turn on and off at will as optional accelerators. :-)

------
figers
Isn't ARM the RISC solution that is already here? Already dominating mobile,
Microsoft is soon to be announcing x86 apps running on Windows on ARM

~~~
wyager
ARM is too license-encumbered. If we're going to switch away from x86, it
might as well be to something that admits free development and production.

~~~
sweden
Things are not that straight forward, I wrote a better comment here:
[https://news.ycombinator.com/item?id=14284409](https://news.ycombinator.com/item?id=14284409)

~~~
wyager
I'm aware that individual implementations of the ISA are nonfree. There's
still a huge benefit to using the free ISA, because we can target nonfree
hardware while necessary and our software will just work on free hardware when
it's available. There are already some free low-power designs, and if RISC-V
gains traction I expect some free high-power designs to come out of the
woodwork.

A robust open processor ecosystem could be the impetus for a huge improvement
in open-source EDA tooling and public EDA research. Even now, the absolute
cutting edge in HDL research is free and open-source (and 100x more user-
friendly than anything to come out of Xilinx or Altera), and I suspect the
same would happen for silicon-targeting synthesis tools if there was a demand
for it.

The idea would be to get 90% of Intel's performance for 5% of the work. Intel
spends insane amounts of money on manual routing and optimization, extensive
testing at every stage of prototyping and production, stuff like that. The
creative laziness of the free software/hardware people could probably improve
on that _very_ substantially with minimal losses to the finished product.

------
alkoumpa
I wonder how of those fit in a zedboard. (not going to ask how many hours of
tool fighting that would require though).

~~~
sidereal
Running on a Zedboard is quite well documented; only took me a couple of hours
to do it from scratch following their instructions: [https://github.com/ucb-
bar/fpga-zynq](https://github.com/ucb-bar/fpga-zynq)

~~~
alkoumpa
I meant in a SIMT fashion, more like a GPU

------
sweden
I see on this thread a lot of people getting blind-folded by the "open-source"
term attached to the headline of this article.

First of all RISC-V can mean more than one thing: it can refer to the
architecture, which is in fact open and free to use, or it can refer to the
implementation of the same architecture, which will not be necessarily free or
open source. For example, check the so claimed SiFive company which was
promising free and open source implementations of RISC-V:
[http://www.eetimes.com/document.asp?doc_id=1331690](http://www.eetimes.com/document.asp?doc_id=1331690)

"“A year ago there was quite a debate if people would license a core if there
was a free version, [but now] we’ve seen significant demand for customers who
don’t want an open-source version but one better documented with a company
behind it,” said Jack Kang, vice president of product and business development
at SiFive."

By the end of the day, they just decided to follow ARM's path by providing
license fees to their CPUs.

Secondly, when people say that RISC-V is "free" and "open-source" and that
will allow companies to create cheaper and more open hardware, that is just an
illusion. There are many more things on a SoC other than a CPU (like memories,
communication buses, GPUs, power management processors, and so on). Cutting
costs on a CPU will not make the cost of an SoC go down to zero, the CPU is
just a small part of the puzzle. With RISC-V, you either need to implement the
CPU yourself (which will be extremely expensive and time consuming) or you
will have to find someone who provides with CPU cores already implemented. And
of course that you need to have support and guarantees that the cores you
bought will work on silicon. There will be always a huge cost associated when
shipping CPUs, you can't escape from that.

You can already imagine that open-source hardware doesn't play by the same
rules as open-source software, it's a completely different game with
completely different rules.

And people speak of ARM's royalties like if they were a very bad thing. Truth
to be told, the royalties you pay ARM can be a very good deal taking into
account that you get access to silicon proven CPU cores, support from the best
engineers in the industry and you automatically get covered by the many CPU
patents that ARM owns. And you can even choose on how you want to pay for
ARM's CPU licenses: you can either choose to license an already implemented
CPU design by ARM or you can buy an architectural license and implement your
CPU completely from scratch (this is what Apple and Qualcomm are current
doing). You don't need to be completely tied to ARM. Even in the royalty fees
you can choose whether you want to pay a big upfront license fee but then
paying low royalties per device or you can choose to pay a low upfront license
but compensating on the royalties per device.

There is a lot of misinformation going around the possibilities of RISC-V,
mostly of this misinformation coming from people involved in the development
of the spec. Don't be fooled by the buzzwords "open-source hardware" and "free
hardware".

~~~
jbarham
> You don't need to be completely tied to ARM.

The point is that if you want to use the ARM ISA you have to pay ARM. Not so
with RISC-V. Anyone is free to fab a RISC-V chip without paying royalties.

~~~
sweden
You are talking like you could download RISC-V from the internet and send it
to the foundry for mass production without additional costs or effort.

RISC-V is just a document, is not an implementation. There are many costs
involved into designing a CPU that end up costing much more money than paying
a license fee.

Check this comment:
[https://news.ycombinator.com/item?id=14284450](https://news.ycombinator.com/item?id=14284450)

~~~
iliis
How about this: [http://www.pulp-platform.org/](http://www.pulp-platform.org/)
? It still in development, but the plan is to release the full CPU. You still
need process/foundry specific data of course (things like flash-cells).

~~~
petra
The GAP8 is a real product based on the pulpino. It's a cpu, more of a low-
power embedded dsp/mcu, and a good one at that.

[http://www.eetimes.com/document.asp?doc_id=1330188](http://www.eetimes.com/document.asp?doc_id=1330188)

------
psydk
After enjoying coding on 680x0 in my youth and later being frustrated by x86,
I acclaim that new ISA. There is a design decision I'm curious about but I
could not find related information. How did they come with the names "x0, x1,
x2..." for general purpose registers, instead of the more conventional "r0,
r1, r2..."?

~~~
_chris_
x for "fixed point". r for "register" is too vague.

------
posterboy
What is so special about reduced ISAs, what's the differentiating factors
between them?

I mean they are so reduced that the ones I've seen are largely the same few
logic ops. RAM access and interrupts might differ some, but a) memory access
should follow the implementation and b) essentially everything else is memory
mapped (avr, c51, pic)

~~~
FullyFunctional
To fully appreciate this, one would need much experience with microprocessor
implementation. It's not reduced for the point of being simpler or smaller,
but because it represent a local optimum of perf/area for running C code,
especially for small to medium implementations.

However, much like the Alpha, RISC-V has been carefully designed to be
efficient to scale UP, that is, to superscalar out-of-order implementations.

Do read the spec and the footnotes; they are delightful:
[https://raw.githubusercontent.com/riscv/riscv-isa-
manual/mas...](https://raw.githubusercontent.com/riscv/riscv-isa-
manual/master/release/riscv-spec-v2.2.pdf)

------
restalis
So many RISC options and almost none for CISC. If you want yet another low
power chip, then it makes sense. If, however, you want to get real on
efficient cache usage and a high instruction-per-execution ratio, just do
yourself a favor and stop ignoring the costly experimenting results that the
industry already paid for.

~~~
Nomentatus
This just doesn't match the research I've read. CISC wasn't about speed of
execution, and x86 isn't an asset, there. (As I understand it Intel's
expertise in compilers, emulation of CISC by RISC, and manufacturing are
wonderful compensating factors.)

------
jbarham
Relevant article: [http://makezine.com/2017/05/03/sifive-brings-open-source-
to-...](http://makezine.com/2017/05/03/sifive-brings-open-source-to-chip-
level/)

------
silur
An opensource, non-licensed, low-cost embedded processor -> sifive sells it
for 600.000$ minimum.

------
roryisok
I always thought ARM chips _were_ RISC. shows what I know

~~~
indolering
That's how they started out, but there is always pressure to add new
instructions for niche markets. But since there isn't any coherent way to
implement extensions it means they have to pollute the entire ISA. RISC-V was
carefully designed to allow for extensions.

~~~
FullyFunctional
No it was never a [real] RISC. Even the very first version included
predication and shift in most instructions. They weren't even fast. The event
that changed everything was when DEC Alpha engineers (for reasons I don't
know) decided to use their expertise to created StrongARM. This ironically
ended up at Intel and was renamed XScale, before being spun out. (EDIT:
grammar & typos)

------
jlebrech
would there be a advantage to not only creating a reduced instruction set but
a minimal instruction set and letting the compiler do the rest. especially
when you can add a lot more cores, so that mul becomes a cpu core with a
counter and add for example.

~~~
FullyFunctional
No.

