

The Itanium processor, part 2: Instruction encoding, templates, and stops - Mister_Snuggles
http://blogs.msdn.com/b/oldnewthing/archive/2015/07/28/10631038.aspx

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faragon
VLIW processors with dynamic configuration of the opcode instruction group has
a lot of potential in the future, in my opinion. E.g. 128 or 256 bit "opcode
groups" with variable-size opcodes, using their own temporary registers, even
custom programable opcodes for ad-hoc opcode compression, etc.

The failure of the Itanium because of cheap x86 chips doing "macro-op"
execution, more efficiently than the Itanium explicit VLIW, is the other side
of the same coin: no matter if explicit or implicit, the way to increase
single-thread IPC (instruction per clock) rate is doing more in parallel and
hiding execution latency. So, explicit, or as hidden abstraction, VLIW-esque
execution seems to be unavoidable.

~~~
WallWextra
Parallel, speculative execution is what's unavoidable. The VLIW idea of
statically compiler-scheduled parallelism and speculation has not been
successful for general-purpose code. The last generation of Itanium abandoned
explicit, statically-scheduled parallelism and switched to out of order
execution, like every fast general-purpose CPU uses.

~~~
anon4
> _has not been successful for general-purpose code_

Let me interject that it has also not been successful for AMD's line of
videocards - they used a VLIW architecture before transitioning to a SIMD
architecture codenamed Graphics Core Next or GCN in 2011. nVidia had been
using SIMD for quite a while before that, but some of their latest cards have
a few VLIW features like the option to explicitly specify parallelism between
instructions.

~~~
WallWextra
Apparently they switched because VLIW wasn't good for GPGPU workloads, which
is in keeping with the general theme, that VLIW works very well on certain
highly-specific DSP-ish workloads.

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smcl
Is the Itanium bundling described in the article a pretty common pattern in
cpu architecture? The only CPU architectures I knew fairly intimately (Analog
Devices Blackfin and SHARC - neither particularly mainstream) had a limited
version of this and, at least in Blackfin's case, was pretty key to achieving
reasonably performant code.

~~~
willvarfar
It's fairly common in newer ISAs.

For a very modern take, [shameless plug] the Mill CPU instruction encoding
talk is very entertaining: [http://millcomputing.com/topic/instruction-
encoding/](http://millcomputing.com/topic/instruction-encoding/)

(Mill team)

~~~
pslam
It's also very common in _older_ ISAs, especially DSPs. As pointed out
elsewhere, it's common in VLIWs (which is generally "older" ISAs).

A good example is the Motorola 56K DSP family. Instructions are 24 bit wide
(24 bit wide memory!). They come in a few formats, which can be broken down
into two major types: complex instruction, or simple instruction plus up to 2
memory moves and address updates.

It's basically designed around performing a single-cycle 24x24->56b multiple-
accumulate with two memory reads and address increments, with zero loop
overhead. The rest of the ISA really, really suffers for it :) But it's
impressive when it's doing exactly what it was designed to do! It's a great
example of a domain-specific ISA.

Also worth noting that in 56K, there is no score-boarding or other dependency
tracking to automatically insert pipeline bubbles. That's the job of the hand-
writer/assembler/compiler. If you get it wrong, it simply does something
undefined. It's "fun" when this happen.

~~~
CountSessine
Yes - this seems to be a common design in DSPs. TI's c64x series is similar -
'instructions' are 32 bits wide and 8 of them are bonded together and issued
simultaneously for a mammoth 256 bit instruction 'packet'.

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hollerith
Itanium is the first processor architecture in whose design patent lawyers
were heavily involved. (I try to spend my personal learning time on tech that
isn't patented.)

~~~
acallan
Honest question: like what technology? Is there an area of technology that is
relatively patent-free?

~~~
hollerith
No one talks about patents on programming-language features. So, there is an
example for you. In the 1990s or early 2000s, the designers of a programming
language named Curl out of MIT tried to protect their design with patents, but
they were a very small minority among PL designers (at least at that time and
since that time), and I don't think their PL has any remaining users.

Because of the nature of the patent system, it is impossible to state
definitively that none of the currently-popular PLs currently have any patent
encumberances, but we can say that none of the project leaders or main
contributors to the design of any of the popular PLs have been accused of
pursuing patents on their creations. Nor does anyone AFAIK complain or warn
about any popular PL's being patent-encumbered.

Although most designers of instruction-set architectures that have seen
significant economic use _have_ pursued patents on this or that feature or
technique, Itanium is AFAIK the only one where the patent lawyers were
involved in the _early stages_ of the design of the architecture.

~~~
kyberias
This is the first time I see PL used as an acronym for programming language.

~~~
ceequof
It's used quite often among PL nerds: [http://lambda-the-
ultimate.org/](http://lambda-the-ultimate.org/)

