
RISC-V 3D GPU - EvgeniyZh
http://libre-riscv.org/3d_gpu/
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monocasa
Recent discussion:
[https://news.ycombinator.com/item?id=18094734](https://news.ycombinator.com/item?id=18094734)

What I said then:

I don't have particularly high hopes for this. "Start looking at HW" is their
last step in the roadmap. GPU microarchitectures are all about being a
reflection of the hardware, amortizing a lot of traditional CPU components
across as many threads as you can, to such a degree that there are ISA
implications.

EDIT: What would be cool would be a more traditional GPU architecture, married
to RISC-V minion looking cores that today already exist, but aren't open at
all. There's a lot of very closed (even more so than shader unit) RISC
processors in GPUs. AMD has a RISC core reading and processing the command
lists, among other things. [https://github.com/fail0verflow/radeon-
tools/tree/master/f32](https://github.com/fail0verflow/radeon-
tools/tree/master/f32) PowerVR has one doing thread scheduling and argument
marshaling (Programmable Data Sequencer). Nvidia has their cores that they
just switched to RISC-V.

Imagine having a custom command list tailored to your application sort of like
the benefits custom N64 RSP microcode had.

