
IBM Open-Sources Power Chip Instruction Set - Katydid
https://www.nextplatform.com/2019/08/20/big-blue-open-sources-power-chip-instruction-set/
======
bem94
I have so many questions:

\- Where can I get the ISA specification?[1]

\- Where can I get a compiler?

\- Is there a link to the "softcore model"?

With RISC-V you can start very simple and small (micro-controller) and work
your way up in understanding and implementation to a very large core
(application class). POWER is a monster of an architecture, designed more for
"big iron". I guess that might limit the "hobbyist" factor RISC-V has.

1\. This I think, all 1200 pages of it:
[https://openpowerfoundation.org/?resource_lib=power-isa-
vers...](https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0)

~~~
kop316
I own a Talos II
([https://www.raptorcs.com/TALOSII/](https://www.raptorcs.com/TALOSII/))
computer. It actually runs an official port of Debian
([https://wiki.debian.org/PPC64](https://wiki.debian.org/PPC64)) on it, which
includes a compiler.

~~~
voldacar
I have drooled over the Talos II for quite some time...

Do you have a particular use case that makes POWER make sense over x86, or do
you share my paranoia and love of non-mainstream ISAs?

~~~
einpoklum
Use of GPUs. Not Talos II it seems (?), but with POWER, GPUs are first-class
citizens on the system, with NVLink-2-bus access to main memory as the CPU -
150 GB/sec in each direction! (simultaneously!)

~~~
madez
Are all accesses to the memory from the GPU still checked for permissions at
the hardware level by an IOMMU?

~~~
rrss
Yeah, checked for permissions in hardware, but not by an IOMMU. Requests from
the GPU are forwarded to the "standard" SMMU. See [http://www.ieee-
hpec.org/2018/2018program/index_htm_files/13...](http://www.ieee-
hpec.org/2018/2018program/index_htm_files/135.pdf)

------
cipherboy
I'd like to recommend the friendly people at Oregon State University Open
Source Labs [0] who host POWER resources for open source projects. If you're
looking to see what the ISA can do on P8 or P9 system, I'd definitely contact
them and see if you can get a VM.

There's also a cool vector library [1] that bridges the gap between different
versions of the ISA and different compiler versions.

[0]:
[https://osuosl.org/services/powerdev/](https://osuosl.org/services/powerdev/)
[1]: [https://github.com/open-power-sdk/pveclib](https://github.com/open-
power-sdk/pveclib)

~~~
tpearson-raptor
Shameless plug, but you can so grab a POWER9 micro VPS (and large ones too)
without any human intervention at integricloud.com . Those are commercial /
paid though, not free.

------
andyjpb
An open, high end CPU design is really going to change the cloud market. An
ISA like this is a first step in that direction.

Facebook and Google already have their own compute projects and, like Amazon,
have access to custom versions of silicon from a variety of vendors.

With a properly open CPU design we'll start to see the first tightly
integrated, vertical "cloud" products that maybe still have a "commodity" API
on the top (or maybe not?) but are custom _all_ the way down from there.

With the end of Dennard Scaling, if not Moore's Law, Open ISAs and Open CPU
designs will radically change both the hardware and compute markets and
ecosystems over the next 5 to 15 years, similar to what we saw with Open
Source in the 1990s.

Of course, it's not clear that POWER will be the one to do that, and RISC-V
isn't going to be making a grab for Intel's crown any time soon, but this
looks like IBMs bid to lead in that area.

When the cloud vendors start building systems like this they'll not look too
much different from mainframes and IBM wants to continue to own that market.

~~~
mlyle
It's a far, far cry from an open ISA to having multiple competing vendors, let
alone open CPU designs.

It was much earlier, but OpenSPARC's impact was limited-- and that was full
RTL.

If POWER is open, does anyone really want to make competing high-performance
designs-- let alone open them? Better to take something like RISC-V and come
up with the first high performance design.

This is especially true when you consider IBM's vertical integration: IBM is
the only real POWER OEM and the only real POWER semiconductor vendor.

(If we really assume a reduction of innovation in processors, and a 15 year
time horizon... expiration of IP becomes a significant factor, too. Why not
just make generic ARM?)

~~~
Annatar
"Better to take something like RISC-V and come up with the first high
performance design."

The problem is that RISC-V mnemonics and programming model is so retarded (as
compared to MC68000 or UltraSPARC) that one needs a compiler to abstract and
hide that mess away. The other problem is that in several years in which
RISC-V has been hyped, nobody came up with a 19" rack server design, let alone
sold one priced competitively with a 1U P. C. tin bucket server. RISC-V is all
hype, but without serious hardware, its impact will be and remains
questionable at best.

~~~
pjc50
> mnemonics and programming model is so retarded

Could you provide some examples instead of a slur?

~~~
Annatar
move dst, src, src -- I could stop right here, but wait, there is more!

lui, auipc -- because two instructions are better than a simple move.b or
move.w. Really, what nonsense.

sx, ux - I'm speechless at that nonsense.

bltu, bgeu -- because blt and bge just weren't enough -- who designs a
processor like this?

lb, lh, lhu, lbu, sltiu instead of move.b, why? I challenge the sales pitch of
making more nonsensical instructions amounting to a simpler processor design!
(Boy does this make me mad.)

It's not a slur, it really is utterly retarded, especially if one used to
program an elegant microprocessor like the UltraSPARC or the Motorola 68000;
even the MOS 6502 is more elegant.

But to each his own, live and let live, right? Well why then must this botched
processor constantly be sold and paraded as the greatest thing since sliced
bread, a non plus ultra of processors, when it isn't?

~~~
DanBC
Plenty of HN readers have children with severe learning disability. Using the
word "retard"[1] is likely to attract downvotes.

[1] Unless you're talking about progress or watch mechanisms.

~~~
Annatar
That's exactly what I'm writing about, progress. RISC-V is not an advancement.
What is opposite of advancement? In a system, it's either regression or
retardation.

And expecting people outside of the Puritan U. S. to abide by the same
political correctness norms is extremely rude, inconsiderate and exclusionist
-- using those same politically correct norms no less, which is to say, the U.
S. should ban political correctness, and do so yesterday for the benefit of
everyone.

~~~
DanBC
I don't care what words you use. I'm just telling you that when you describe
people as retards you're going to get downvotes, and I'm telling you why that
is.

I'm not American and I don't live in the US.

~~~
Annatar
I didn't describe people as retarded, but their work. Even very smart people
often do dumb things.

~~~
DanBC
When you say things like this...

> mnemonics and programming model is so retarded

...you are going to get downvoted. This is because people who speak English as
a first language understand you to mean "this is stupid, like a retard". They
don't understand you to mean "this is delayed, like a watch mechanism would be
adjusted".

You can keep arguing that you didn't mean what you said, but at least two
people are telling you how your words are being interpreted.

~~~
Annatar
...you are going to get downvoted.

I would be a sad excuse of a being if I feared what some people on a random
forum will think of me, or "downvote" me in some arbitrary, imaginative
system. The entire thing is a delusion.

Not singling out anyone in particular but I'm a formed adult and have been for
several decades, and I do not require upbringing, id est, anyone telling me
how to behave or what not to write.

I will write it how I want and I shall not fear arbitrary decisions based on
some arbitrary policies someone somewhere thought up. If that gets me down-
voted or even banned, I will not let it bother me, as life does not revolve
around arbitrary websites trying to tell one how to behave and think and I
will damn myself into oblivion before I allow someone to impose such a thing
on me. Lest we forget: I'm the only one who decides that, and I'm not allowing
anyone to control my thinking or writing.

------
bryanlarsen
Will this do any better than open source SPARC, which was open sourced in
1999?

[https://www.eetimes.com/document.asp?doc_id=1140292](https://www.eetimes.com/document.asp?doc_id=1140292)

~~~
blihp
I can't see why it would. This would have mattered 20 years ago when there
weren't more compelling ISA's out there. But that's not today's world: ARM is
fairly ubiquitous and dirt cheap while RISC-V is a promising and open source
up-and-comer. This seems like a relatively non-event (or worse: confirming
that it's effectively a dying/dead platform) unless one has a significant
investment in Power.

~~~
classichasclass
Except neither of those are in the same performance ballpark as Intel, while
Power ISA is.

~~~
adwn
I might be misunderstanding you, but performance isn't in the ISA, it's in the
implementation. In fact, the x86 ISA is the best example for this: It's really
difficult to get competitive performance out of an ISA designed in the 70s,
yet billions upon billions of USD in R&D and optimization make it work.

~~~
ecnahc515
The ISA matters, otherwise we wouldn't care about SIMD. If your ISA is missing
SIMD functionality, then it doesn't matter how good your implementation is, it
will be slower than an implementation of an ISA that supports SIMD when it
comes to anything that can leverage SIMD.

------
PaulHoule
I like it.

Back in the day IBM ran a "System on Chip" factory based on PowerPC that gave
us the Bluegene/L supercomputer, the GameCube/Wii/Wii U, the Playstation 3 and
the Xbox 360. All of these combined one or more cores, coprocessors and tweaks
to hold its own against x86.

RISC-V is meant to be used like that, but memory management support is not yet
finalized. They are sampling prototype RISC-V chips with an MMU you can put in
a dev box to develop Linux on. Other than that you are not using Linux or
Windows.

If you think mainstream OS is bloated, then RISC-V has your number. If you
want very low cost it would be exciting to cut RISC-V down to have fewer and
less wide registers. The other day I saw an article about a guy who wants to
build RISC-V out of vacuum tubes and thought... 'cripes with all of those wide
registers it is a lot of tubes.

POWER is good-to-go right now for high end applications and can stay relevant
against ARM and x86 by staying open.

------
Annatar
They are misunderstanding why RISC-V and Raspberry Pi are popular: it's not so
much that they're freeware but that they are cheap. Very few people in IT know
how to implement processors in hardware even with an FPGA. What makes a
processor popular are cheap, affordable systems people can easily acquire in
an online shop at prices which compete with or are below contemporary P. C.
tin bucket hardware.

If IBM wants an uptake of POWER systems and people to develop on them and for
them, the only thing which might make a dent are sub-$500 USD complete
workstations and rack mountable servers. Otherwise, they will repeat the same
mistake which _Sun_ made, that is, they open sourced their UltraSPARC T1 under
GNU GPL but the uptake was nil, because few had the knowledge to design
systems around the processor. People want cheap, ready made toys they can
tinker with immediately.

------
gumby
Not a problem with the article but when it lists the various past contenders,
MIPS (with many times the lifetime installed base of, say SPARC, and still in
active production) doesn't get a mention. MIPS's IS has also been recently
open sourced. It's a cautionary tale.

I don't see the point of this effort for IBM. These things need communities,
and POWER simply doesn't have the community; as a proprietary architecture for
so long that nobody really decided to buy POWER but rather they wanted some
device/ecosystem/price point and POWER was how IBM could deliver it.

The article mentions RISC-V, which still has a nascent ecosystem and no
significant design wins (yet!!). But if you want to design a chip with it you
can find designers with some experience with it, people developing some IP you
might want to use, etc. Even that has more momentum.

------
olivierduval
Naive questions:

\- Will Huawei be able to use this processor design (now that it is open
sourced) to build it's own chips, bypassing ARM restriction & US IP ?

\- Are these processor designs usable in mobile device, or only in
workstations and servers (using to much power for example) ?

~~~
blattimwind
IBM targets the scale-up market (few big, fast machines) with POWER instead of
scale-out (many small, slower machines). Consequentally they are high
performance but not particularly tuned for high efficiency, because
performance is the more important design goal of the system.

~~~
dragontamer
[https://en.wikipedia.org/wiki/PowerPC_e6500](https://en.wikipedia.org/wiki/PowerPC_e6500)

Freescale hasn't made a new low-power Power chip in a while, but...
historically speaking, there were a lot of low-wattage / efficiency-focused
embedded POWER designs.

I don't know what happened politically between the companies to use ARM
instead. But I would imagine that ARM's instruction set was cheaper (or maybe
easier) to engineer than Power ISA. Hopefully Freescale engineers can chime in
on the discussion, because I'm really just shooting from the hip here.

I would expect most issues to come down to business politics. IBM open
sourcing the PowerISA is also a business politics move (I guess they hope to
recapture the lost ground in the embedded space).

PowerISA means operating with IBM's ecosystem: GCC, Linux, etc. etc. Remember
IBM has merged with RedHat, so there's a lot of promise for Linux support that
ARM and RISC-V don't necessarily provide. I think this is a good move.

~~~
floatboth
> promise for Linux support that ARM and RISC-V don't necessarily provide

uh, ARMv8 and RISC-V were developed with Linux in mind from the beginning,
they didn't even _have_ anything other than Linux/BSD/various-RTOSes, like IBM
did with AIX.

~~~
dragontamer
That's not the kind of support I'm talking about.

Who is writing the RISC-V compiler? If the RISC-V compiler for GCC or CLang
messes up, who do you call?

If the Power9 GCC / CLang compilers mess up, you call Red Hat for support. Red
Hat / IBM are now the same company, so they'll offer end-to-end services.

\-----------

ARM has okay support: the ARM foundation seems to be taking care of their
compiler kits / Linux patches / etc. etc. pretty well. But I don't think you
can buy an ARM support package from anybody... really.

I think the ARM / Linux ecosystem is still nascent. You get good support
through the Rasp. Pi community, and maybe the occasional Android Phone gets a
big community around it. But ARM / Linux ecosystem is quite poor outside of
Rasp. Pi.

ARM, as a company, is clearly designed as an "embedded" company. It provides
the documentation and compilers, but doesn't provide too many OS-level
services above that.

~~~
floatboth
> If the Power9 GCC / CLang compilers mess up, you call Red Hat for support

uh, where and when exactly did they offer that? Actually I don't remember
anyone anywhere offering commercial support for GCC or LLVM/clang.

Well, I'm not the type of person to look for commercial support for anything
ever, but I've heard of several companies that provide support for DBMSes like
PostgreSQL. Not so for compilers.

I just googled "gcc commercial support" and the results are the GCC FAQ, a
mailing list post about it from 2005 (!), GCC on Wikipedia, "Office 365 GCC"
(lol) and so on. Looks like it's just not a thing at all.

~~~
dragontamer
Sorry, not GCC / Clang. You're right.

But IBM's XL Compiler:
[https://www-01.ibm.com/support/docview.wss?uid=swg21110831](https://www-01.ibm.com/support/docview.wss?uid=swg21110831)

\-------

I think I confused it with ARM: ARM has a CLang-based compiler with official
ARM support IIRC. [https://developer.arm.com/tools-and-software/server-and-
hpc](https://developer.arm.com/tools-and-software/server-and-hpc)

I think the hobbyist (who won't get much support even if they're a paying
customer) benefits from free tools / free support / communities.

But it seems like a number of professionals prefer having a degree of
professional support in the products they use.

------
the_trapper
Interesting move by IBM.

See also OpenSPARC. [1]

I'm curious if anyone will do anything interesting with this.

[1]
[https://www.oracle.com/technetwork/systems/opensparc/index.h...](https://www.oracle.com/technetwork/systems/opensparc/index.html)

------
freemint
The IP/patents was doomed to expire anyway. But hey they got a free PR stunt
out of it.

Anyway it will be interesting what "non expired" patents they bundle with
this. Mostly because of
[https://archive.fosdem.org/2019/schedule/event/patent_exhaus...](https://archive.fosdem.org/2019/schedule/event/patent_exhaustion/)

which would allow people in the US to use these patents in any context as
long, they derived their worked from an Open Source Power processor which got
the patents exhausted and did not violate the Open Source license the
processor.

------
peter303
3 of the top 11 supercomputers in this years ranking are Power-9s.

------
vermaden
Still waiting for that modern POWER9 based laptop with 7-row classic ThinkPad
keyboard ...

------
sandfly
How is does this different from publishing the _instruction set_ , which was
presumably already available (if it weren't, how would one write an
application for it)?

~~~
Koshkin
I guess, publishing something does not necessarily mean making it public
domain.

~~~
tpearson-raptor
Right. For instance, the x86 architecture is published. If you try to build
anything that can interpret it, you'll get sued by Intel or AMD (or both, if
you really copied anything good).

What is less widely considered is that emulation is considered an
implementation of a CPU. So e.g. research labs at universities have been told
in no uncertain terms by CPU vendor legal notices to stop working on research
that is emulating the x86 or ARM instruction sets. Now with the POWER ISA
being open, everything about the ISA is fair game for research in emulation,
soft cores, hardware, etc., which does put it in a space that only academic
"toy" ISAs and RISC-V really sat in before.

~~~
reirob
But we have qemu [0] that emulates quite a lot of Instruction Sets. How comes
that it is allowed to exist, qemu is emulating quite a lot of instruction sets
[1] ?

[0] [https://www.qemu.org/](https://www.qemu.org/)

[1]
[https://wiki.qemu.org/Documentation/Platforms](https://wiki.qemu.org/Documentation/Platforms)

~~~
tpearson-raptor
The support is there, yes, but it's always been a grey / largely unenforced
black area. As soon as the emulator cuts into chip sales in any significant
way the tolerance for its use would stop.

IANAL, this is simply what legal folks are saying on this topic.

------
llampx
If only this had happened as Opteron was taking a beating in the server
market.

Now with EPYC Rome, I wonder just how many takers IBM will have.

~~~
brianwawok
There seem to be general paths for OS.

1) OS from the start. Develop in the open. Maybe lock some features behind a
paywall.

2) OS when something is not hot anymore. Take your formerly private stuff you
charged a lot of money for, and because so much better stuff has come out..
meh, let's OS it.

This is clearly a case of #2....

~~~
ch_123
While I agree that there's a whiff of IBM trying to offload responsibility for
older tech, I think some credit has to be given to projects which pre-dated
the current industry attitudes towards open source. A lot of things had to
happen (probably including people of a certain generation/era passing the
torch) before companies felt comfortable with the idea that they could open
source their tech, and still have a competitive advantage over anyone else who
would use it.

In the late 80s/early 90s when POWER appeared, and RISC fever was in full
swing, if someone, as a VP or C-suite level decision maker at a mega-corp like
IBM, declared "let's just release all the IP of our high performance processor
design to anyone who wants it!", they would have their coworkers and superiors
questioning their sanity, at very, very least.

~~~
StillBored
> if someone, as a VP or C-suite level decision maker at a mega-corp like IBM,
> declared "let's just release all the IP of our high performance processor
> design to anyone who wants it!", they would have their coworkers and
> superiors questioning their sanity, at very, very least.

Well that was basically the PPC consortium. I'm not sure how much
apple/motorola/etc paid to be part of it, but the idea was to build a common
ISA from multiple vendors.

------
baybal2
I'm afraid the are doing it at least 10 years too late.

------
rgblambda
Naive question: What would this mean for Xbox 360 emulators?

~~~
monocasa
As someone writing a 360 emulator, probably not much. The Cell docs are
already available (Xenon is a modified Cell PPE), and the ways that it's
different are a one off for Xenon that probably won't be documented in this
dump.

------
crb002
IBM is dead until it gets Z mainframes and Power servers in big a three data
center (AWS, GCP, Azure).

Guessing Microsoft will start with putting mainframes in the West Des Moines
data center since so many insurance companies are still dependent on DB2 batch
crunching.

~~~
wolfgke
> IBM is dead until it gets Z mainframes and Power servers in big a three data
> center (AWS, GCP, Azure).

Google _is_ using POWER9 servers in their data centers:

>
> [https://www.forbes.com/sites/patrickmoorhead/2018/03/19/head...](https://www.forbes.com/sites/patrickmoorhead/2018/03/19/headed-
> into-its-fifth-year-openpower-has-momentum-into-the-power9-generation/)

> [https://www.nextplatform.com/2018/03/26/google-and-its-
> hyper...](https://www.nextplatform.com/2018/03/26/google-and-its-hyperscale-
> peers-add-power-to-the-server-fleet/)

Of course, most of their servers are still x86; as far as I am aware, the
reason why Google also uses POWER9 servers is that they don't want to be _too_
dependent on the two manufacturers of x86 CPUs.

------
ausjke
might be too little too late.

I used to be powerpc developer myself, now nearly all the communities, the
ecosystem, the core developers are gone, it's beyond repair, sigh.

------
gigatexal
Phoronix ran benchmarks and current Talos II systems run hotter and slower
than equivalent x86 systems but maybe they will improve over time.

~~~
std_throwaway
AFAIK those benchmarks weren't specifically optimized for that processor
architecture. Most programs are optimized with x86 systems in mind. The
results for your specific application might come out differently.

~~~
ajdlinux
Cases in point: [https://sthbrx.github.io/blog/2018/08/15/improving-
performan...](https://sthbrx.github.io/blog/2018/08/15/improving-performance-
of-phoronix-benchmarks-on-power9/)

------
StillBored
Does this include the system IP? I asked that question when openpower started,
and it took a number of years before any of that started to show up. Even now,
i'm not sure its all there.

Its pretty hard to build a reasonable/compatible machine when you have to
"reinvent" the interrupt controller/iommu's/etc.

------
bogomipz
That article statues:

>"No one is saying that the OpenPower Foundation will have an easy time
growing its ecosystem, despite the many architectural advantages that Power
holds over other ISAs ..."

Could someone elaborate on what some of those "architectural advantages" over
other ISA are exactly?

------
std_throwaway
Is there a second independent manufacturer for Power processors?

~~~
blihp
NXP/Freescale

~~~
floatboth
Did they ever make anything faster than the 4-core QorIQ chip that powerpc-
notebook.org is using?

Current NXP networking chips are ARM Cortex based, like the LX2160 that's in
the upcoming SolidRun workstation (which they still haven't publicly
demonstrated ECAM PCIe on, sadly…)

~~~
aidenn0
Their very first of the T4 series was 12 core / 24 thread 64-bit e6500 based
(T4240).

------
aap_
Interesting. I would like to take a look at that softcore model.

------
haolez
What does it mean to open source an instruction set? What can we do now that
we couldn't earlier? (genuine doubt)

~~~
albandread
Probably means they wont sue you or bill you if you use it in your own
processor designs. The article mentioned releasing a softcore for FPGA; that
at least means you can run the instruction set on something. There are even
enthusiasts that might be interested in using an FPGA to build a whole
computer; for example the Amiga community have a PowerPC based operating
system. Instruction sets must also be an acquired taste; Power seems complex
to me; but a lot of people clearly like it.

------
Animats
28 years after introduction. A bit late.

------
alttab
Use xlc once. I'm done thanks.

~~~
arghwhat
Why in the _world_ would you use xlC, unless you're masochistic enough to
target IBM-AIX? PowerPC is a very well supported architecture, supported by
common compilers and operating systems.

~~~
StillBored
For the same reason people use icc, it generates faster code.

A couple of years ago I compiled part of the application I was building for
power8. The perf was pretty bad, so I rebuilt parts of it with xlc, and it was
literally over 2x faster. That made the machine competitive/faster than the
x86's we were using.

Now GCC/clang have bee getting better and the gap with icc is nearly closed.
I'm not sure how much of that applies to xlc, but i'm betting there hasn't
been nearly as much work optimizing for POWER as there has been for arm and
x86.

