
Berkeley’s RISC-V Wants to Be Free - jobstijl
http://www.eejournal.com/archives/articles/20141210-risc-v/
======
PythonicAlpha
As much I heard, the ARM instruction set is also not so simple as it could. So
a new, fresh and clean instruction set would be great and the comparison of
the two architectures looks promising.

I scan-read the paper, but did not encounter any number of registers. Does
anybody know, how many registers this architecture has/supports ... is there
any implementation yet?

Hope, there will be an implementation soon, and maybe a smartphone or tablet
computer based on it... (or a new Raspberry?)

Edit: Now I see, should be 32 registers, based on the 32bit opcode-format (5
bits to address any register).

~~~
userbinator
_As much I heard, the ARM instruction set is also not so simple as it could._

I'd argue that's part of why it's been so successful, especially in
competition with the other big ISA - x86. Complex instructions are _good_
because they do a lot in a small size, and a small size is good because it
conserves cache usage and memory bandwidth; decoding is rarely the bottleneck
now. That's why ARM has Thumb, and their latest cores are similar to x86's
uop-decoding and decoupled decoder/execution units.

The whole "it can be done faster in software" idea of RISC was mainly based on
some early CISC microarchitectures that weren't implemented as efficiently as
they could be, which doesn't imply that they couldn't be. Look at all the
instructions added by the various SSE extensions, for example; the
performance/speed improvements they provide are real, and the cost of the
hardware is basically negligible in comparison.

Here's an interesting comparison where ARM and x86 are quite close in power
efficiency, while MIPS is relatively far behind:
[http://www.extremetech.com/extreme/188396-the-final-isa-
show...](http://www.extremetech.com/extreme/188396-the-final-isa-showdown-is-
arm-x86-or-mips-intrinsically-more-power-efficient)

~~~
yaantc
I'm not sure that the Extremetech page allows concluding much on its own
regarding MIPS efficiency vs. others as the implementations are pretty
different and the only MIPS instance is an oddball: it's OoO and 4-wide as the
i7, while being on a very old process (90nm) while the all other chips are on
better processes, and the 3 or 4 wide ones on 32 nm. 3 process generations
tends to have an impact on efficiency ;)

Also on this topic: if the original MIPS was indeed very simple, recent
versions added thumb-like code compression, SIMD extensions, DSP extensions...
As everyone else does really. And you can get similar CPU benchmarks level as
other architectures. Then the very same instruction architecture can have
pretty wide power efficiency differences depending on implementations. Just
look at Atom vs. Core, A8 vs. 15... Even the same model shows big differences
based on implementation choices (optimize for speed vs. area/cost for
example).

As someone working on SoC, I believe the key difference in MIPS vs. ARM vs.
Intel is not so much the instruction set, but the work effort spent on
optimizing the implementations close to the processes. It's pretty obvious for
Intel, but ARM spends a lot of time with the big foundries (TSMC,
GlobalFoundries, Samsung) to make sure their implementation are well tuned.
And they pass on the know-how to their customers through what they call "POPs"
(Process Optimization Packages). This is important for ARM, but also for the
foundries as ARM is the de facto standard in mobile. A lot of work go in this,
and it shows at the high end. MIPS/Imagination recently propose something
similar for MIP, but they're far from having the same amount of resources.
That's the main difference between MIPS and ARM at the high-end IMHO.

~~~
WallWextra
It would have been nice if they had a MIPS core actually designed by MIPS.

------
faragon
“There are two major products that came from Berkeley: LSD and Unix. We don't
believe this to be a coincidence.”

Unix came from Bell Labs in the East Coast. Californian Unix is just a non-
elegant derivative, in my opinion (e.g. BSD sockets don't follow the "Unix
philosophy", and one explanation could be the LSD, I agree with that).

~~~
patrickg_zill
Could you maybe expand on your thoughts of BSD sockets vs. what SVR4 came up
with?

~~~
faragon
Well, BSD sockets don't use file abstraction. Plan 9 recovered "Unix
philosophy" in that regard. In my opinion.

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JoachimSchipper
Does anyone have actual experience using RISC-V? It does come with a gcc
toolchain, so it should just run C - but is it of any practical use yet,
relative to the enormous ARM (or MIPS, or even SPARC) ecosystem?

~~~
qwerta
We were investigating CPUs for embedded use. I am not sure right now if it was
RISC or MIPS. The performance was fraction of ARM or x86. But the consulting
company would build SOC exactly to our spec. There were zero licensing fees.

So for embedded use if performance is not important, I would seriously
consider it.

~~~
arbuge
Reading the article, I see no reason why there should be any major performance
issues inherent to RISC-V. Lack of an ecosystem looks like the issue, at least
initially. But a $1m licensing fee for a CPU with an established ecosystem is
an issue too...

~~~
sspiff
The reason the chips will be slower in practice is because they are produced
in small batches, and need to be produced by smaller fabs and by extension
much older process. MIPS is routinely produced at 95nm still.

~~~
asb
We at lowRISC intend to produce in volume at 40nm or 28nm.
[http://www.lowrisc.org/](http://www.lowrisc.org/)

~~~
arbuge
Looks really interesting. Where are you guys based? Cambridge, UK I'm
guessing?

~~~
asb
Yes, the core team is based in Cambridge, UK. However we do intend to be a
truly open-source project, with an open and distributed development process
which would involve arbitrarily geographically distributed third-party
contributors.

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bsder
Why redesign a new core? We have plenty to choose from that have semi-existing
ecosystems.

First, I'd just go with a MIPS core. This is effectively the original RISC
core, after all. Most patents have expired, and the Chinese have an
implementation.

If I didn't do that, I'd probably go with a DEC Alpha core. A shrunk, voltage
optimized Alpha core was what drove the StrongARM series, and people raved
about it. The Alpha architecture up through EV5 is quite clean.

Given that most data suggests that ecosystem and optimization is more
important than basic architecture, reinventing the wheel is not a good thing
here.

~~~
techdragon
Unfortunately the Alpha core is unlikely to ever return, much as its fans
would like.

Sparc is open back at the T1 T2 era pre oracle takeover. That's not a bad
place to go, but MIPS is not really ideal due to a lot of factors that make
the Chinese clones less than appealing.

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zzzcpan
Is there a picture of RISC-V architecture (with pipeline, ALUs, FPUs)?
Couldn't find anything.

~~~
asb
You're asking for a picture of a particular RISC-V implementation and its
chosen microarchitecture. The RISC-V ISA has a range of different
implementations each hitting different points in the design space and
different trade-offs in terms of area/performance. See for instance the
'Sodor' teaching cores [https://github.com/ucb-bar/riscv-
sodor](https://github.com/ucb-bar/riscv-sodor) [https://github.com/ucb-
bar/riscv-sodor/wiki](https://github.com/ucb-bar/riscv-sodor/wiki) which
demonstrate 1-stage, 2-stage, 3-stage, 5-stage, and micro-coded
implementations.

~~~
ibrahima
Oh man, that's cool. I must have just missed out on this when taking CS152, we
played with simulated SPARC when I took the course IIRC.

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higherpurpose
This could be used for stuff like Arduino at least.

