
Inside the Microsoft FPGA-based configurable cloud [video] - willyyr
https://channel9.msdn.com/Events/Build/2017/B8063
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samuell
The explanation of FPGAs between 5:00 and ~12:00 was very very good.

TL;DW:

\- FPGAs are more power-efficient than CPUs and GPUs

\- FPGAs are more flexible than ASICs

FPGAs vs CPUs:

\- CPU: Sequentially apply instructions on data in place

\- FPGA: In parallel, flow data through instructions in place

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samuell
Tried to scan the video to see if they have any support for reconfigure.io [1]
(Code FPGAs with Go concurrency primitives). Didn't see any mention. Anybody
knows more? Or I'll have to watch the vid in detail ... looks pretty pedagogic
anyways :) ...

[1] [https://reconfigure.io/](https://reconfigure.io/)

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monocasa
In general, code meant for sequential processors (even massively parallel
sequential processors) doesn't really translate into the potential gains you
see from FPGAs. I'm pretty skeptical that this gives you any gains.

Even OpenCL->HDL wasn't the huge boon it was supposed to be.

~~~
thesz
1) You're right. The problem here is the unpredictability of the buffer's size
- it's equivalent to halting problem in general. You miss just one item in the
buffer and you risk circuit not working at random times.

2) OpenCL->HDL takes hours to complete due to need to synthesize, whereas
OpenCL->CPU code takes seconds at worst. The time to get working (synthesized)
code is major blocking factor in utilizing FPGAs anywhere.

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nintendo1889
Google's TPU uses 28-40 W, Microsoft's uses 25 watts.

Relevant but not deep: [https://redmondmag.com/blogs/the-schwartz-
report/2016/10/dif...](https://redmondmag.com/blogs/the-schwartz-
report/2016/10/different-cloud-based-ai-paths.aspx)

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mmalone
Why aren't more people deploying FPGAs like this? I started looking into using
FPGAs for distributed systems work about six years ago when I was building a
distributed database. Since then, about once a month I come across some
problem that an FPGA could be useful for (i.e., enhance the performance enough
that something otherwise infeasible becomes feasible). The devices themselves
aren't that expensive (<$100) so why doesn't every server have one? Is there
some hidden cost I'm not aware of (socket real estate, power consumption)? Or
is it just a chicken-and-egg problem with not enough engineers asking for them
because they don't know how they work because they're not more widely
deployed?

~~~
JoachimSchipper
FPGAs are hard/expensive to program (including being very painful to debug),
at least for most tasks - and few people are good at both FPGA and software
development, so you may need different people to do the programming. New FPGA
generations can require substantial re-work, at least for best performance.
Many tasks would require kernel support (which is another "hard/expensive to
program, and annoying to debug", although not nearly as bad).

You need a deployment scenario where FPGAs beat GPUs (and CPUs) by enough to
be worth that pain, but not by enough that someone already has a ready-made
ASIC for you. I agree that one would expect to see _more_ deployment of FPGA's
naively, but not a lot.

~~~
mmalone
This seems right, except that Microsoft has clearly developed a higher level
language than VHDL / Verilog for writing "virtualized network functions" that
compiles down to something they can flash onto an FPGA (they call it Flow
Tables in the presentation). So there's a higher level language that's,
presumably, more intuitive for "normal" engineers to work with. When a new
FPGA comes out the compiler is re-written and high level code stays the same.
Basically the same thing we do with CPUs. So they're not _inherently_ hard to
program.

SDN is common, and definitely a scenario where FPGAs outperform GPUs. Same for
machine learning. (FWIW, Google uses ASICs for both of these use cases.) What
we need is a high level language and access to FPGAs. I've been interested in
business opportunities in this area, but it's hard to monetize. What's
somewhat surprising is that the language bit hasn't been solved in the open
source world either. My suspicion is that the reason an open source language
like Flow Tables doesn't exist (AFAIK) is that there's not widespread access
to FPGAs.

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drewg123
Does anybody know if the FPGA accelerated NIC uses a different driver on the
guest VM, or just the standard hyperv net driver?

If it uses the standard hyperv driver, can a guest be migrated live between
accelerated and unaccelerated hosts?

~~~
kaidchen
Yeah, there's a different driver in the VM needed

