
Centaur Unveils Its New Server-Class x86 Core - parvizp
https://fuse.wikichip.org/news/3099/centaur-unveils-its-new-server-class-x86-core-cns-adds-avx-512/
======
iforgotpassword
CentaurHauls!

I didn't even know they are still around. Still remember my VIA epia mini ITX
board with 800 MHz. Must have been around 2004, before Intel tried the same
with Atom. At the time AMD and Intel didn't really have anything to offer in
that segment, so that was really a great solution for having a small 24/7
machine in your dorm room that's completely silent.

Cool to see they're still going.

~~~
jchw
> At the time AMD and Intel didn't really have anything to offer in that
> segment

Didn’t AMD have Geode for this segment?

~~~
bitL
Wasn't Geode actually Cyrix?

~~~
jchw
Mostly, but the NX Geode was Athlon based IIRC.

------
yorwba
Related discussion where this link was posted in the comments:
[https://news.ycombinator.com/item?id=21789777](https://news.ycombinator.com/item?id=21789777)

------
dmitrygr
No uop cache is a very strange choice. They way they phrased it "we can meet
our _current_ performance goals without it in _this generation_ " just sounds
like they didn't manage to get it working in time.

~~~
greggyb
That seems to be a very pessimistic interpretation.

Perhaps, they've been evaluating that as an architectural change, but
recognize it would be a significant engineering effort. And they can already
meet their current performance goals. Thus, they will wait until a future
generation, when they cannot meet their _future_ performance goals. In _that
future_ generation, they'll implement a uop cache.

------
quotemstr
One aspect of the design that I like is not downclocking when using wide
vector operations. That Intel chips cut their frequency if anything is using
AVX-512 makes the instruction set practically unusable for general purpose
software, since the whole core runs at that reduced frequency (across all
processes and threads) whether or not it's doing vector work. Consequently, it
only really makes sense to use these operations if you can dedicate a whole
clock domain to them and nothing else --- and few systems are set up that way.

~~~
gruez
[deleted]

~~~
close04
I don’t think OP means throttling. AVX frequency scaling imposes different
base and turbo in different types of scenarios.

------
VectorLock
I found out the other day there is a documentary called "The Rise of Centaur"
that I haven't had a chance to watch yet but its on my list.
[https://www.amazon.com/Rise-Centaur-Glenn-
Henry/dp/B01FSZU6F...](https://www.amazon.com/Rise-Centaur-Glenn-
Henry/dp/B01FSZU6FK)

Also surprised to see they're still a going concern.

------
nullc
I wonder if it'll be more secure than past VIA offerings (
[https://www.bleepingcomputer.com/news/security/backdoor-
mech...](https://www.bleepingcomputer.com/news/security/backdoor-mechanism-
discovered-in-via-c3-x86-processors/) ) or Intel with the opaque, non-owner-
controlled, and often vulnerable ME.

------
ris
What are we going to do with all these "AI coprocessors" once the AI bubble
bursts? Are they at least well documented or flexible enough to be used for
more general float crunching?

------
seriesf
It's hard to imagine how one gains confidence in this kind of product. How
does this vendor have the resources to qualify this chip? Intel can already
barely qualify theirs. The last seven generations of AMD parts shipped with
serious defects that were discovered by customers in the field. Centaur and
Via are far smaller. Is it really possible to be scrappy and scrappily produce
a bug-free assembly of billions of transistors?

~~~
wmf
Centaur has already built several generations of x86 processors so you need to
make a stronger argument than that.

~~~
seriesf
Sure but what have they built that’s this complicated? The recent AMD flaws
have been things like frequency scaling doesn’t work (zen). The more features
you have, the harder it becomes to validate the product.

