
Arm Shows Backside Power Delivery as Path to Further Moore’s Law - magoghm
https://spectrum.ieee.org/nanoclast/semiconductors/design/arm-shows-backside-power-delivery-as-path-to-further-moores-law
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ChuckMcM
This is a super interesting result. As others have pointed out, two sided die
have been tried in the past but it was expensive and the backside components
could not be very interesting because you are limited in what you can do (for
example ion implantation can shoot through the place you're trying to hit and
damage the component on the 'other' side, not a problem when you are laying
down the first set of devices on raw silicon, a big problem if you've got
structures underneath you need to protect).

Whereas just doing power delivery on the back side is much simpler proposition
and you could likely make simple transistors to give you the ability to switch
more fine grained power domains on and off for even better power and heat
management.

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baybal2
Was seconds away from posting this too. Basically, we have a situation where
logic voltage is approaching Silicon's threshold voltage of 0.7.

With logic operating at such low voltage, the current you have to supply to
the die is very high even in "low power" chips, and you begin suffering
significant copper losses over single millimetres.

If you can put a DC-DC converter on the chip itself, that problem is solved.

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wahern
Haswell had an on-die, integrated voltage regulator. I guess it didn't work as
well as expected because they removed it in Broadwell.

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chapplap
It was removed in Skylake, not Broadwell. Ice Lake reintroduces the FIVR
again. The inductors are now in the package substrate (rather than discrete
inductors on the package or the weird 3DL module in Broadwell-Y) and
efficiency at low power is improved. The latter is obviously extremely
important for mobile workloads.

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sitkack
Do you see integrated super caps or batteries into the package or die at some
point?

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satya71
Backside processing is standard in the CMOS image sensor industry. Turns out
all the metal on the front-side makes it very difficult to get light down to
the silicon where the actual photon-electron transduction takes place.
Backside imagine (BSI) has been standard for quite a few years.

Wafer thinning is used extensively in stacked-die products which have become
common in recent years.

This looks like an incremental change applying the tech from image
sensor/memory technology to standard silicon. Although, I'm not sure why they
chose ruthenium.

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hristov
BSI is very simple compared to what they are proposing here. BSI illumination
does not require that any features are actually built into the backside. It
basically just requires that the backside be polished very nicely.

Here we are talking about building elements on the backside and then
connecting them to the front side. It is much trickier.

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satya71
That's not entirely true. BSI always had some metallization on the backside
for aperture, power and packaging. For example, see this: [https://image-
sensors-world.blogspot.com/2018/03/techinsight...](https://image-sensors-
world.blogspot.com/2018/03/techinsights-publishes-samsung-09um.html)

Perhaps what they're proposing is more sophisticated, but definitely not
something entirely new.

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rayiner
This is crazy:

> The only trade-off is the complexity of manufacturing the backside network,
> Prasad noted. To make it, the frontside of the wafer must be fully
> processed, including the construction of the buried power rails. The wafer
> is then flipped over, and the silicon is removed down to a mere 500
> nanometers thickness. Then vertical connections less than 1 micrometer
> across, called micro-through-silicon vias (microTSVs), were built to contact
> the buried power rails.

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baybal2
Making double sided chips, and TSVs on them are nothing new. Been tried in the
past and didn't take off.

Even without costs of TSVs, a double sided wafer costs twice the normal one,
while you can at most squeeze like 20-30% more things onto it, given that the
backside will only be usable for lower tier logic or analogue process.

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Dylan16807
> Even without costs of TSVs, a double sided wafer costs twice the normal one

If you ignore the TSVs the back of the wafer has zero circuitry constructed on
it.

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baybal2
Well, as I catch the idea, they do want to put a DC-DC on the back side

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Dylan16807
They may want to, but they can trivially choose not to if it makes things too
expensive. So 'double cost' will not be a problem.

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tomxor
At most this looks to provide a linear performance improvement on each
iteration (if it's not a one off improvement - which it looks to be).

Moors law implies exponential improvement up to the the physical limits we hit
over the last decade on each process shrinkage (this is also explicitly
defined in Moore's paper) i.e Dennard scaling, this is possible because
roughly speaking when you shrink the process, you reduce latency (allowing
faster clock with the same design or new larger design i.e double transistors
with same max straight line latency) without increasing power consumption or
_absolute_ heat dissipation requirements - it's almost "free" if you can keep
shrinking it which is why you get exponential improvement if you can keep
halving.

Media have completely watered down the term into a flowery synonym for
"somehow improve".

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drcross
Let's not split hairs, Moore's law is the doubling of transistor count in the
same size every 18 months.

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Filligree
Which we recently have only managed by shrinking the wires, packing the
transistors tighter, increasing the die size, changing transistor shape or
doing _anything_ but actually shrink the transistors.

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zozbot234
You don't _want_ to shrink the transistors because that increases static
leakage, other things being equal. With dark silicon becoming more important,
you actually want bigger devices that can minimize that, and use charge-
recovery logic to conserve dynamic power as well. Only stuff that's _very_
infrequently powered up can be built naïvely, the way it would be absent dark
silicon constraints.

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baybal2
You can shrink it even further, no questions, and we possibly go there once
HfO process will advance to the point when you can bury everything in it.

There are many ways forward, I'd say even too much of them. Too many people
are trumpeting "the death of silicon" or CMOS, and too many people are
focusing on "revolutionary" solutions

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ncmncm
Doesn't look like this is ARM's project, but imec's. They just used an ARM for
their demonstrator. Could just as well have been a MIPS, except imec is
probably well committed to ARM designs.

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danellis
When did ARM become Arm? It's like that on their own site, too.

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mrkstu
UK's grammar rules differ from the United States- they don't capitalize
acronyms. i.e. NASA becomes Nasa.

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danellis
I can't say that I've ever noticed that to be _generally_ true, but I'll
certainly be looking out for it now.

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skyyler
The only time Brits capitalise the entire acronym is if we are worried about
confusing Americans.

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taneq
Which is always, is it not?

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skyyler
Almost never, actually.

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stevespang
ruthenium is only $8K per kg.

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Dylan16807
That sounds sarcastic? But a kg is a ridiculous number of chips.

Let's look at a very big chip, 3cm a side. Once you thin it to 500nm, the
volume is .45 cubic millimeters. Since Ruthenium has a density of 12.2, it
would take 5.5 milligrams to make a version of the chip that was solid
Ruthenium all the way through. That's 4.4 cents.

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aasasd
> _Backside Power Delivery_

So they're saying some stimulation applied in a proper place gets things going
faster?

