
Xerox Alto's 3 Mb/s Ethernet: Building a Gateway with a BeagleBone - jf
http://www.righto.com/2018/01/xerox-altos-3-mbs-ethernet-building.html
======
DannyB2
BYTE magazine, April 1980, page 115.

NEW HIGH-SPEED COMMUNICATIONS BUS: Xerox Corporation recently made a public
announcement of a new concept of processor-to-processor communications
intended for an office environment. This novel concept is called "Ethernet",
and is a result of some of the work being done in their research labs. In this
concept, a single coaxial cable is used as a high-speed communications bus
between all processors; communication protocol is handled through software or
software supplemented by special-purpose hardware. Rumor has it that an
Ethernet processor is now being developed by some form of joint arrangement
between Xerox and Intel.

[http://www.americanradiohistory.com/Byte_Magazine.htm](http://www.americanradiohistory.com/Byte_Magazine.htm)

[https://archive.org/details/byte-magazine](https://archive.org/details/byte-
magazine)

~~~
ghostly_s
I've never considered networking as "processor-to-processor communications"
before. Kind of an interesting angle.

~~~
teh_klev
The usage likely originates from the use of the word "processor" to mean a
whole machine that does some kind of "processing", kinda like the IMP's
(Interface Message Processor) on the early ARPANET. These days "processor"
usually means a more narrow definition, i.e. just the CPU, rather than a whole
machine.

~~~
DannyB2
Ah, but once upon a time,

Long ago, in a galaxy far, far away,

CPU meant a large metal enclosure with circuit boards, main memory, power
supplies and cooling. Oh, and blinking lights. Don't forget the blinking
lights like REAL computers on TV.

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rootbear
Here at NASA Goddard, old wiring is often never removed. In the cable trays in
the hall outside my office is some ancient coaxial Ethernet cable. At one
point, there is a tap and one of the standard cables that went from the tap to
a workstation. I keep thinking I should grab the tap and squirrel it away as a
historical artifact.

~~~
mhalle
Vampire tap. You had to place them at marked locations on the coax because of
signal reflections.

~~~
jacquesm
And because at that point the shield wires were spaced further apart so as not
to short out the connection.

~~~
jonsen
Really? Sounds like a major complication to the cable manufacturing process.
Wouldn't all those holes in the shielding hose degrade cable specs? All for
not having to drill a hole for the eventual connecting tap.

~~~
jacquesm
It is not that big a deal actually, either you drill a hole with a special
tool and then align the tap with the center of the hole or, on some cable you
align the tap with a special dot mark on the cable where the shield has been
moved aside a couple of mm. It is a convenience at the slight cost of some
loss. Far faster to connect to than drilling holes in insulation using yet
another tool.

It really adds up if you have to make a lot of drops on a cable.

If there is one thing I am happy about then about then it is that we no longer
have coax networks. Nightmare stuff. Flaky connections and weird voodoo
problems.

~~~
teh_klev
> If there is one thing I am happy about then about then it is that we no
> longer have coax networks

I used to install 10BASE2 and 10BASE5 infrastructure back in the late 80's and
into the late 90's. I hated having to install 10BASE5 vampire taps for fear of
completely buggering up what were already creaky 10BASE5 networks where the
2.5m rule was widely flaunted by on-site staff.

I remember a job at a factory in Manchester where I had to install a bunch of
kit on a 10BASE2 installation. The customer insisted on running their own
cables and swore blind they knew what they were doing and had done their
previous install etc. When I arrived I discovered the coax had been installed
in a star config :/

Yes good riddance to coax bus networks.

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godzillabrennus
Fascinating to learn that the Ethernet design of the Alto influenced the
design of TCP.

This might be common knowledge to those who lived through that era but as a
millennial I wasn’t aware of this.

~~~
kens
The story is that the PARC engineers went to the TCP design meetings, but
Xerox lawyers wouldn't let them say anything about Pup. So the PARC engineers
would just ask questions until the TCP designers realized the flaws in their
proposals: "Have you considered what would happen if..." And the TCP designers
would go, "Hey! You've done this before, haven't you!"

~~~
vvanders
That's both an awesome anecdote and a great way to approach any design review.

If you can take the time it's a great way provide technical feedback in a way
that isn't hostile and keeps an open dialog.

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jonsen
How did we make a similar adaptor in the 80'ies with a microprocessor running
2 MHz? Fortunately the PLA was invented. A few bits of memory and a little
programmable logic. Enough to synchronize to the, in this case 2.35 MHz,
Manchester coded bitstream and assemble the data bits into bytes. The
processor was still not fast enough to handle the control bytes of the data
stream in real time. It could actually handle the controlling logic, but then
it had no time left for looping around. The trick was then to disable the
processors address bus during program fetching and feed it instructions from a
separate ROM, controlled by another small PLA which also handled the looping.

~~~
bsder
While I love this (and I am _ECSTATIC_ about the PRU documentation ...
thankyouthankyouthankyouthankyouthankyouthankyouthankyou ... I have been using
this _right now_ ), I would expect this would have been loads easier with even
something really cheap like a MAX10 FPGA.

However, he does mention needing a network stack, so maybe not.

~~~
sigstoat
> I would expect this would have been loads easier with even something really
> cheap like a MAX10 FPGA.

basically nothing is easier with an FPGA. faster, perhaps.

~~~
bsder
If I can draw a handful of gates, an FPGA eval board is almost _ALWAYS_
easier.

I can have a MAX10 evaluation board on my desk in less than 24 hours for
probably less than Osh Park charged him.

The real question is how much software is required. Once I have to start
writing software or Verilog/VHDL, things slow down.

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binhex
I love these types of posts. There is something really interesting about the
detective work required to be able to talk to old devices like this.

~~~
chrisweekly
Agreed!

Meta for admins: shouldn't the headline include the year? (I've got comment
downvote rights per karma > 500, but can't edit post headlines.)

~~~
kens
Why would the headline include the year? The article is from 2018.

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thought_alarm
What makes ethernet "Ethernet"?

There's 10BASE-T Ethernet, which is what we all use and has been around since
the late 80s.

There's 10BASE5 and 10BASE2 Ethernet, which uses a shared coax cable between
machines and was around from the early-80s to the mid-90s.

And then there's the pre-standard coax Ethernet that the Alto used in the
1970s.

Is there a common technological thread between these three things, other than
the name?

~~~
fernly
I think the common thread is multiple sender/receivers on a single shared
conductor using csma/cd.

[https://en.wikipedia.org/wiki/Carrier-
sense_multiple_access_...](https://en.wikipedia.org/wiki/Carrier-
sense_multiple_access_with_collision_detection)

~~~
tyingq
See token ring for shared conductor, but different coordination.[1]. There was
a time when it wasn't clear which one would win out.

[1]
[https://en.m.wikipedia.org/wiki/Token_ring](https://en.m.wikipedia.org/wiki/Token_ring)

Edit: Also DecNet, SNA, Arcnet if you want some more view into competing ideas
in the same time period.

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dfox
What is inside the Alto's ethernet transceiver?

From the remark that interface between Alto and transceiver is TTL I gather
that it is not same as 10M one (which transformer-coupled RS-422-ish
differential interface) and also the collision signal detected by transceiver
should probably be different.

~~~
kens
The transceiver basically has three parts. There's the logic side connected to
the Alto, which XORs the sent data and received data to see if there's a
collision. The cable-side circuitry has some analog stuff to put signals in
and out of the coax. These two sides are connected via transformers for
isolation. Finally there's a simple switching power supply to provide isolated
5.7V to the cable-side circuitry. (You want the Alto electrically isolated
from the cable so you don't get ground loops and other nasty stuff from the
cable.)

The schematic for the transceiver is at:
[http://bitsavers.org/pdf/xerox/alto/schematics/209926B_Ether...](http://bitsavers.org/pdf/xerox/alto/schematics/209926B_Ethernet_Transceiver.pdf)

~~~
CamperBob2
Interesting, I wonder what the funky magnetically-coupled circuit with Q1 and
Q2 is for.

~~~
dfox
That is the aforementioned switching power supply.

On the other hand what I see as more funky is IC1 and IC02, what exactly is
that? Some kind of gated comparator? (Also of note is how IC3A and B has
different, but equivalent, logic symbol to IC3C and D)

~~~
kens
IC1 is a 75140 dual line receiver, where pin 6 is a reference and pin 2 is a
strobe, so pretty much what you thought.

Also of interest is IC101, a 75122 triple line receiver, which has a Schmitt
trigger, two AND gates and a NOR for each line. Most of the pins are tied to
ground (1, 2, 3, 4, 12) so it's used as a buffer, ignoring the rest of the
logic.

For IC3A-D, I think what's going on with the symbols is a briefly-popular way
of representing positive logic and negative logic by changing the symbols so a
wire has bubbles on both ends. In other words, if you have active-high inputs,
represent it as a NAND gate, but if you have active low inputs, represent it
as an OR gate with inverters on the inputs. It's the same gate, just drawn to
indicate if it's performing an AND or OR. Note the way the bubbles move on the
inverters too.

~~~
bsder
Well, IC3A and IC3B are just functioning as inverters ...

The thing with the bubbles is probably an old technique that we used to use
called "pushing circles".

You can shove all the circles on one side of a logic gate to the other side of
the logic gate by exchanging the gate type (AND->OR, OR->AND).

And then you can ignore lines with two bubbles in series (ie. a double
inversion).

There are a bunch of tricks that we used to use when you had to do everything
on graph paper. It's actually a _good_ thing that they are lost to the mists
of time as it means we have progressed enough that they don't matter anymore.

~~~
thrownhwn
Cool, had to Google bubble pushing[1]

[1]
[http://district.bluegrass.kctcs.edu/kevin.dunn/files/Simplif...](http://district.bluegrass.kctcs.edu/kevin.dunn/files/Simplification/mobile_pages/4_Simplification10.html)

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kevin_thibedeau
> using a 74AHCT125 level shifter chip

The 74x125 is not a level shifter. It is a tristate buffer that can be
exploited for poor-man's level shifting with a suitable configuration of
external components. It isn't an ideal part to do this and it would be nice if
the purveyors of hacker/maker doodads didn't misrepresent what they're
selling.

> Without a resistor, the open-collector signal stayed at ground. Adding the
> resistors to my circuit fixed that problem.

That never would have been an issue with an actual level shifter.

~~~
stn8188
While you're technically correct, Nexperia outlines the technique for using
the 74AHC series for level shifting here:
[https://assets.nexperia.com/documents/brochure/75017511.pdf](https://assets.nexperia.com/documents/brochure/75017511.pdf).

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stevefan1999
this is so cool and nostalgic!

