
The Hierarchical Asynchronous Circuit Kompiler Toolkit (HACKT) - ch
http://www.csl.cornell.edu/~fang/hackt/
======
nickpsecurity
Achronix is my favorite among the FPGA companies due to use of asynchronous
logic. Got me doing research on the topic. Here are some of the first things I
found:

[https://www.schneier.com/blog/archives/2015/07/friday_squid_...](https://www.schneier.com/blog/archives/2015/07/friday_squid_bl_488.html#c6702018)

Asynch design flow at 250nm
[http://async.usc.edu/pubs/MF_ASYNC04.pdf](http://async.usc.edu/pubs/MF_ASYNC04.pdf)

65nm standard cell library for async
[http://www.inf.pucrs.br/~calazans/publications/2013_SIM_asce...](http://www.inf.pucrs.br/~calazans/publications/2013_SIM_ascend.pdf)

That one partly uses Null Convention Logic by Theseus
[http://www.theseusresearch.com/NullConventionLogic.htm](http://www.theseusresearch.com/NullConventionLogic.htm)

The very interesting AASP chip
[https://www.wikiwand.com/en/Asynchronous_array_of_simple_pro...](https://www.wikiwand.com/en/Asynchronous_array_of_simple_processors#/AsAP_2_chip:_167_processors)

I kept pushing both asynchronous and analog circuits for neural networks as
they fit them better. I know one startup is doing mixed digital and analog for
it. Not sure if asynch is getting much attention outside of memory. Anyway,
readers jump on it as asynch should be easiest accelerator tech for VLSI
ANN's.

Regardless, hope readers have fun with the links. :)

