
Show HN: Architect – Hardware Description and Emulation JavaScript Library - mbad0la
https://github.com/mbad0la/Architect
======
TD-Linux
For reference, the 4-input AND gate from the third example in Verilog:

    
    
      module ForInpAndGate(a,b,c,d,o);
        input wire a,b,c,d;
        output reg o;
        always @(*) begin
          o <= a & b & c & d;
        end;
      endmodule;

~~~
voltagex_
I'm not sure why the output is passed in at the start (I'm guessing it's like
an out parameter in C#) and I don't understand what @(*) is, but that's
surprisingly readable.

~~~
blackguardx
Verilog isn't a programming language. It is a hardware description language.
It is used to describe the behavior of hardware. The output isn't "passed" out
at the beginning. Rather, That line is indicates that there is an output and
what it's name is. The @() indicates a sensitivity list. The block below is
evaluated whenever the states of any signal in the sensitivity list are
changed. The * is a wildcard character and signifies any signal in the block
below. That feature was added in Verilog2001. Before that, you had to manually
list any signal you wanted in the sensitivity list.

~~~
e19293001
> Verilog isn't a programming language. It is a hardware description language.
> It is used to describe the behavior of hardware.

In short, coding in verilog is like creating a schematic of the circuit.

~~~
krupan
You can write Verilog as schematic-like description, but there is a higher-
level of modeling supported by synthesis tools that doesn't look quite so
netlist like.

------
clusmore
This may be confirmation bias but I feel like since the Megaprocessor
thread[1] I'm noticing an increase in hardware-simulation related posts. Can't
think of them all off the top of my head, but see also:

* Nand2Tetris[2]

[1]
[https://news.ycombinator.com/item?id=12317217](https://news.ycombinator.com/item?id=12317217)

[2]
[https://news.ycombinator.com/item?id=5888705](https://news.ycombinator.com/item?id=5888705)

~~~
mbad0la
Oh these were great!

I didn't know about them though. My project's inspiration is due to the fact
that I love JS and had a computer system architecture course wherein I learnt
VHDL.

I felt that the NodeJS Events API could probably help me simulate a `signal`
driven system and thus, I started experimenting :)

~~~
aceperry
Since nodejs is single threaded, you'll get the best results with synchronous
logic. Even asynchronous systems are difficult to design in real life, so it's
not a bad idea to use nodejs.

~~~
mbad0la
Yeah, using events do offer an amazing async behaviour.

Thus,the I/O arguments of every hardware component are extensions to
EventEmitter, resulting in quite an amazing simulation.

------
aceperry
Looks like a cool project. And since it's based on javascript, it shouldn't be
too difficult to add a graphical interface, so the system could be driven
primarily by graphics instead of using text only. A graphical interface would
vastly improve on productivity and open up hardware design to more than just
hardware engineers. Heck, this might give FPGAs a boost in popularity.

~~~
mbad0la
Couldn't agree more! Someone has already suggested me some cool libraries that
I might be able to use. Visualisation is on the agenda definitely.

