
Bipolar-Zener Combo Takes On CMOS - baybal2
https://www.eetimes.com/document.asp?doc_id=1335216
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zw123456
Interesting, here is another link with some additional interesting points:
[https://www.electronicsweekly.com/news/design/tunnelling-
tra...](https://www.electronicsweekly.com/news/design/tunnelling-transistor-
offers-logic-power-easy-make-ic-2019-10/)

What caught my eye was this tidbit.... "Analogue computing The last trick up
SFN’s sleeve is Bizen analogue blocks – op-amps and comparators (in the PDK),
and even analogue computing blocks such as a divider – the analogue computing
blocks avoiding using logic – and thus the associated ADC and DAC – in certain
applications. Using a coarse-fine architecture, Summerland is predicting 1μW
1μs analogue division instead of ~20 instructions and ~100 instruction cycles
if logic was employed. This analogue processing capability is being branded
IPU for ‘instantaneous processing unit’."

Analog computers making a comeback ? you never know.

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gumby
> Analog computers making a comeback ? you never know.

Analogue processing may be a superior alternative to GPGPU for implementing
neural networks.

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zozbot234
I dispute this. The problem with analogue processing (besides noise, of
course) is that the dynamic range sucks compared to plain old floating point.
Fine for inference, not for training. And most of the compute power in NN is
spent on training, inference is trivial.

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emmelaich
Analogue processing has certainly been successful for people, so I wouldn't be
too dismissive.

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krastanov
I would not be certain of the premise in your statement. We do not understand
the brain well enough to say whether error correction (which is inherently
digital) is utilized. There are some pretty solid clues that some of the
processing in the brain is not analog (e.g. the step-like behavior of the
activation function of biological neurons).

And coming from the other side: If it turns out that the brain is actually an
analog computer without anything that can be rephrased as some form of sloppy
noisy approximately-digital error correction, this would be __incredibly
__important discovery, completely changing our understanding of theoretical
computer science and complexity theory. P-vs-NP or the eventual creation of
quantum computers would pale in comparison to the impact of discovering
scalable analog computers.

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emmelaich
Agree mostly, except for "error correction .. inherently digital"

For an example of an analogue error corrector, see
[https://en.wikipedia.org/wiki/Centrifugal_governor](https://en.wikipedia.org/wiki/Centrifugal_governor)

PS. cool fact; "governor" has the same etymology as kubernetes.

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ChuckMcM
Pretty cool, I think the rub will be how well they can control the PN boundary
and hence the switching thresholds.

The simpler NOR gate was pretty cool too, so their next step should be to
build a RAM chip (either a 2 gate equivalent dynamic cell or 4 gate equivalent
static cells) If they can do that, then they can show that the process can be
controlled well enough for reliable gate fabrication.

Then the step after that might be mixed mode analog/digital circuit paths.
Process control gets even harder when you're doing analog as non-linearity
propagates and you can't ever get rid of it.

A typical zener[1] has a variance of >100mV for its breakdown voltage. The
"easy" analog circuits in my radio need better than 40 dB of dynamic range
which is more like 1 mV so 100 times better than a zener. I'll have to read up
more on the device physics to see if getting that level of precision or better
is really practical.

[1]
[http://www.vishay.com/docs/84830/plzseries.pdf](http://www.vishay.com/docs/84830/plzseries.pdf)

~~~
magicalhippo
> A typical zener[1] has a variance of >100mV for its breakdown voltage.

My interpretation was that that was the point of the substrate biasing:

"A second tunnelling junction, represented by two horizontal lines in the
device diagram, biases the device so that it is ‘on’ (but not saturated) when
the tunnel terminal is open-circuit. While this represents a continuous
current flow to ground during operation, tunnel current is typically only
2-5nA [...]"

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fouric
The static power dissipation might be a problem, depending on its magnitude,
and would only be exacerbated by the increased density. On the other hand, the
increased density allows for lower latency relative to CMOS, and latency
improvements are hard to come by.

~~~
adammunich
These are insulated gate transistors so you don't need base current. It might
not be too bad actually.

~~~
markrages
If it is Zener-ing, there is some base current, no?

The article says there is "some" static power requirement... that sounds like
base current to me.

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magnat
What's the likelyhood that Intel, TSMC or some other fab company already
stumbled upon the process in r&d and binned (hehe) it due to some unforeseen
difficulties making it not worth investing?

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robocat
What is "plasma metal edge" and "wet edge metal"?

The article is a unique usage of these words in that order...

Edit: generally the article feels a bit like word salad for April fools
(however, I only have an undergraduate EE knowledge of transistor design, so
there's a lot I don't understand in there).

Edit 2: if it were a good chance to become a breakthrough tech, why is it
missing deep VC level funding to get it to market? I know it's not software,
but neither is it limited by FDA regulations!

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baybal2
It is how you etch the metal-device contact. Using liquid or plasma.

Plasma etch is more expensive and slower, but is easier to control.

> Edit 2:

Electronics is not in vogue with those people. Just like in computer science,
the few breakthroughs that matter in last few decades went by nearly
completely anonymous despite their enormous utility, but every cat video
website gets... you know.

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satya71
This looks interesting, but it's very early days. No mention of reliability,
variation, interconnect (modern CMOS processes have 8-10 layers of
interconnect). Certainly not taking on CMOS anytime soon.

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hthtegr
Does the quantum tunneling have a lower limit on node size?

This is being developed it seems to keep a 1um fab competitive, but does it
also apply to smaller nodes?

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m0xte
It’s got a terrible reputation on repeatability on a process. One reason
tunnel diodes never went anywhere. They were expensive, tetchy and unreliable!

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dfox
There was one big application for tunnel diodes: fast comparators. IIRC many
classic Tek scopes use tunnel diode based comparator in their trigger
circuitry.

On the other hand doing the same thing in some modern bipolar process is
significantly cheaper and more reliable.

Another thing is that in such designs the tunnel diode looks like it does
nothing. And that may have something to do with most engineers not using it.

~~~
m0xte
Exactly. I actually have few ex Tektronix trigger tunnel diodes here[1].
Repairing the infernal scopes was a hobby of mine until I got fed up of it. By
the mid-80s we had cheap ECL comparators which were much faster, required no
bias calibration and lasted a lot longer.

[1] [https://imgur.com/5ijmSh8](https://imgur.com/5ijmSh8)

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adammunich
This is absolutely incredible, I can't wait to see what foundries adopt the
process.

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campfireveteran
_EEVblog (Dave) entered the chat_

hope he makes a video about this development.

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zwieback
Is there a problem with charge, like in MOSFETs?

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mannykannot
Is this what you are thinking of? "Bizen also does not suffer from CMOS’
electrostatic discharge (ESD) susceptibility and latch-up problems."

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tawm
I think the question is about gate charge.

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amelius
And I guess gate capacitance may cause signal-delays.

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magicalhippo
Not just delays. Being able to drive a transistor fast can be important for
reducing power dissipation. That is, for switching one wants the transistor to
spend the least amount of time in the non-saturated (linear) region where it
acts as a resistor.

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Ballas
Judging by the process size quoted in the article, they won't be chasing
speed, but rather low-cost devices.

