
Skyscraper-style chip design boosts electronic performance - ingve
http://news.stanford.edu/news/2015/december/n3xt-computing-structure-120915.html
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gjm11
> suburban-style layouts create long commutes and regular traffic jams in
> electronic circuits

> millions of "vias," which play the role of tiny electronic elevators

Is it unreasonable to suggest that maybe there is such a thing as trying _too
hard_ to avoid scaring people with technicalities?

I mean, I get it, they made a neat skyscraper-versus-suburban analogy. Fair
enough. But why not "just as suburban layouts in cities can mean long commutes
and regular traffic jams, suburban layouts in chips can mean signals take
longer to get from one place to another" or something?

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Frenchgeek
I only skimmed the thing a bit, but how do they deal with heat exactly? Water
cooling at every level?

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jacquesm
FTFA:

"Just as skyscrapers have ventilation systems, N3XT high-rise chip designs
incorporate thermal cooling layers. This work, led by Stanford mechanical
engineers Kenneth Goodson and Mehdi Asheghi, ensures that the heat rising from
the stacked layers of electronics does not degrade overall system
performance."

Paper about that:

[https://www.researchgate.net/publication/263004944_Phonon_sc...](https://www.researchgate.net/publication/263004944_Phonon_scattering_in_strained_transition_layers_for_GaN_heteroepitaxy)

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mhb
Since these are stacked solid layers, heat isn't really "rising" though, is
it?

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Zardoz84
Not was AMD doing something similar ?

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nhaehnle
Yes indeed, the HBM memory in the latest AMD GPUs is stacked.

This press release is extremely frustrating, by the way, because it's full of
fluff and hype. Through-silicon vias have been in discussion for a long time
(and, as you said, are even in production already). Apparently, this team uses
different materials (carbon nano-tubes). This is potentially interesting, but
I'm very sceptical. Certainly, any claim of "factors of thousands" is just
ridiculous. Wires are a significant part of delays on chips, but having
shorter interconnects isn't going to speed up the switching time of
transistors, which would become a bottleneck again.

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chrsw
The industry has been abuzz about these types of structures for years. It
would be interesting to see if this is practical at scale: making millions of
these types of chips per month with a high yield.

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petra
I think 3D-nand can be considered a practical use of such structures.

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illumen
System on a chip is already able to achieve much of this. Without having to
completely retool. It's not impossible to combine memory with CPU and GPU on
one chip. This is one way in which computers have been getting smaller and
have been using less resources.

I imagine this will still be useful though.

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kingosticks
CNT (carbon nanotube transistor) is an unfortunate acronym. I can't imagine
explaining that to my Mother.

