
Western Digital Plans to Ship More Than One Billion RISC-V Cores a Year - deepnotderp
https://www.wdc.com/about-wd/newsroom/press-room/2017-11-28-western-digital-to-accelerate-the-future-of-next-generation-computing-architectures-for-big-data-and-fast-data-environments.html
======
asb
If you're interested in what's going on at the RISC-V Workshop, you might want
to follow my live blog here: [http://www.lowrisc.org/blog/2017/11/seventh-
risc-v-workshop-...](http://www.lowrisc.org/blog/2017/11/seventh-risc-v-
workshop-day-one/)

~~~
madez
Let me thank you for providing the excellent write-up. I eagerly wait for news
from lowRISC in hope for a SBC with general purpose Linux support. This would
open up the hardware in general, and thus be a major step in a good direction.

I do have a question, though. Is there any plan for working on an architecture
for massively parallelizable workloads, like graphics, artifical neural
networks and simulations? Especially the talk by Dave Ditzel seems relevant to
this. Even without competitive performance, that would be another major step.
It would not only improve the situation by the amount of the necessary efforts
for that, but by raising the bar for all the other vendors by being compared
to that.

There is a factor between your work and the impact on the ecosystem, and I
guess it is significantly higher than one.

------
csense
From the headline, I would guess WD is putting a user accessible CPU in each
of their disk drives, idea being that if you have a CPU living close to the
drive, then e.g. map+reduce workloads can be more efficiently executed.
Instead of going with ARM or Intel, I guess the CPU's are using some less
famous architecture called RISC-V.

Then I read the article, and the article is so full of buzzwords and
genericisms that after reading the whole thing, I don't know if this guess is
correct.

~~~
Symmetry
In order to move the reader head inside your drive and to communicate with the
host CPU you need microprocessors in your hard driver, really tiny ones. Now,
instead of paying ARM for licences to use them WD is using open source
processors that don't come with fees besides what it takes to manufacture
them.

~~~
tyingq
This is the right answer...they already use ARM, they want a one-time-fee
license instead of royalties. Trying to shave a little margin.

~~~
_chris_
WD made it clear in there talk that this wasn't about saving on costs, but
rather having control over the innovation in the data space.

I don't see any reason to doubt them. It's an incredible risk to switch their
entire company over to a still-growing ISA. But being able to design and
modify any particular core as they see fit without having to talk to lawyers
or negotiate a new contract... that's an incredible power.

~~~
sliverstorm
RISC-V is certainly more unencumbered, but there's always the ARM architecture
license too. Pricey, but you can modify and build on a relatively more mature
ISA

~~~
asb
An architectural license doesn't give you free reign to extend the ISA, just
to create your own implementation of the standard ISA.

------
jstewartmobile
I guess this will be nice for industry, which may pass the savings along to
the consumer, but as far as having auditable hardware that you have some
control over, I don't see how this is any better than the ARM SoCs we already
have--unless you're going to roll your own system on an FPGA.

That, and I'm kind of disappointed everyone has drunk the RISC kool-aid. I
think a lot of RISC "performance" has more to do with compilers catering to
the least common denominator than anything else. If you had a
language/compiler that took better advantage of a stack architecture, or even
a CISC architecture, the performance would probably be just as good if not
better.

I was particularly impressed by Baker's old paper[0] on stack architectures in
service of his _Linear Lisp_ idea.

[0]
[http://home.pipeline.com/~hbaker1/ForthStack.html](http://home.pipeline.com/~hbaker1/ForthStack.html)

~~~
pkaye
RISC-V benefits is mostly an open source license that is free of patents. I
think the biggest reason for it is academic... there needs to be an open
platform for academic research. I'm sure it is next to impossible for an
average university to do that on ARM or x86 architecture.

~~~
nabla9
RISC-V is just ISA. I don't think ISA's can be patented. Just some specific
instructions.

~~~
kindfellow92
ISAs can be patented. Intel is patenting their latest AVX/SSE instructions.

~~~
hajile
ISA spec is copyrighted. Instructions aren't patented directly. Instead, the
best ways of implementing them are patented.

~~~
kindfellow92
Seems like Microsoft is potentially being targeted for writing an x86 emulator
[https://newsroom.intel.com/editorials/x86-approaching-40-sti...](https://newsroom.intel.com/editorials/x86-approaching-40-still-
going-strong/?cid=em-
elq-27099&utm_source=elq&utm_medium=email&utm_campaign=27099&elq_cid=1494159)

------
sverige
I haven't been following the RISC-V story too closely, possibly because I
didn't want to get my hopes up only to be dashed. From the article, it sounds
like these cores will be developed solely for use in data storage. Can someone
with more knowledge tell whether this will help provide the kind of production
volume needed to make consumer products (like laptops and desktops) more
likely to be viable? Are general purpose chips likely to be one result of the
development of RISC-V, or have I missed something fundamental?

~~~
Symmetry
Probably we won't be seeing RISC-V application processors for quite a while.
There's a lot of stuff that can just be recompiled but there's also a lot of
hand-tuned assembly that goes into making a JIT or media codec fast. That's
why we're seeing initial adoption in the embedded space, where either there's
just a small amount of code to recompile or you were going to rewrite the
assembly anyways for the next product.

In the long run using RISC-V in a laptop is a possibility. And there might be
some limited production $2000 500MHz FOSS laptop soonish. But in 15 years,
say, I could see RISC-V being where ARM is now.

~~~
sitkack
You can already run Debian [0] RISCV.

[0] [https://wiki.debian.org/RISC-V](https://wiki.debian.org/RISC-V)

[https://github.com/riscv/riscv-linux](https://github.com/riscv/riscv-linux)

------
microcolonel
I think the level of industry enthusiasm for RISC-V is so palpable, in part,
because the messaging from day one has been unequivocally: RISC-V will be
_the_ standard ISA for every form factor, in every market.

Can't wait to put a RISC-V SBC in my ThinkPad X220 chassis. :- )

~~~
anderspitman
I'm so excited that we're feasibly within a year or two of being able to
develop embedded devices in Rust[0] on RISC-V microcontrollers [1] running on
open source RTOSes also written in Rust[2]. It's currently already possible
but still requires quite a bit of hacking. Plus the RF stacks (Bluetooth in
particular) aren't there yet. What a time to be a developer. PS RISC-V on my
X220 wouldn't hurt either.

[0] [http://blog.japaric.io/quickstart/](http://blog.japaric.io/quickstart/)

[1]
[https://www.sifive.com/products/hifive1/](https://www.sifive.com/products/hifive1/)

[2] [https://www.tockos.org/](https://www.tockos.org/)

~~~
microcolonel
> _I 'm so excited that we're feasibly within a year or two of being able to
> develop embedded devices in Rust[0] on RISC-V microcontrollers_

I'm happy to report that the future is yesterday![0][1] (sort of)

> _Plus the RF stacks (Bluetooth in particular) aren 't there yet._

Espressif is a RISC-V foundation member, and you know what that means. (hint:
it rhymes with _could-pie den-sill-hiccup_ )† :- )

[0]: [https://abopen.com/news/rust-comes-
risc-v/](https://abopen.com/news/rust-comes-risc-v/) [1]:
[https://github.com/dvc94ch/hifive](https://github.com/dvc94ch/hifive)

† «Goodbye Tensilica» (sorry Tensilica, I have nothing against you!)

~~~
anderspitman
Very nice. I actually hadn't realized Tensilica wasn't an Espressif
technology. That would definitely be sweet if they switched to RISC-V

------
rijoja
Well what I find interesting here is if they are able to manufacture chips
with 7nm litography. Aren't intel and samsung who I belive to be the leaders
in the field, still at 14 nm? In case WD manages to beat them to the market
with this technology at least there will be a lot of hype around this.

As far as binary compability is concerned this is more or less a thing of the
past. The way I see it js and other interpreted languages provide for the most
vibrant ecosystem at the moment. Where we have package management running not
over only kernels but also distributions.

Before this developers have gotten really acustomed to compiling into platform
independent bytecode. And even windows which in comparison with Linux has been
ported to few platforms is by no means impossible to move over to a new
instruction set. As have been demonstrated multiple times. Even C itself was
developed to make few assumptions in regards to the metal. If you please,
excuse me for reiterating facts well known to the average HN reader.

Furthermore with developers more or less requiring to work with open source
software as it makes debugging and making use of other developers experiences
easier. The probability that you will be stuck with CPU specific binaries of
any given program is slim.

Now the problem is "only" to find programmers capable of programming 4096 CPU
cores to operate well simultaneously, in a world where it's completely
accepted and right, for a text editor to eat up hundreds of megabytes of ram
displaying the source code for a hello world program. Also for this to truly
make a dent the development has to span all the way from the metal via the
kernel and to the actual application.

Unfortunately I am afraid that the open license will mean very little, from a
freedom point of view as they take this route out of the pragmatic reasons,
briefly mentioned above, not to make an ideological stand. Nonetheless it's a
step forward so I'll try to supress my cynicism.

~~~
deepnotderp
"Well what I find interesting here is if they are able to manufacture chips
with 7nm litography. "

They're going to be using TSMC "7nm". At this point nm node names from anyone
mean absolutely nothing. Just know that TSMC "7nm" ~= Intel "10nm"

~~~
rijoja
Aha thank you for clearing that out.

------
erikj
So WD is switching their hardware to in-house designed processors after
purchasing a RISC-V developer, do I understand this press release correctly?

~~~
microcolonel
WD had already been a RISC-V foundation member before their involvement with
Esperanto Technologies (who has also been a member for a while). I suspect
they saw Esperanto's portfolio and team after meeting at one of the workshops,
and bought into it because of preexisting interest in RISC-V.

Just to be clear, I think they bought into Esperanto, but I don't think they
acquired it. Much public communication implies that Esperanto Technologies is
still generally autonomous[0][1].

[0]:
[https://twitter.com/rickbmerritt/status/935600820300713985](https://twitter.com/rickbmerritt/status/935600820300713985)

[1]:
[https://twitter.com/EsperantoTech/status/935598028773138432](https://twitter.com/EsperantoTech/status/935598028773138432)

------
ac29
Presentation slides: [http://innovation.wdc.com/downloads/RISC-V-
Presentation.pdf](http://innovation.wdc.com/downloads/RISC-V-Presentation.pdf)

Presentation brief slides: [http://innovation.wdc.com/downloads/RISC-V-
Presentation-Brie...](http://innovation.wdc.com/downloads/RISC-V-Presentation-
Brief-forWeb.pdf)

~~~
gbrown_
Talk about buzzword bingo.

~~~
eeZah7Ux
It's almost a parody.

------
technofiend
I haven't dug through all the marketing speak yet but this _seems_ like it's
tangentially related to WD's He8 converged servers they've been sampling,
which were ARM-based and ran Debian Jessie. [0] Although when I saw them spoke
about in Redhat Summit of course they were mooted to be running RHEL. It would
be interesting to see if WD Labs is now sampling RISC-V-based boards running
Redhat and Ceph OSD software which like the He8.

I found the whole concept of on-board PCB with dual gig ethernet ports
fascinating and I believe there's a second generation with faster network
speeds. Unfortunately WD never seem to have gone mainstream with it.

[0] [http://ceph.com/geen-categorie/500-osd-ceph-
cluster/](http://ceph.com/geen-categorie/500-osd-ceph-cluster/)

~~~
kijiki
I am similarly disappointed that this didn't go mainstream. At Cumulus we did
a follow up experiment to the one in your link, with the WD labs folks using
Cumulus Linux switches.

The idea was that you'd run the Ceph monitors on the switches, and the OSDs on
the hard drives, and you'd have an entire storage array with no servers
needed. Was very neat, but pointless unless you can buy the drives...

~~~
sitkack
WD could easily take on Intel and AMD for datacenter workloads if computation
starts moving to the drives. Drives have mass causing more Data Gravity. Data
Gravity is literally money.

------
H99189
I like the idea behind RISC-V's open architecture but I had a question. Does
it do or even try to do anything about the cloud of uncertainty surrounding
Intel ME and the AMD equivalent in x86?

~~~
pedroaraujo
RISC-V is not an architecture, it is just an instruction set. People still
need to design the architecture for an implementation of RISC-V.

Intel ME is a co-processor that runs at the same time as the main processor,
it is not related to the instruction set.

To answer your question: Intel ME is a problem that happens on an higher level
than the document that defines instruction set.

~~~
fulafel
There are "instruction set architecture" and "microarchitecture" (=specific
implementation of an ISA). ISA is the one more commonly referred to as just
architecture, I think.

------
sandGorgon
Does anyone know what is the state of the processor that they are proposing to
ship ? Has it already gone to GDS?

Or is this simply at proposal stage right now (mwani1the hardware is still RTL
or netlist).

------
tonmoy
This is so exciting, can’t wait for all the open source contributions to
RISC-V WD will make

~~~
phkahler
It is an interesting play. I didn't think WD would be all that relevant,
but... I figured with open ISA the CPU would no longer be a significant piece
of IP and competition and leadership would move to those with graphics IP.
OTOH if tightly coupled CPU and storage was to become a big thing then storage
companies would be the big winners (maybe just in some markets). But the fact
that they talk about contributing back is interesting. If companies with GFX
or storage want their specialty to become the real value, they will benefit by
contributing high quality IP to the open CPU movement thereby destroying the
market for the old guard (CPU makers).

------
dfee
A primer on the RISC vs CISC debate that helped me understand why this
matters:
[http://cs.stanford.edu/people/eroberts/courses/soco/projects...](http://cs.stanford.edu/people/eroberts/courses/soco/projects/2000-01/risc/risccisc/)

------
flamedoge
everybody makes processors!

------
nolanpro
"RISC" is a terrible name for anything related to computing

~~~
pavlov
Advanced RISC Machines (ARM) doesn't seem to have suffered from the
association.

------
Numberwang
I have not been following this, what are the advantages?

~~~
tw04
For you as an end-user? Nothing. For WD? They escape paying ARM licensing fees
on every drive. They'll see an extra couple points of margin on every hard
drive they sell.

------
0xFFC
This was what I exactly predicted one year ago. Risk-V ISA is coming for all
of them{x86,arm,mips}.

And this is very smart move by WD to jump into Risk-V wagon.

Update: Why do people downvote? I honestly don’t understand.

~~~
s-macke
Even though I see no reason to vote you down, there are a lot of reasons not
to vote you up.

The message from WD is very good news for RISC-V. But to make the claim that
it overthrows all other architectures from the throne is not only a bit
daring. With this logic, ARM should have crashed Intel a long time ago. There
will always be a market for different architectures.

You have also misspelled RISC-V, indicating that you are not really aware of
the market and architecture.

~~~
0xFFC
Did you read even my comment?

Where did i claim this?

>ut to make the claim that it overthrows all other architectures from the
throne is not only a bit daring

It is always fascinating how much people do extrapolate when the want to
believe something. It is _going to overthrow_ and it is _overthrown_ is two
quite different thing if you can think critically.

>You have also misspelled RISC-V, indicating that you are not really aware of
the market and architecture

Again. This just like you other analysis, which is based on flawed logic and
not being intelligent enough.

Rest assured I have wrote enough Chisel, and I would bet I am more familiar
about interenal of most architecture than most people in topic (since my grad
school work is focused on outputing chisel via LLVM).

One extra lesson for you: dont extrapolate and judge based on appearance. Look
at what they are saying deep down.

And don’t based your judgement on spelling, particularly in unofficial
context. Some people only have time to comment when they ar in bus or
something.

~~~
s-macke
I have tried to explain to you why your message might have been down voted.
Nothing else. If I interpret your message that way, others will do the same.

~~~
0xFFC
I know ( and i upvoted both of your comments)

No hard feelings ;) But i have a right to defend my comment.

~~~
AnimalMuppet
Free tip: If you don't want to be downvoted for your comment (#3) defending
your comment (#1), don't say in comment #3 about the person who wrote comment
#2 that their analysis was based on not being intelligent enough. That's a
personal attack, and is absolutely downvote-worthy.

------
milesf
I remember RISC's back in the late 80's/early 90's. CISC's bullied them away
and we've been stuck in Intel's quagmire every since. Anytime there's an
attack on the status quo, the established players feign concern and beat back
the attack then return to the way things were (remember Negroponte's $100
laptop and the netbook response?)

No idea how this will pan out.

~~~
astrodust
It wasn't that CISC won or that RISC lost, it was that the architectures got
so blurry you couldn't tell one from the other. There's so much microcode in a
CPU now that the instruction set is just the icing layer on the cake.
Internally there's surprising amounts of commonality between PowerPC, ARM and
x86 type chips.

Plus PowerPC started to adopt CISC-like instructions, x86-64 started to adopt
RISC-like features such as having a multitude of generic registers, and here
we are where nobody cares about the distinction.

Don't forget that while Intel won in certain markets, like notebooks, desktops
and servers, it's absolutely, utterly irrelevant in other places that ship
far, far more CPUs. A typical car may have as many as _one hundred_ CPUs of
various types, typically at least fifty, many of them PowerPC for power and
legacy reasons. Your phone is probably ARM. Remote controls. Routers.
Switches. Refrigerators. Thermostats. Televisions and displays. Hard drives.
Keyboards and mice. Basically anything that needs some kind of compute
capability probably has a non-Intel processor.

If there's a quagmire we're stuck in it's that we're surrounded by thousands
of devices that are likely full of vulnerabilities that can never, will ever
be fixed.

~~~
Taniwha
Actually most real RISC CPUs have no microcode, and if they do it's really
just the same instruction set running out of an exception handler, not
hardwired stuff on some other lower level private ISA

~~~
astrodust
Is PowerPC still considered RISC? That instruction set has evolved
considerably from the 601 days.

What is a "real" RISC CPU? By what definition?

~~~
Taniwha
Well, there's lots of definitions - I'd include anything that generally has:

\- single cycle ops \- easy to decode ops (fixed size) \- load/store
architecture \- lots of registers to reduce pressure on memory

