
Die shrink: How Intel scaled down the 8086 processor - mnem
http://www.righto.com/2020/06/die-shrink-how-intel-scaled-down-8086.html
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drmpeg
Die shrink of a processor I worked on in the 90's, the C-Cube CL4010.

Looks like the design changed even though it was functionally equivalent.

[http://www.w6rz.net/IMG_0044.JPG](http://www.w6rz.net/IMG_0044.JPG)

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monocasa
That's really neat! Was there ever public documentation on the
microarchitecture of these chips? I seem to remember them from back in their
day and it'd be neat to see how they worked.

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drmpeg
Unfortunately, this was around 1993-1995 and PDF's weren't in widespread use
yet. Everything was on hard copy and I'm sure I tossed that years ago.

It was a fully custom 32-bit ISA and we had a custom back-end for GCC
(although a lot of the code was written in assembly language). The I-cache was
manually loaded. The C compiler had a mechanism to detect when the instruction
pointer went off the ends of the current I-cache page and automatically loaded
the target page. I can't remember if it was some sort of trap or if it was
hard-wired in the code.

The chip had some specialized processing units, most notably a motion
estimation engine that did billions of MSE operations per second and a DSP
engine for the DCT/IDCT.

The chip was used for the DirecTV roll-out in 1995. I remember watching the OJ
Simpson chase on a test receiver in the lab at C-Cube.

The original DirecTV encoders used the CL4000 and were actually MPEG-1 at
720x480 resolution. They used 8 chips to parallel process the image in strips.
When the CL4010 was ready, the encoders were upgraded to MPEG-2 with a 12 chip
architecture (4 chips added to do the additional field/frame motion
estimation).

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monocasa
Neat! Thanks so much for the run down!

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kens
Does anyone have experience with die shrink on modern chips? How does it
compare?

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monocasa
There's a lot of options with different tradeoffs. I've seen both where they
keep most of the mask intact like your 8086 example, and where they just
didn't make RTL changes, but still go through the whole tape out process again
(normally with what were pretty hands off standard cell designs in the first
place).

The Zen+ shrink was neat because they only shrunk the individual transistors,
but kept their position and spacing the same. So the die was the same size,
but just more gaps between gates. I've got a theory the folk who normally sit
between RTL and layout were running around with their hair on fire from the
Spectre revelations, and didn't have the bandwidth to help with low hanging
micro optimizations you'd normally see with a shrink, but only have rumors and
speculation to back that up.

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kristianp
What's the point of doing a shrink, but keeping the die size the same? Power
efficiency, using a new fab?

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monocasa
The choice between better power efficiency, better clock rates, or some
combination of the two.

Additionally, in the Zen+ case, it was a shrink from TSMC 14nm to TSMC 12nm,
which you'd be excused for thinking about as TSMC 14nm+++++. Not a lot of
design rules changed.

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kuroguro
Took me a bit to figure out why Intel was researching mortal psychotherapists,
lol.

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sytse
I looked into the differences between the 8086 and 8088 because the 8086 was
selected for most designs when the 8088 was already available.

Turns out the 8088 has less compute power. I think all Intel chips since than
have higher numbers if they are more powerful, not if they are more recent.

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SomeoneFromCA
Contrary to what the others are saying, 8086 and 8088 have more differences
than just bus size. Certain instruction have different timings, and as I
vaguely remember, pipeline depth was also different.

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kens
The 8086 and 8088 CPUs differ essentially from one another by their respective
data bus widths (the 8086 uses a 16-bit data bus, and the 8088 uses an 8-bit
data bus). The Execution Unit for each processor is identical. The Bus
Interface Unit for the 8086 incorporates a 16-bit data bus and a 6-byte
instruction queue whereas the 8088 incorporates an 8-bit data bus and a 4-byte
instruction queue.

See the iAPX 86,88 User's Manual
[http://www.bitsavers.org/components/intel/_dataBooks/1981_iA...](http://www.bitsavers.org/components/intel/_dataBooks/1981_iAPX_86_88_Users_Manual.pdf)

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SomeoneFromCA
You contradict yourself, when you say "differ essentially from one another by
their respective data bus widths" and "8086 incorporates a 16-bit data bus and
a 6-byte instruction queue whereas the 8088 incorporates an 8-bit data bus and
a 4-byte instruction queue.". In a sense 8088 has shorter pipeline. Shorter
pipeline makes optimization techniques for 86 and 88 different, irrespective
of the bus width - I mean, even if you slap 16 bit bus to 88, without changing
the queue size, most efficient optimizations would still be different between
these 2 CPUs.

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kens
I'm literally quoting from page 4-1 of the Intel 8086/8088 manual.

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SomeoneFromCA
And how the fact that you are quoting from some manual contradicts the fact
that speed is different because of different pipeline depth?

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Jonnax
How long was the 8086 in production for?

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kens
The 8086 was in production from 1978 to 1998.

