
RISC-V port accepted for inclusion in GCC - edelsohn
https://gcc.gnu.org/ml/gcc/2017-01/msg00148.html
======
AdmiralAsshat
Given the momentum of Coreboot and Libreboot for having completely "free and
open" architecture, how many years away are we from having commercial laptops
available using RISC-V processors?

~~~
nine_k
Probably many: the processor has to be made by millions (per model, not in
total) to become reasonably priced, and it will still be slower and/or hotter
than an offering from Intel who have spend untold man-years honing their
architecture. Think Talos and IBM Power8, IBM being a serious force behind the
Power architecture, with companies like Google among its customers.

RISC-V should have a key advantage and exploit it. IDK if the advantage of
openness would be key for general-purpose laptops. Special laptops would
probably be available but pricey; compare to other niche laptops, like highly-
protected ones.

~~~
throwawayish
It's completely unreasonable to expect some underdog architecture to get
anywhere close to the big ones, which have pured dozens of billions of dollars
into research over _decades_ to optimize their designs, tooling and
fabrication.

A reasonable expectation is to get some low-end-ish CPUs out that might be on
the same level (in terms of efficiency) than older, not really optimised ARM
designs.

The biggest incentive RISC-V can offer is less legacy bullshit (like AArch64)
and the fact that you don't have to pair royalties to ARM. Perhaps better
standardisation of peripherals compared to ARM, so less time/money spent on
integration, BSPs and stuff like that.

(And even then: Looking at recent POWER one can see that they can outperform
related Intel offerings, while being drastically less efficient.)

~~~
wyager
This is a fallacy that I see repeated about the quality of open products all
the time.

It's true, Intel spends more money on R&D than RISC-V is likely to ever get.
But that means next to nothing. When a huge, monolithic, management-driven
company spends billions of dollars on something, a lot of those billions of
dollars aren't being used very effectively.

Consider Linux versus Windows. My suspicion is that Microsoft has spent more
money on Windows dev than has ever been spent on Linux dev. Does that mean
Windows is better than Linux? No; in fact, many people who have to use both
would probably say the opposite. Why is Linux the OS of choice for many
production applications in tech-savvy industries? It just works better and
easier than the high-budget closed competition.

That's not to say that Linux is starved for funding; many large companies
volunteer serious man-hours towards Linux development, because they want an
open system that competes with (and beats) the crappy license-uncumbered
alternative they would have to use otherwise. I expect the same thing to
happen with RISC-V.

You also have this phenomenon in the open-source world where you have grad
students, researchers, and enthusiasts embarking on ultra-high-risk projects
that would never get funded at most companies, but pay off in a big way when
they work. Now that we have an open ISA to work with, I fully expect a huge
outpouring of automated synthesis software based on clever new ideas that
beats the clunky stuff available in industry. We've already seen this
happening on the HDL side of things; open-source, research-driven efforts like
Clash and Chisel are orders of magnitude better than the crap that industry
has been using for years (VHDL and (System)Verilog). Give it some time for the
silicon side of things to improve as well.

~~~
gluggymug
"We've already seen this happening on the HDL side of things; open-source,
research-driven efforts like Clash and Chisel are orders of magnitude better
than the crap that industry has been using for years (VHDL and (System)
Verilog). "

As someone in the industry, I would have to disagree. I question this every
time someone claims it's so awesome. None of those solutions can run
simulations on the back annotated netlist . How do you design without a
simulation tool that can work at every stage of the design flow?

RTL is a behavioral model. Post synthesis is the physical model. What do you
think synthesis engineers do? Just sit around watching the tools run?

~~~
kmicklas
> What do you think synthesis engineers do? Just sit around watching the tools
> run?

Can you explain briefly for someone not in the industry why it's not that
simple? This seems like it should be a 100% automatable process.

~~~
gluggymug
Things don't just work automatically. Some idiot can throw a design in that
doesn't just synthesize.

After synthesis, your RTL becomes a gate level representation. You then place
your logic i.e. Your memory logic near your memories, I/O logic near your pins
etc. You then make clock trees for your various clocks. You don't want related
logic clocked by different parts of the clock tree. Once you have stuff
physically located, you back annotate and do your static timing analysis.

You generally run simulation on the different stages of synthesis. Someone has
to debug all these simulations. They never just pass.

There is a big difference between RTL and gate level simulation. A test
passing in RTL is only the 1st stage. RTL doesn't have any wire models so no
delays are in there. Gate level sims can run with delays in there.

Synthesis tools can also tell you it doesn't pass timing through static timing
analysis but asynchronous parts of the design can't be analyzed. You need
simulation there!

------
saurik
[https://news.ycombinator.com/item?id=13381070](https://news.ycombinator.com/item?id=13381070)

^ Related discussion from when this port was submitted.

------
ktta
I remember hearing something about there being problems with RISC-V+GCC since
FSF wanted copyright assigned to them. [1]

RISC-V did make it to llvm[2], with there being healthy development there. I
remember Fedora running on RISC-V successfully.

Anyone know what happened with the whole copyright assignment problem?

[1]:[https://news.ycombinator.com/item?id=12633037](https://news.ycombinator.com/item?id=12633037)

[2]:[http://lists.llvm.org/pipermail/llvm-
dev/2016-August/103748....](http://lists.llvm.org/pipermail/llvm-
dev/2016-August/103748.html)

EDIT: I found a comment[3] in the old submission which answers my question.

[3]:[https://news.ycombinator.com/item?id=13385968](https://news.ycombinator.com/item?id=13385968)

------
WhitneyLand
How important was it to get support into gcc? llvm wouldn't have been enough?

~~~
_chris_
Can you compile linux with llvm?

~~~
WhitneyLand
I don't know actually, clang/llvm doesn't compile linux?

