
CPU of the Day: Motorola MC68040VL - protomyth
http://www.cpushack.com/2019/11/01/cpu-of-the-day-motorola-mc68040vl/
======
tyingq
The time period is very interesting to me. The 680x0 story is pretty well
documented, but their 88k chips + MVME [1] were also popular in specialized
devices like firewalls. There was a time when Motorola was kicking Intel's
butt in specialized areas.

[1]
[https://en.wikipedia.org/wiki/Motorola_88000](https://en.wikipedia.org/wiki/Motorola_88000)

~~~
pavlov
Motorola was even kicking ass in PCs, although you had to be selective with
benchmarks to show an advantage over Intel Pentiums.

When Steve Jobs came back to Apple, he sanctioned a marketing campaign
emphasizing the performance of the Motorola PowerPC G3, with Intel chips
pictured on the back of snails.

~~~
rasz
Lets not forget "the world's fastest personal computer"
[https://www.businessinsider.com/the-20-most-sexy-violent-
and...](https://www.businessinsider.com/the-20-most-sexy-violent-and-
offensive-ads-that-have-been-banned-in-the-uk-2012-2)

'The ASA has banned two separate Apple commercials from airing in the UK. In
2004 the Power Mac G5 made unsubstantiated claims of being "the world's
fastest personal computer" and in 2008, an iPhone commercial was banned for
saying that it could access "all of the internet" even though it couldn't
support Flash.'

~~~
claudiawerner
>in 2008, an iPhone commercial was banned for saying that it could access "all
of the internet" even though it couldn't support Flash.'

So, not even "all of the web", never mind "all of the Internet", which Apple
still doesn't support.

------
cmrdporcupine
There's an over $5000 bounty for someone to rewrite the GCC backend for the
68k/ColdFire so it can be kept and maintained going forward for newer
versions.

[https://www.bountysource.com/issues/80706251-m68k-convert-
th...](https://www.bountysource.com/issues/80706251-m68k-convert-the-backend-
to-mode_cc-so-it-can-be-kept-in-future-releases)

------
Koshkin
> [microcoding] _is common in processors today and allows greater flexibility_

Microprogramming was already widespread since the 1960s. The early
microprocessors, such as MOS Technology’s 6502, too, used microcode (in its
“hardwired” form).

~~~
jonsen
In a way everything is microcoded. The 6502 was hardly microcoded in the
general meaning of microcode:

“An alternate approach, used in many microprocessors, is to use PLAs or ROMs
(instead of combinational logic) mainly for instruction decoding, and let a
simple state machine (without much, or any, microcode) do most of the
sequencing. The MOS Technology 6502 is an example of a microprocessor using a
PLA for instruction decode and sequencing.”:

[https://en.m.wikipedia.org/wiki/Microcode](https://en.m.wikipedia.org/wiki/Microcode)

~~~
monocasa
Having written microcode, and with the gate level information we have on the
6502 now, I can totally tell you that it's microcode. Some people get confused
for some reason if they've only been exposed to vertical microcode.

~~~
userbinator
If a 6(?)-state PLA counts as microcode, what CPU _isn 't_ microcoded?

~~~
0xcde4c3db
Looking at what the PLA actually does, though, isn't it tantamount to a
cleverly compressed microcode ROM? As far as I understand it, the opcode and
cycle number select a "word" of control signals to spit out, and the PLA
aspect is primarily used to allow multiple permutations of cycle+instruction
to select the same "microinstruction" without duplicating it as a conventional
ROM would require.

edit: I realize that in some trivial sense any combinational logic is
tantamount to a compressed ROM, but I mean that even in a design sense this
seems like it's not far off from a deduped array of microinstructions.

------
classichasclass
Here's an MCF5102 based system, the Alpha Micro Eagle 450. Alpha Micro used
the MCF5102 in their ColdFire-based systems for its '040 backwards
compatibility.

[http://ampm.floodgap.com/www/e450.htm](http://ampm.floodgap.com/www/e450.htm)

~~~
watersb
Big fan of your work.

Once I get my desk rebuilt I will fire up my PowerPC collection again.

------
Someone
_”It has dual MMUs”_

What are dual MMUs good for? One for kernel code and one for user-mode code?
(Does that mean less cache flushing during context switches?)

~~~
tralarpa
The two MMUs use the same page table. There is only one page table root
pointer (actually two: one for user mode and one for kernel mode). But there
are two translation caches for code and data (usually called TLB; called ATC
in the 68040).

However, there are separate configuration registers for code and data address
space that can be used to define which parts of the virtual address space
should be translated and which parts are directly mapped to physical addresses
without translation. Therefore, strictly spoken, the instruction address space
is not necessarily identical to the data address space, despite having only
one page table.

~~~
tralarpa
By the way, the possible difference between instruction and data address space
can have interesting effects.

Amiga programmers, do you remember the (bad) habit of putting data fields
directly into the code? Like this fragment:

    
    
        ...
        jsr OpenLibrary(a6)
        move.l d0, gfxbase
        rts
        gfxbase dc.l 0
    

Imagine now what could happen in the above move.l instruction if the address
"gfxbase" is translated differently from the addresses of the instructions :)

~~~
immigrantsheep
Ooh good times :)

