
RISC-V Foundation - rcarmo
https://riscv.org/
======
ktta
100+ points and no comments? That's a first.

If anyone is wondering, this is the foundation behind the RISC-V architecture
that is supposed to make a dent in the proprietary ISA world of x86 and ARM.

Why? Because this ISA is licensed using a BSD like license which means anyone
can use the ISA without paying _anything_. There have been previous projects
like OpenRISC which failed but they're hoping the company backing behind this
will make it to the consumer and not remain on paper[1].

So what does this mean for you? Cheaper hardware (hopefully).

Whenever any company licenses a core from ARM to make modifications they pay
out of they nose _and_ sign a slew of NDAs. This is another reason why ALL of
raspberry pi isn't open. You can't see the CPU internals even though Broadwell
is open to it.

Now this ISA, has a bunch of minimal base specs which they _must_ follow as to
maintain basic compatibility and then they can add their own extensions as
needed. You can see them here[2] - scroll down to the PDF and then the third
page - preface.

So what the people excited for the project are hoping for, is to get everyone
to use the ISA, because there is very little reason not to, other than
developer inertia and because almost all of existing code is for x86 or ARM.

Now this won't bring about the software like open-sourcedness to hardware,
because every company isn't to eager to share their specific architecture with
you. But some companies which want to, can.

Hopefully this is bring auditable hardware, make everyone focused on specific
compiler architecture (like llvm and GCC) and make hardware, especially the
cheap microcontrollers even cheaper because they don't need a license or fear
getting sued by ARM or Intel(talking about the shady manufactures who break
NDAs and go ahead and manufacture micro-controllers without license). So
expect microcontroller prices to drop to the ground on eBay.

This architecture, isn't just meant for microcontrollers, don't get me wrong!
It is specifically _meant_ to be extensible even for super computers (even
128-bit architecture)! That would require a _huge_ company with large army of
engineers involved in CPU engineering. So a startup like approach isn't
possible. But keep your hope alive!

When? Soon™

[1]:[https://riscv.org/membership/?action=viewlistings](https://riscv.org/membership/?action=viewlistings)
\- Note how Intel and ARM are absent while almost every other semiconductor
manufacturer is present.

[2]:[https://riscv.org/specifications/](https://riscv.org/specifications/) \-
embedded PDF on this page

~~~
ant6n
Ok, so the ISA is open. What about the rest of the design of the CPU?

~~~
microcolonel
There are some interesting open CPU designs at the high level, but it is
basically impossible to fab a state of the art chip with _truly_ open designs.
From the standard cells down, you are unlikely to be allowed to know anything.

Bunnie Huang touched on this, and other themes, at the 6th workshop (though
sadly the audio was not captured directly from the microphone, so it's crummy
PA sound from the perspective of the camera):
[https://www.youtube.com/watch?v=zXwy65d_tu8](https://www.youtube.com/watch?v=zXwy65d_tu8)

That said, if you mean the high level/functional design of the chip, then
there are quite a few open ones. Chris Celio is working on a (seemingly quite
excellent) superscalar out of order RISC-V called BooM. There's a reference
in-order core called Rocket, which is attacked to a lot of "uncore"
infrastructure which is reused by BooM and a couple other chips. They also
have an introductory educational RISC-V core called Sodor.

There's Z-scale which is a deeply-embedded-sized in-order core. Clifford Wolf,
in addition to developing a formal verification framework for RISC-V cores,
has a small RISC-V core called PicoRV32.

SiFive's FE310 is open to the extent permitted by the agreements they've had
to make to fab the chips, which includes RTL for the core itself and a couple
other things. FE310 being the model they shipped in their Arduino-compatible
HiFive1 boards.

------
szatkus
Hey, I was thinking recently about porting something to RISC-V. After short
research looks like there is qemu fork[0] that could be a good start if I
don't want to spend money (probably horribly slow, but better than nothing).
Unfortunately I couldn't find any Linux distro to run on it. Would be grateful
for any advice.

[0] [https://github.com/riscv/riscv-qemu](https://github.com/riscv/riscv-qemu)

~~~
ktta
There's a fedora port to RISC-V, you should be able to find it pretty easily.

There was also a GSoC project I think last year which ran a linux distro on
the FPGA of a parallela board. I guess this will require purchasing something.
But if you are up for purchasing something, get the Nexys 4 DDR, which is what
Fedora project recommends and you can use open sources RISC-V designs like
SiFive[1]

[1]:[https://news.ycombinator.com/item?id=14283272](https://news.ycombinator.com/item?id=14283272)

~~~
rjsw
The Nexys 4 only has 16-bit wide RAM, the Parallella has 32-bit wide RAM.

------
nfriedly
How long until I can buy an Adruino or Raspberry Pi sort of development board
that has a chip implementing the RISC-V ISA?

Is anything like that available today? Anything planned?

~~~
tdicola
The Arduino Cinque board was just announced and has a RISC-V chip along with
an ESP32 and STM32: [http://hackaday.com/2017/05/20/arduino-cinque-the-risc-v-
esp...](http://hackaday.com/2017/05/20/arduino-cinque-the-risc-v-esp32-wifi-
bluetooth-arduino/)

------
MycroftJones
I've been wondering how RISC-V compares to Donald Knuth's MMIX ISA. Surely
MMIX is also freely available, probably Public Domain or something?

------
deepnotderp
I'm hoping for the success of RISC-V, an open ISA would solve many binary
compatibility issues and free chip makers to compete on the merits of their
microarchitecture and not their ISA lock in ( cough cough Intel).

That being said, I doubt it's going to happen. Chip makers have a strong
incentive to have a proprietary USA that they can use for lock in a la x86.

~~~
ZenoArrow
There are only a handful of high end chip manufacturers left. The lock in you
describe only really applies to Intel (and not that strongly either, they have
been known to manufacture non-x86/x64 chips in the past). Manufacturers like
TSMC are effectively a fab-for-hire, you're unlikely to see them turning down
sales just to specialise in a single ISA.

[https://en.m.wikipedia.org/wiki/TSMC](https://en.m.wikipedia.org/wiki/TSMC)

~~~
deepnotderp
I meant fabless companies and ODMs, why on earth would a foundry refuse
business?

------
cmurf
I think cheaper hardware is one possibility, but more importantly it's
decentralized design, manufacturing, and auditing. It unencumbers it from one
or a few companies, and governments. And it has the potential to increase
trust.

With Intel ME/AMT, I think we're witnessing the limitations of the existing
models.

