

IPhone 4S: Anandtech review - incremental
http://www.anandtech.com/show/4971/apple-iphone-4s-review-att-verizon

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johno215
I like seeing an in-depth review.

These days it feels like all the major sites rush out the reviews right before
launch day with less than a day of actually testing being done. The reviews
often sound like just a re-hash of the press release specs.

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technoslut
I, as I assume most on this site, only considers Anandtech the one true tech
product reviewer on the web. The only other equal is John Siracusa's review of
the latest Mac OS release.

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amartya916
Exactly. Which is why the only time I quote a review in a post is when it's
one from Anandtech. It takes a solid hour and a little more for me to go
through their reviews and it's always a pleasure because one comes out wiser
at the end of it. In this review, I really enjoyed reading the A5 architecture
and the optics section, it was interesting that they bothered to dig out where
the optics might be sourced from (Genius Opt.).

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barredo
Now that an 800mhz A5 gets better scores than 1.2Ghz chips... are we going
back to the PPC vs Intel days?

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nextparadigms
No, it doesn't. It's still mostly a software issue. As you can see a dual core
1.2 Ghz GS 2 gets 3300 ms, while a dual core 1.2 Ghz Droid RAZR gets 2000 ms.
And that's just the stock browser. It can even get 1300 ms in Firefox.

The A5 still uses 2 Cortex A9 cores. Whatever optimizations Apple has done to
it will have a minimal impact on performance. The biggest gains will still be
obtained on the software side.

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roc
> _"Whatever optimizations Apple has done to it will have a minimal impact on
> performance."_

I agree in general, though I think Apple is going to continue adding custom
DSPs to their package. And that will provide an advantage in those targeted
areas that software alone will not be able to bridge.

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ajross
Overall a good article. Though it's got this whopper:

 _A DRAM package is then stacked on top of the SoC. Avoiding having to route
high-speed DRAM lines on the PCB itself not only saves space but it further
reduces memory latency._

Uh... come again? DRAM latency is a function of the analog circuit inside the
chip, not the wires you connect to it. At best, you might be able to drive the
chips at a higher transfer frequency (but even then, the limit is probably on-
package in the DRAM, not due to board trace problems). But that has at best a
minimal effect on latency (you're shrinking the handful of transfer cycles at
the end of the read).

The advantage of the PoP configuration is _precisely_ that it saves space --
quite a bit of space, and it's a great trick. But this bit is just way off.

