
MIPS Goes Open Source - walterbell
https://www.eetimes.com/document.asp?doc_id=1334087
======
jf
> “Had this happened two or three years ago, RISC-V would have never been
> born.”

Had RISC-V not been born, MIPS wouldn't have made this announcement.

~~~
ac29
MIPS was on its way to irrelevance, first as ARM slowly ate its remaining
marketshare, then quickly when Imagination Technology went under and sold it
off for a pittance to a relatively obscure "AI" company.

RISC-V may have hastened its demise, but the writing was on the wall for a
long time.

~~~
chasil
I don't program in assembler professionally, but I understand that MIPS has
some ugly, ugly aspects:

[https://www.jwhitham.org/2016/02/risc-instruction-sets-i-
hav...](https://www.jwhitham.org/2016/02/risc-instruction-sets-i-have-known-
and.html)

Sun opened the SPARC T2 a decade ago, and it certainly has not become popular:

[https://www.oracle.com/technetwork/systems/opensparc/openspa...](https://www.oracle.com/technetwork/systems/opensparc/opensparc-t2-page-1446157.html)

It does seem that RISC-V corrects a number of these design eccentricities.
SPARC did not move the market an inch with an open release - perhaps MIPS will
fail just as spectacularly.

~~~
spoonhat
The blog post you link to criticizes MIPS because it has pipeline hazards and
branch delay slots. MIPS had hazards in 1985. MIPS II eliminated hazards. No
MIPS processor released after 1989 has hazards. Branch delay slots are no big
deal once you know they're there. There are a number of equally questionable
design decisions in RISC-V, such as variable length instruction encoding and
dest, src order of instruction operands. But RISC-V does have momentum.

~~~
amluto
> Branch delay slots are no big deal once you know they're there.

I disagree. I'm not really a MIPS user, but I've managed to encounter some
branch delay slot issues, and, as an x86 system programmer, I can only imagine
how unpleasant they must be. Here are some reasons:

\- The program counter does not adequately describe the execution state of the
CPU. In other words, starting or resuming execution with a given set of
register values and a given address will do the wrong thing if you're resuming
in a branch delay slot.

\- Handling a fault due to an instruction in a branch delay slot seems highly
problematic. Suppose you have a load in a delay slot and the load touches
swapped-out memory. How is the operating system supposed to page in that
memory and resume?

\- Linux, and probably other operating systems, will emulate FPU instructions
if the CPU doesn't support them. Emulating FPU _branch_ instructions is deeply
problematic because of delay slots.

~~~
monocasa
The first two just mean that there's an extra trap state bit in a flags
register for "I'm in a bench delay slot currently" and isn't really a big
deal.

The third one I imagine is a pain in the ass, but I've been lucky enough to
always compile MIPS for the exact CPU I was running it on.

~~~
amluto
It’s more than just a bit. You need a bit saying “in a delay slot” and a whole
word that stores the target of the branch.

~~~
monocasa
Nah, a delay slot bit is fine. Branches haven't really retired yet (that's the
point of a delay slot), so when you reenter the instruction with that bit set
the CPU just backs PC up and executes both of them again.

You have to make sure you can map two pages at once in case the branch/delay
pair straddles a TLB boundary, but you have to screw up pretty bad to not
allow that.

~~~
amluto
_shudder_

If you try this on hardware that also supports software single stepping (which
x86 does, but MIPS seems not to by default), then you have to be extra
creative to guarantee forward progress. The same issue arises if you have data
breakpoints. And if the branch loads from MMIO space, you have a problem.

~~~
monocasa
I mean, it's MIPS so it's a load/store architecture anyway. Between the pair
you're only going to have one memory reference at most, and it's going to be
the delay slot.

------
ChuckMcM
That is pretty awesome. So three 'open' RISC architectures (RISC-V, MIPS,
SPARC) with varying amounts of ecosystem support.

That the patent stuff seems to be dealt with is key here, one of the
challenges with working with MIPS and SPARC was always that their 'parent'
organizations (SGI and Sun respectively) were essentially patent trolls when
it came to third parties being successful with the architecture. Now that SGI
and Sun are just footnotes in the computer industry, perhaps these
architectures can flourish.

~~~
rurban
POWER8 is also open now:
[https://openpowerfoundation.org/](https://openpowerfoundation.org/) By far
the best of those. But IBM, and it's not POWER9.

~~~
ksec
>and it's not POWER9

Surely POWER9 is open as well? Otherwise how did Raptor ship their POWER9 CPU?

~~~
rurban
Power9 only has open firmware and ISA, but not the verilog. They just resell
it, to Raptor and Google-Rackspace mostly.

------
monocasa
What licence?

Their FAQ certainly reads more like "source available" than "open source". You
have to be a registered MIPS Open Member to even see anything.

[https://wavecomp.ai/mipsopen](https://wavecomp.ai/mipsopen)

~~~
snaky
> Swift is very familiar with most of the MIPS players in China, “because I
> worked with them,” he told us.

Well, things change, and if he still thinks about a couple of big vendors,
that would fit. But most of the Chinese SoC vendors using RISC-V aren't big
nowadays, and most of them probably wouldn't bother with all that corporate
memberships and stuff.

~~~
microcolonel
I think this might change. They are participating at least a bit for now.

------
_chris_
In comparing RISC-V vs MIPS, I think people are forgetting that one is a
Foundation of member companies driving development, and the other is one
company releasing their IP.

There's obvious pluses and minuses to both approaches, but if I were a company
trying to choose an ISA for my own IP development, I'd probably want the ISA
that has a Foundation I can join and help drive its direction going forward
[Ed: it will be interesting to see how MIPS proceeds from here].

~~~
walterbell
MIPS is involved in this foundation: [https://prplfoundation.org/current-
members/](https://prplfoundation.org/current-members/)

------
jhallenworld
I wonder if this will include the MIPS 16e extension (the thumb-like
instruction set for MIPS). It would be interesting to me if MIPS can compete
with ARM in microcontrollers. As far as I know, only the PIC32 is MIPS.

I used IDT's MIPS IDTR3041 in an embedded system in the mid 90s... I remember
compiling gcc for "decstation" to support it.

[https://stuff.mit.edu/afs/sipb/contrib/doc/specs/ic/cpu/mips...](https://stuff.mit.edu/afs/sipb/contrib/doc/specs/ic/cpu/mips/r3051.pdf)

Will Sparc follow? I used the LEON4 SPARC processor in Intel / Movidius Myriad
recently, was surprised to see Sparc...

~~~
rjsw
> Will Sparc follow?

SPARC is already open, as in it can be used royalty free and there are open
source implementations.

~~~
hlandau
My understanding is that only 32-bit SPARC is open. The 64-bit extensions are
still proprietary, aren't they?

~~~
djcapelis
The verilog for the UltraSPARC T1 core is GPL. I have my own fork on a dev
board they used to make for the purposes of researchers modifying it and
giving a modified processor a spin. So... I don’t think so?

~~~
hlandau
I'm talking about the patent licences for the _ISA_ , not a specific core.
Does the GPLv2 licence for the T1 confer a patent licence? If not, you'd
probably need patent licences for the 64-bit ISA from Oracle to market
something, AIUI. Whereas I believe 32-bit SPARC is an IEEE standard and
royalty-free.

~~~
blattimwind
SPARC V9 (which is the 64 bit version) lies with SPARC International. That
doesn't necessarily extend to OSA2011/OSA2017, whose specifications are
available from Oracle, but I wouldn't bet on their royalty-freeness.

------
fernly
The article notes the "maturity" of the support software. Indeed when I was
writing manuals for SGI in the 90s, I was trying to document what seemed like
extremely sophisticated compiler optimization techniques, including link-time
optimization. (Due to customer demand there was also a screaming Fortran IV
compiler, but it was bought in from a vendor.)

I also remember how one range of the MIPS line (4000?) had the "4K page bug"
where a page fault induced by the last instruction on a page caused some nasty
problem. IRIX had special code to handle it.

------
walterbell
Will this make MIPS hardware virtualization available to the Western market?
So far it's only been available in a Russian CPU (Balkal),
[https://news.ycombinator.com/item?id=18142295](https://news.ycombinator.com/item?id=18142295)

Article says that PRPL foundation may be governing Open MIPS. There was an
L4-based hypervisor offered by PRPL, but the website seems to have been
reorganized.

Virt whitepaper: [https://prplfoundation.org/wp-
content/uploads/2018/07/prpl-s...](https://prplfoundation.org/wp-
content/uploads/2018/07/prpl-security-guidance-for-critical-areas-of-embedded-
computing-2-5-2.pdf)

~~~
baybal2
Lol, the story with them choosing MIPS over ARM is that ARM was too afraid to
get slapped with sanction, and they went to MIPS instead.

After ARM saw that the sky is not falling on MIPS, they decided to license
them their cores as well.

------
mindcrime
Interesting that MIPS includes DSP functionality in the ISA. Does anyone have
experience using DSP functionality with a MIPS chip? This seems like something
that could be big, since so many of the DSP chips that are out there are
totally proprietary, require proprietary compilers, etc. The idea of widely
available DSP support that can be built with standard off the shelf OSS
compilers / tools seems like something that could be a big win.

~~~
lambda
These include instructions for saturating arithmetic (arithmetic that give the
greatest or lowest possible values, rather than wrapping around), 16 and 32
bit fixed point, fused multiply add instructions, and some SIMD instructions
[https://en.wikipedia.org/wiki/MIPS_architecture#MIPS_DSP](https://en.wikipedia.org/wiki/MIPS_architecture#MIPS_DSP)

Basically your usual DSP fare.

ARM has a similar extension; see
[https://en.wikipedia.org/wiki/ARM_architecture#DSP_enhanceme...](https://en.wikipedia.org/wiki/ARM_architecture#DSP_enhancement_instructions)
for a reference to it, or
[http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc....](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.100166_0001_00_en/ric1417449098079.html)
for details.

I don't think that RISC-V has a DSP extension yet; they are still working on
nailing down their SIMD/vector extension story.

~~~
wbl
They are trying to support vector machines as well as SIMD instructions.

~~~
lambda
You mean RISC-V or MIPS?

There's a reason why I said SIMD/vector extension, since RISC-V first started
down the SIMD route, but then they took a step back and decided that a vector
extension might work better, so from what I can tell more work has been going
into the vector extension than SIMD. But neither SIMD nor the vector extension
are finalized yet.

I'm unaware of a MIPS vector extension, it seems to just have standard packed
SIMD instructions, though I'm not that familiar with MIPS.

------
nickpsecurity
This is awesome! It might mean we get a CHERI board without a RISC-V port. The
port is still a good idea but a port to highest-end MIPS will probably be
cheaper since it reuses toolchain and some hardware stuff.

Then we can make the desktop cases look like SGI’s as a tribute to the best
MIPS of the past. Plus, they look cool.

[https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/](https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/)

~~~
walterbell
That would be industry-changing for desktop security - capabilities in open
hardware.

Does the MIPS ecosystem have an equivalent to coreboot?

~~~
LargoLasskhyfv
For what? There is [https://en.wikipedia.org/wiki/Das_U-
Boot](https://en.wikipedia.org/wiki/Das_U-Boot) and [https://www.linux-
mips.org/wiki/PMON_2000](https://www.linux-mips.org/wiki/PMON_2000) I bet "Das
U-Boot" is more of an "ecosystem" than coreboot when you zoom far out and see
the installed base of embedded devices. Coreboot unfortunately not so much in
comparison.

------
gurjeet
Despite this announcement, RISC-V momentum is not going to stop. Anyone trying
to understand why, should watch this presentation by Krste Asanovic, as it
sets RISC-V in historical and market context.

[https://www.youtube.com/watch?v=QTYiH1Y5UV0](https://www.youtube.com/watch?v=QTYiH1Y5UV0)

edit: added link to presentation.

------
retSava
It's cool to see such an old and well-used arch still be used in new
applications, not just old legacy stuff.

And, gotta love: "Wave, which styles itself as a tech startup poised to bring
“AI and deep learning from the datacenter to the edge,” sees MIPS as a key to
advancing Wave’s AI into a host of uses and applications.". Hello, fellow
kids!

~~~
kevin_thibedeau
As opposed to the 8080 variant most people have in their PCs?

~~~
snvzz
68000 was the better CISC architecture.

------
znpy
The devil lies in the details: it all depends on the actual license that Wave
Computing will use for MIPS.

------
nickik
Funny, I would have gone bananas over this a couple years ago. Now, its mix
between disappointment and but still support. MIPS exists and will continue to
exist, its far to large to ever go away so it is good that it will open up and
eventually we can remove property architectures from the market.

I just hope they really commit to that strategy. Remember Docker was once a
failing PaaS company who released their tech as open source.

------
bogomipz
The article states:

>"Included in MIPS instruction sets are extensions such as SIMD (single
instruction, multiple data) and DSP."

I always thought of DSPs as being a specific type of chip i.e a DSP chip. Are
Are many DSPs MIPs based then? Is a DSP really just any general purpose CPU
whose ISA has optimized DSP instructions then?

~~~
dumael
MIPS has what's called an Application Specific Extension (ASE) basis for
extending a given MIPS core for particular areas.

The MIPS DSP ASE extends the base instruction set with certain instructions
applicable to various codecs of the day that the ASE was defined for. It's
essentially extending a general purpose cpu to efficiently perform DSP like
tasks.

------
amatecha
BTW, some official information on MIPS' site[0] which doesn't show a
fullscreen modal or split the information across three ad-laden pages ;) Looks
like there is a forthcoming site[1] for the initiative as well, which has not
launched yet.

[0] [https://www.mips.com/mipsopen/](https://www.mips.com/mipsopen/) [1]
[https://mipsopen.com/](https://mipsopen.com/)

------
ksec
If Imagination didn't win, CEVA would have been a much better fit for MIPS.
IMG might have been better off focusing on something else ( But judging from
their management direction and execution I doubt they would have survived long
anyway )

I think only Cavium and Broadcom are the biggest supporter of MIPS, not sure
if there are any other heavyweight, but both have in recent years diverged to
ARMv8.

I think the most interesting part is open sources includes DSP and SIMD.

------
dtx1
what does open source mean in this context?

~~~
justincormack
The article just says the most recent 32 and 64 bit instruction sets will be
open. No mention of open core designs (there are many old versions of MIPS, it
has been very fragmented, so excluding these makes sense to get some
commonality).

~~~
jordigh
And again, what does it mean for the instruction set to be open? Does that
mean that they are releasing circuit schematics and hardware documentation?
Surely it means more than releasing documentation for the instruction set like
we have for Intel chips.

~~~
orbifold
It means that you are allowed to design/produce a chip using this instruction
set without getting sued.

~~~
jordigh
Just that? With no extra help from them? No schematics or diagrams or
documentation? Do you still have to reverse-engineer their work?

Did AMD have to get permission from Intel to implement the i386 instruction
set?

~~~
otterlicious
_Did AMD have to get permission from Intel to implement the i386 instruction
set?_

Yup, and Intel needed permission from AMD to implement the x86_64 instruction
set.

[https://www.cnet.com/news/intel-and-amd-a-long-history-in-
co...](https://www.cnet.com/news/intel-and-amd-a-long-history-in-court/)

~~~
jolmg
What about emulators? Did bochs and qemu need to get permission?

I'm not really understanding the legal basis here. Did these companies get
patents for the instruction sets? Since instruction sets are really like APIs,
can people get patents for APIs?

------
riemannzeta
What applications is the hierarchical clustering approach MIPS's owner Wave is
taking to designing ASICs for machine learning going to work best for? Deep
learning?

Anybody with ASIC design experience have a view on whether what they've got
will be competitive (along energy or speed dimension) with TPUs or whatever
RISC-V solution NVIDIA is working on?

~~~
WillSlim95
Till the silicon comes nobody can really say much. Also NVIDIA is only using
RISC V for the system controller for their future GPUs.

~~~
nickik
NVIDIA is also working with SiFive to deliver some of their stuff on RISC-V.

~~~
WillSlim95
Well it is different, what they are delivering is not based on RISC V but
rather a silicon implementation of their NVDLA which will act as a peripheral
to a SiFive core.

------
victore
[https://www.amazon.com/Digital-Design-Computer-
Architecture-...](https://www.amazon.com/Digital-Design-Computer-Architecture-
Harris/dp/0123944244/ref=sr_1_4?ie=UTF8&qid=1545079537&sr=8-4&keywords=computer+architecture)

------
danaos
From what I gather they are also holding Lexra core IP.[1]

Hopefully they will be releasing the Lexra IP too. I have stumbled upon many
routers that utilize Lexra cores.

[https://www.linux-mips.org/wiki/Lexra](https://www.linux-mips.org/wiki/Lexra)

------
billfruit
Hearing news like this I wonder, what happened to Transmeta's processor
architectures?

~~~
walterbell
Similar capabilities are shipping in some Nvidia CPUs,
[https://hothardware.com/news/nvidias-64bit-tegra-k1-the-
ghos...](https://hothardware.com/news/nvidias-64bit-tegra-k1-the-ghost-of-
transmeta-rides-again)

Transmeta's founder is working on RISC-V AI/ML chips at Esperanto.

------
userbinator
"Open Source"? As if it really matters for the dozens of computer science
courses out there which used MIPS as a base (and some are now switching to
RISC-V)... and a lot of unlicensed MIPS-ish/clone cores are also present in
various cheap Chinese gadgets. I mean, if the average second-year CS student
can make a working MIPS core, what does that say about how much it's worth?
It's such a mundane ISA that you can't really squeeze much out of it (and I'm
not talking about adding SIMD and such, which you could do for x86 and ARM
too) unlike x86 and to a lesser extent ARM.

x86 or ARM going open-source, now _that_ would be interesting...

------
pozzed420
Is this only for their newest core or will they be releasing old stuff too?
Would be really interesting to see the HDL for early MIPS processors like the
3051, 4300, 5900, etc.

~~~
ZirconiumX
Of those cores, MIPS own the direct rights to none of them.

The R3051 (used in the PlayStation 1) was a derivative of the R3000A (which
MIPS should have the rights to) made by IDT. I don't think MIPS have the right
to the modifications.

The R4300 (A derivative, the NEC VR4300 was used in the Nintendo 64) was
designed by Quantum Effect; I think whoever owns what's left of them would own
the HDL, if it's still around.

The R5900 (used as the core of the PlayStation 2's Emotion Engine) was
designed by Sony and Toshiba; I'm pretty sure Toshiba have the rights to it.

~~~
pozzed420
Yeah I know there's licensing issues for those exact processors, it would
still be cool to see the stuff they were derived from.

------
kbumsik
Only ISA? I must have missed something, but I cannot see if they are going to
open-source its implementation though.

------
jibanes
I wish they could opensource mipspro

------
capkutay
I can't wait for a company to raise $100 million Series A to sell 'Enterprise,
Open Source MIPS', then come back in 4 years with a blog post about changing
the license due to concerns that large companies are taking advantage of it.

------
glenrivard
Will it slow down RISC-V?

~~~
lambda
Probably not at this point. If they had done this right when RISC-V was first
announced, then maybe, as at that point they had the advantage of much more
ecosystem and tooling integration.

However, it's now at the point where there are shipping RISC-V Linux distros,
it's supported in GCC and LLVM out of the box, there are more than a dozen
open-source RISC-V cores ([https://riscv.org/risc-v-
cores/](https://riscv.org/risc-v-cores/), several of which are actually
parameterized families of cores), and there are companies like SiFive offering
commercially supported proprietary cores. There is hardware that has shipped
from multiple different vendors, and that likely means that there are a number
of others where it's fairly far in the pipeline.

With MIPS being behind Intel on the desktop and server market, behind ARM on
the proprietary embedded core front, and behind RISC-V on the open source ISA
and cores front, it's a bit hard to see why someone would buy MIPS who hasn't
already invested in it.

If you want something more well established with a wider variety of cores
available to purchase, you'd go with ARM. If you want something with no ISA
licensing fees and even potentially no charge at all for an open source core,
you can go with RISC-V.

I suppose there is some chance that MIPS could win some folks over from RISC-V
for already having stable SIMD and DSP extensions, and more overall
architectural maturity than RISC-V. But given that this seems to just be
opening up the ISA without opening up any cores, and right now is a press
release without having decided on the governance structure for the project or
released any assets, while RISC-V has a number of fairly mature open cores
including Rocket, BOOM, RI5CY, and more, and has a governance structure with a
number of different companies involved, it seems like it will be a while if
ever for MIPS to catch up on the open ISA front.

~~~
snaky
> from multiple different vendors

Hundreds.

> China is rallying around the architecture with perhaps hundreds of RISC-V
> SoCs and dozens of cores in the works.

> “We are talking hundreds, if not thousands, of [RISC-V–based SoC] projects
> under way; it’s crazy … probably at least 40 to 50 companies or academic
> groups are dabbing in core development — some for internal use, some for
> open-source, and some commercial”

[https://www.eetimes.com/document.asp?doc_id=1334032](https://www.eetimes.com/document.asp?doc_id=1334032)

~~~
lambda
When I mentioned "multiple vendors," I was talking about hardware
implementations that have actually shipped.

I've been looking for RISC-V chips that I can buy right now, and from what I
can tell, there are only a handful. Two from SiFive (the E310 embedded
processor, and U540 supervisor mode/Linux capable processor), one from
GreenWaves (the GAP8). Turns out since I last looked (around the beginning of
October) it looks like the Kendryte K210 has been released, also available in
the Sipeed M1 module ([https://www.cnx-software.com/2018/10/22/sipeed-m1-risc-
v-com...](https://www.cnx-software.com/2018/10/22/sipeed-m1-risc-v-computer-
vision-module/)). Anyhow, that makes 3 vendors shipping hardware
implementations.

It's possible there are other special purpose chips not widely available for
sale, or not advertised to English speaking customers, but I haven't found
much evidence of them.

There certainly are a lot of RISC-V projects under way, which was what I was
referring to by "that likely means that there are a number of others where
it's fairly far in the pipeline." I think the "hundreds" from the article you
quote is about total number of projects, not total number of vendors.

Some of these are just academic projects, some are multiple projects at the
same vendor, and so on. I wouldn't be surprised if it was dozens of vendors
that have projects at various stages of completion, however. I can imagine
we'll be seeing a lot of releases over the next couple of years.

And there are a number of cores you can run on FPGAs, from high-end cores like
BOOM that can be run on big expensive Xilinx FPGAs (or on Amazon's cloud
FPGAs), to low-end like PicoRV32 that you can run on a $5 Lattice ICE FPGA.

~~~
snaky
> It's possible there are other special purpose chips not widely available for
> sale, or not advertised to English speaking customers, but I haven't found
> much evidence of them.

Take any established Chinese IT company, there are chances they are working on
RISC-V based SoC or two. Alibaba - CK902, Huami - Huangshan No. 1, not talking
about less known at the West vendors.

But it seems there are some considerations among established IT companies
about not announcing RISC-V products very loud, especially in English.

> The Western executive, speaking on condition of anonymity, told us, “A lot
> of the biggest companies doing this are being very discrete indeed: perhaps
> they cannot afford to upset Arm.” He said they fear being told by Arm, “‘Oh,
> the core for your new smartphone is two weeks late.’”

[https://www.eetimes.com/author.asp?section_id=36&doc_id=1334...](https://www.eetimes.com/author.asp?section_id=36&doc_id=1334001)

