
The ARM1 processor's flags, reverse engineered - mnem
http://www.righto.com/2016/02/the-arm1-processors-flags-reverse.html
======
userbinator
_But why complement the bus? The reason is that it 's easier with CMOS to pull
a line low than to pull a line high._

The other reason, and why some signals are active-low instead of active-high,
is that it saves transistors (and is slightly faster) - due to how gates are
constructed, a NAND or NOR is the "natural" construction, and AND or OR gates
are actually NAND/NOR with an extra inverter on the output. A CMOS NAND-2 or
NOR-2 requires 4 transistors, whereas an AND-2 or OR-2 requires 6.

~~~
kens
That's a good point. One wild thing about MOS is that it's also "natural" to
create gates such as AND-NOR or AND-OR-NAND or other even crazier
combinations, as long as the last step is inversion. Right now I'm looking at
a Z-80 gate that is three triple-input ANDs, all NORed together, and this is a
single gate. Also, a pair of OR-NAND gates is a convenient way to make a
latch. This may be more than anyone wants to know about gates :-)

~~~
userbinator
_Right now I 'm looking at a Z-80 gate that is three triple-input ANDs, all
NORed together, and this is a single gate._

An "AOI333", like this?

    
    
               Vdd
                |
                +-|
                  |--+
                +<|  |
                |    |
                +----+---> out
                |
           +----+----+
           |    |    |
         +-+  +-+  +-+
        -+   -+   -+
         +>+  +>+  +>+
           |    |    |
         +-+  +-+  +-+
        -+   -+   -+
         +>+  +>+  +>+
           |    |    |
         +-+  +-+  +-+
        -+   -+   -+
         +>+  +>+  +>+
           |    |    |
           +----+----+
                |
               Vss
    

It's a good example of how even at the hardware level, abstraction can hide
optimisation --- someone who didn't know about these compound gates would just
design with the regular ones, using far more transistors than necessary. That
(NMOS) gate has a total of 10 transistors, while the equivalent with
individual gates would take 22 (6 for each AND -- 3 pulldown + 1 pullup for a
NAND, followed by another 2 for an inverter, feeding into a 4-transistor
NOR-3), more than double.

Given how "loose" its layout is compared to the Z80, I guess the ARM1 doesn't
have very many compound gates either? I wonder if they could've gotten an even
lower-power and faster ARM1 if they did manually optimise the layout.

~~~
kens
Amazing job with the ASCII gate layout :-) Here's a link to the real layout:
[https://lh3.googleusercontent.com/-vsyhirk5hFU/VrgVJMXZDyI/A...](https://lh3.googleusercontent.com/-vsyhirk5hFU/VrgVJMXZDyI/AAAAAAAAy6g/Ydvjg1r59PY/s800-Ic42/z80-gate-
labeled.png) Note how insanely optimized the hand layout of the Z-80 is.

The ARM1 has some compound gates. but I haven't come across anything more
complex than OR-NAND. It's mostly built from standard cells. The layout is
kind of awful compared to the 6502 or Z-80, but the ARM designers were going
for ease of design rather than optimization. Since the ARM1 had so few
transistors for its time, they didn't need to worry about space on the die and
were more concerned with making the design easy to debug. One of the other
guys looking at the ARM1 found "wires to nowhere" from fixes to the chip:
[http://daveshacks.blogspot.com/2016/01/inside-armv1-read-
bus...](http://daveshacks.blogspot.com/2016/01/inside-armv1-read-bus-b-alu-
output-bus.html)

