
SiFive open sources RISC-V chips - erichocean
https://github.com/sifive/freedom
======
vhodges
They're also doing silicon:
[https://www.crowdsupply.com/sifive/hifive1](https://www.crowdsupply.com/sifive/hifive1)

Along with:
[https://www.crowdsupply.com/onchip/open-v](https://www.crowdsupply.com/onchip/open-v)

The fifth RISC-V workshop is on right now and being live blogged at:
[http://www.lowrisc.org/blog/2016/11/fifth-risc-v-workshop-
da...](http://www.lowrisc.org/blog/2016/11/fifth-risc-v-workshop-day-one/)

~~~
ant6n
Neat. Does that board run linux? Can I hook up a screen, mouse and keyboard?

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duskwuff
No. The SiFive part is a microcontroller -- it has 16 KB of RAM.

~~~
ant6n
Huh, I thought that was the cache. 320Mhz, but 16KB Ram. That seems like an
odd combination.

Quake ran on a 75MHz cpu, but needed 8MB or ram.

~~~
wyldfire
Quake was targeted on a CISC-design general purpose CPU, on a very different
process from modern ones. Those factors likely explain much of the difference
in clock speed. They just couldn't make 320MHz parts as easily then. Even
modern x86 CPUs are RISC inside and have microcode to execute the CISC
instructions.

These particular RISC-V parts are targeting the microcontroller marketplace
where there's little RAM required.

~~~
wang_li
It's a bit silly to be talking RISC and CISC these days. The big idea behind
RISC is to spend your transistor budget on minimizing the cycle time of a
smaller core set of instructions.

However, transistor count has been doubling for quite some time, and clock
frequency has gone up by a factor of 100.

The idea behind RISC no longer applies. This is observed in the numbers and
the fact that every processor manufacturer has been adding video engines,
crypto engines and vector units to their processors.

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greglindahl
One of the designs runs on a $99 evaluation FPGA board -- not so bad for
something available today.

They have actual chips/boards shipping in December & February:
[https://www.crowdsupply.com/sifive/hifive1](https://www.crowdsupply.com/sifive/hifive1)

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wyldfire
Sounds like a super neat uC. Is anyone planning a generally available RISC-V
with typical ARM or x86-sized caches and memory controllers?

RISC-V is open, but so is the SH-esque j-core. Why is RISC-V so much more
popular?

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asb
That's what we're working towards with
[http://www.lowrisc.org](http://www.lowrisc.org)

~~~
wyldfire
I can't seem to find what specs the SoC(s) might have on the site. We're 1yr+
away from being able to buy these parts, right?

Also, is anyone scaling the RISC-V up to compete with Xeon/Opteron?

~~~
vhodges
[https://en.wikipedia.org/wiki/RISC-V#Adopters](https://en.wikipedia.org/wiki/RISC-V#Adopters)

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erichocean
I'm convinced RISC-V has a strong future. Tons of momentum, and lots of well-
managed projects are building on top of it. Exciting times!

~~~
ant6n
Need arm Chromebook-like laptop that's risc-v + Linux

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microcolonel
A beautiful thing.

I can think of plenty of markets which would be glad to see this from their
SoC vendor.

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vasilia
Does someone use Chisel language for FPGA programming? I'm using Verilog for
my Altera DE1-SoC because it used in "Computer Principles and Design in
Verilog HDL".

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deepnotderp
Super sweet! Gonna get one :)

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amckinlay
Where is the management engine (ME)?

