
Flash Disruption Comes to Server Main Memory - nkurz
http://www.theplatform.net/2015/08/05/flash-disruption-comes-to-server-main-memory/
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solarexplorer
It would be nice to see how their DDR interface compares to their earlier
block level implementation. A memory module with latencies that are an order
of magnitude greater than a pagefault seems a strange idea. Especially when
the memory interface of the CPU is not aware of it.

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Vendan
From what I've seen in a quick 5 minutes of googling, 100+ microseconds of
read latency in an SSD is considered good/amazing. They listed the "Memory
Channel Storage", a different, though similar tech to the one being
introduced, as 3.3 microseconds, which is 2 orders of magnitude BETTER then a
good SSD.

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solarexplorer
Better than SSD but much slower than DDR memory. You could use the flash
memory as cache and access it within the page fault handler at block level.
That would make sense because the flash latency is much larger than the
overhead of a page fault. So why access it at "bit-level" like they pretend?

(actually that would be word-level, because DDR doesn't allow bit-level
access...)

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Vendan
Just saying, page-faults are at least 2 orders of magnitude slower then this
has the potential to be, though I would be interested in a version that
wouldn't erase on power up. I bet someone could write something for linux that
would get the whole block treated like a ram disk, and you'd probably see some
amazing performance out of it for many common things like serving web pages.
Makes me curious about designing it so you could boot straight from there and
have servers that were just mobo+ram+flashram.

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solarexplorer
3.3 microseconds latency for the flash at the memory bus are about 11,000
cycles latency @ 3.3GHz. That is quite a lot compared to a normal DDR latency
of about 150 cycles. Of course it's much better than 100 microseconds or about
330,000 cycles for a normal SSD. I would guess that the overhead for a page
fault would be around 1000 cycles.

Writing a block device for Linux so that the flash could be used as a cache or
ram disk is quite easy (speaking from experience) and I assume that Diablo has
already written one.

If Diablo had access to the memory controller inside the main CPU they could
even run the DDR as a cache for the flash memory like some giant L4 cache. In
such a scenario the DDR ram emulation would make sense...

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Vendan
A page fault is going to cost way way more then 1000 cycles, it's going to be,
at bare minimum(for major faults), your storage medium's read latency, so 100
microseconds or more. I'd think in many circumstances hitting a 3.3
microsecond latency to avoid a 100 microsecond latency is def. a good trade.
There might be an issue if you have to repeatedly pay that 3.3 microsecond vs.
one time the 100 microsecond, but that's getting into things that we can't
really know without knowing more specs about the stuff.

And I was more speaking about using it as a blazing fast non-volatile "ram"
drive. I know a standard ram drive is simple, but it'd be neat to install os
and programs and such onto a drive with 2 order of magnitude better
performance then a high-end SSD.

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yuhong
"SATA interface used by NAND flash chips"

ONFI more likely.

