
ORCA – An implementation of RISC-V intended to target FPGAs - vanjoe
https://github.com/VectorBlox/orca
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kinghajj
Why would someone use this vs Rocket/BOOM? Is it compatible with cheaper
FPGAs?

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vanjoe
Yes, it is built to be as lightweight as possible. We have used it with
wishbone devices on ICE40 chips, which are about as small as they come

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tropo
I've been wondering if one of those chips could fit a CPU.

How do you estimate this sort of stuff? I can estimate software decently, but
the penalty for being wrong is seldom so bad. With a hardware project, things
actually don't fit and you are out of luck.

Different FPGAs have different sorts of limits, not just 1 different number.
Do you go by lines of Verilog/VHDL code? Do you go by some idea of "most crazy
operation" and register width? How...?

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mechagodzilla
An fpga has finite resources (block rams, pins, logic blocks (lookup table +
flop)). If you have a good understanding of the logic you're designing, it's
not that hard to estimate resource usage. You just get used to thinking in
terms of gates, flops, etc

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vanjoe
Right, you usually have some idea of how Look up tables an n bit add
operation, or an n bit multiplexer etc takes up. You also need to take into
account how much memory and multipliers you need since FPGAs have multiplier
and ram blocks built in.

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samlittlewood
Presentation that includes size and performance figures:

[http://riscv.org/wp-
content/uploads/2016/01/Wed1200-2016-01-...](http://riscv.org/wp-
content/uploads/2016/01/Wed1200-2016-01-05-VectorBlox-ORCA-RISC-V-DEMO.pdf)

Summary: smaller and faster than PicoRV32 & Z-scale, slower but smaller than
Nios II/f.

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pawadu
Any idea why it performs so bad on ice40?

Given that ice40 is the only (unofficially) open source FPGA, I had high hopes
for the architecture...

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erichocean
Would be nice to see a change log.

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vanjoe
The biggest feature change is the addition of interrupt support. Also
stability and bug fixes.

