
New 167-processor chip is super-fast, ultra energy-efficient - Anon84
http://esciencenews.com/articles/2009/04/22/new.167.processor.chip.super.fast.ultra.energy.efficient
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jws
URL to the project: <http://www.ece.ucdavis.edu/vcl/asap/> [last updated a
year ago, does not address this latest silicon]

Hotchips presentation:
[http://www.hotchips.org/archives/hc18/2_Mon/HC18.S5/HC18.S5T...](http://www.hotchips.org/archives/hc18/2_Mon/HC18.S5/HC18.S5T3.pdf)
[also of the previous 36 processor silicon]

Looks like 64 words of instruction and 128 of data for each processor. You
will want to think "dataflow of simple DSPs" rather than "cluster of linux".

The power use is amazing. 84mW while 100% active on their 36 processor 475MHz
unit.

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chancho
Would an electrical engineer please explain why the number of cores is prime?

~~~
jws
It is a 13x13 array with 5 chopped off to make space. That goes down to 164,
but there are three special purpose processors added back in to get up to 167.

If you can open a PowerPoint presentation you can read about the chip at
[http://www.ece.ucdavis.edu/vcl/pubs/2008.06.symp.vlsi/vlsi_s...](http://www.ece.ucdavis.edu/vcl/pubs/2008.06.symp.vlsi/vlsi_symp08_presentation_final.ppt)

Also worth noting that although they do an 802.11a receiver in 20-30 cores,
they use two big chunks of special purpose silicon for a Viterbi decoder and
an FFT. I'd be curious to know how many more cores it takes without the
special purpose hardware, if it is even possible.

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listic
I wonder if this could fly.

Because the other approach very-many-cores processor design that I know of,
was by Intellasys (<http://www.intellasys.net/>), the latest company of
Forth's inventor Chuck Moore. And it seemed to have gone nowhere:
<http://www.colorforth.com/S40.htm>

The problem with this design, as I could see it, is that tiny cores can be too
small to do anything practically useful on their own; inter-processor
communication and I/O eats cycles. In Intellasys' case I guess the problems
were multiplied by the fact that it would be harder to get traction for the
chip was designed to be programmed in Forth , and Chuck Moore would settle for
nothing less.

Maybe University of California will have better chance of success, i.e. if it
has more runway to tweak their design.

Does anyone know of other very-many-cores processor chips?

~~~
JulianMorrison
IIRC the seaforth chips were designed to have blocking reactive IO at ports on
each processor, so there was no need to waste cycles waiting on IO or
explicitly driving peripherals, you just coded as if the stream was
continuous.

~~~
listic
Yes, you're right. In Seaforth's case inter-processor communication and I/O
shouldn't eat cycles on its own.

I wish we could use some of this technology.

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anigbrowl
Motorola used to do devkits for their 56k series that featured USB or RS232
connections to a box containing the DSP and a pair of audio i/o jacks with
average DACs.

This plus a front-end DSP environment like <http://synthmaker.co.uk/> would
sell like hot cakes. Update to this now please:
<http://www.ece.ucdavis.edu/vcl/asap/asap_demo_boards.html>

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stcredzero
Someone's come up with a One Instruction Set Computer for this purpose -- to
enable reconfigurable arrays of small processors for massively parallel signal
processing.

<http://en.wikipedia.org/wiki/One_instruction_set_computer>

~~~
gcheong
Not sure if this fits the bill, but your comment reminded me of it:

[http://www.cellmatrix.com/entryway/products/concepts/intro1....](http://www.cellmatrix.com/entryway/products/concepts/intro1.html)

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njharman
> just three months to write "a fully compliant Wi-Fi transmitter

That _seems_ like a long time. But I don't know how hard a fully compliant
"Wi-Fi" transmitter is.

~~~
aswanson
It's fairly involved:

[http://standards.ieee.org/getieee802/download/802.11g-2003.p...](http://standards.ieee.org/getieee802/download/802.11g-2003.pdf)

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JulianMorrison
Sounds like the ideal target for the spatial composition of Haskell's "lava" (
<http://raintown.org/lava/> ).

