
Run-ahead transfer prediction in the Mill CPU architecture - signa11
http://ootbcomp.com/docs/prediction/index.html
======
unwind
The point of the page is that the Mill CPU (of which I know almost nothing, I
don't think I had heard of it before) does _not_ do branch prediction, instead
it focuses on the memory traffic and does _transfer prediction_ :

 _[...] it predicts transfers rather than branches [..]_

So, the title of the post is annoyingly misleading and I would really
appreciate it if someone could edit.

~~~
Mindless2112
Did you watch the video of the talk? The wording in the summary is a bit
misleading.

The Mill does exit prediction on extended basic blocks -- it predicts which
branch will be taken rather than if a particular branch will be taken, and it
can chain these predictions.

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Symmetry
I've gotta say, organizing the code in terms of EBBs instead of calls makes
lot of the features in earlier videos make a lot more sense. I have no idea
how they'll be able to handle interrupts or avoid having to deal with
interrupts, but I'm sure they have a story for that. Really gotta re-watch the
memory video now.

Hand coding assembly for this would be really painful, but we already knew
this with the belt. The Mill really seems to have been designed with compilers
in mind.

~~~
igodard
Sure was! I write compilers; much better to have the hardware team do the work
:-)

Mill interrupts are nothing but involuntary function calls, and handlers are
perfectly ordinary functions. There are no privileged operations; all security
is memory based - an upcoming talk will cover that. ootbcomp.com/mailing-list
to get talk announcements.

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foxhill
until i can see some decent attempt at an implementation (either in an FPGA,
or an open-source simulator), where i can see cycle counts for some
benchmarks, i will be erring on the side of scepticism, primarily because this
CPU design still has some major issues (in my opinion).

compilers should _not_ be deciding instruction scheduling - this is exactly
the issue that kills VLIW ISAs (e.g Intel's Itanium CPU, AMD's Northern
Islands and prior GPUs) when used for anything other than DSP-like codes. as
much power and die space as an out-of-order schedular takes, run time is the
only time (really) that the order of operations can be determined (in my
humble opinion).

~~~
chongli
Have you watched all of the lectures? Your questions are answered in them. The
Mill is not at all like other VLIW architectures.

~~~
DSingularity
He is talking about the fundamental problem of VLIW architectures. They rely
on the static scheduling of programs to enable instruction level parallelism
-- which is critical to performance. Scheduling is an NP Complete problem.

~~~
Dylan16807
The harder the problem, the worse it's going to be to calculate it on the fly.

~~~
foxhill
not true. an OoO scheduler has a fixed window size with which to re-order. and
as soon as you have data-dependent branches or dependencies, your compiler
cannot possibly schedule instructions effectively.

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jstclair
I found it interesting that in a presentation given in 2013, the (only)
comparison to a competitor's processor was the Pentium 4 (Prescott) from
2004(!).

~~~
Symmetry
He's just using the P4 because it has the longest mis-predict penalty of any
recent mass produced CPU. I'd guess that the Mill is going to be clocked
fairly slow given the cycle latency numbers I'm seeing so I wouldn't be
surprised if the Mill's 5 cycle mis predict penalty came out to the same time
delay as a 10 cycle penalty on a Sandy Bridge.

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brainburn
Are there architectures where a programmer can just use a specific opcode to
inform the cpu what's most likely?

~~~
seanmcdirmid
Yes, its called static branch prediction. I'm not sure how popular it is in
modern ISAs, but MIPS and SPARC had such instructions.

~~~
_delirium
The Pentium 4 introduced prefix opcodes that hinted that the next branch would
be likely or unlikely to be taken. These are still legal, but afaik post-
NetBurst CPUs ignore them, and Intel's optimization manuals have dropped
mention of them.

