
Intel delays chip-making changes - willvarfar
http://www.bbc.com/news/technology-33549916
======
walterbell
Bunnie Huang on Moore's Law,
[http://www.wired.co.uk/magazine/archive/2015/08/features/moo...](http://www.wired.co.uk/magazine/archive/2015/08/features/moores-
law/viewall)

 _“.. WIRED buys the iPhone 6 schematic book (above) for 25 RMB (£2.70) .. It
's like getting a master class on circuit design .. for £2.70, engineers in
China can get a leg up on the best and brightest university-educated kids by
studying these designs ..

.. there are established, legitimate businesses that earn their keep creating
schematics from circuit boards. As the pace of Moore's law diminishes,
learning through reverse engineering will become increasingly effective, as
me-too products will have a larger market window to amortise reverse-
engineering efforts before the next new thing comes along.

.. Even a modest deceleration of Moore's law can have a dramatic effect: a
five per cent reduction in the pace of gate-length shrinkage -- from 16
percent to 11 per cent per year -- increases the available time to develop
products within a technology generation by 50 per cent, from two years up to
three.

.. Instead of running in fear of ­obsolescence, open-source hardware
developers now have time to build communities around platforms; we can learn
from each other, share blueprints and iterate prototypes before committing to
a final design._”

~~~
tzs
Where did the designers who designed the iPhone 6 learn?

~~~
rer0tsaz
House for the Feeble Minded.

~~~
shalmanese
This is a reference to the classic Asimov short story Profession
([http://www.inf.ufpr.br/renato/profession.html](http://www.inf.ufpr.br/renato/profession.html))
and should not have been downvoted.

~~~
walterbell
Thank you for that story, akin to China Mieville's concept of "breach" in _The
City and The City_.

------
Animats
Putting huge numbers of ordinary CPUs on a chip only helps until the memory
bus runs out of bandwidth. For GPU-type devices, the computation/memory
request ratio is higher, so GPUs can have many more compute units. GPUs are
now used for lots of other parallel computations, and there's room for
expansion in pure-computation GPU-like devices that don't drive a display.

Historically, unusual massively parallel architectures have been commercial
failures. "Build it and they will come" doesn't work there. There's a long
history of weird supercomputer designs, starting with the ILLIAC IV and
continuing through the Ncube. The only mass-market product in that space was
the PS3's Cell, which was too hard to program and didn't have enough memory
per CPU. (The Cell had only 256KB (not MB) per Cell CPU.)

The next big thing may be parts optimized for machine learning. That's
massively parallel. We may, at last, see "AI chips".

~~~
nickpsecurity
I mainly agree with that sentiment. What do you think about the TOMI tech,
though?

[http://www.venraytechnology.com/Making%20a%20Frosted%20Cake%...](http://www.venraytechnology.com/Making%20a%20Frosted%20Cake%20and%20Processor%20in%20Memory.htm)

I think it was a brilliant reframing of the problem: move CPU's to memory with
its cost-benefit analysis rather than vice versa (status quo). The design also
achieves what some exascale proposals are _trying_ to achieve with R&D in
terms of better integrating CPU & memory with lower energy. It's also
massively parallel (128 cores) and optimized for big data. Close to your next
big thing.

It's main risk right now is that DRAM vendors are more conservative and mass
market than most fabs. There's not all this MOSIS, multi-project runs, and so
on. Their low-volume cost is currently high (tens of thousands). They might be
facing a chicken-and-egg problem in terms of hitting enough volume to get a
nice, production deal. I do like their tech and think it has far more
potential than what they're doing right now.

~~~
minthd
>> It's main risk right now is that DRAM vendors are more conservative and
mass market than most fabs.

recently micron released a memory based processor/state-machine architecture
called "automata". This might be a good sign that the problem you mention will
be solved.

~~~
nickpsecurity
That was a _really neat_ processor. That's what happens when hardware vendors
look at FSM problems their way instead of support software developer's way (eg
C lang). The best bet might for those using memory fab tech to haggle one of
the fabs to do MPW's on, say, one production line. Fab as a whole can keep
cranking out tons of memory chips, new players can crank out theirs, and any
risk is very limited.

The problem has already been solved outside memory fabs several times over.
The memory fabs just need to take some steps, themselves. If I were them, I'd
push I.P. vendors to follow path of Micron and Venray just to get more fab
customers.

------
dragonwriter
> When first formulated by Intel co-founder Gordon Moore 50 years ago, this
> suggested that chip power could double every 12 months.

Actually, when first formulated by Moore, it was that transistor density
doubled every 12 months (he later revised it to 2 years.)

Per Wikipedia, it was David House who applied it to performance (and, when he
did, it was with an 18 month timeframe.)

~~~
tedsanders
>Actually, when first formulated by Moore, it was that transistor density
doubled every 12 months

No, it was the number of integrated components on a chips, not transistor
density.

Anyway, I think the article's statement is fine. Doubling the number of
components _would_ suggest that performance doubles too.

~~~
brianwawok
Does a car with 12 cylinders drive twice as fast as one with 6? Or accelerate?

Performance is too complicated to just say "CPU X doubles perf".. because
likely some perf cases stayed the same, some got better, but some got worse
(think deep pipelines).

------
jolan
I hope Intel uses this pause to implement things like DJB's suggestions for
the Intel instruction set:

[http://blog.cr.yp.to/20140517-insns.html](http://blog.cr.yp.to/20140517-insns.html)

~~~
notatoad
When a company delays a product launch, it's usually because they have too
much work to do, not not enough.

~~~
awalton
Intel didn't delay a product launch, they delayed a PROCESS launch, which is a
much bigger deal given their previous cadence towards the bottom. Physics is
kicking the silicon industry's ass.

Meanwhile, the guys doing HDL and verification at Intel don't even notice the
process delay, they just go about what they're doing, leaving them plenty of
time to implement whatever (namely GPU improvements, which is what most of the
industry has been requiring for newer Windows/Mac OS Xes).

------
higherpurpose
> When first formulated by Intel co-founder Gordon Moore 50 years ago, this
> suggested that chip power could double every 12 months.

What? I don't think it was ever 12 months, but 18-24 months.

> Now, improvements are expected approximately every 24 months.

No, they said it will take 2.5 years now instead of two.

[http://seekingalpha.com/article/3329035-intels-intc-ceo-
bria...](http://seekingalpha.com/article/3329035-intels-intc-ceo-brian-
krzanich-on-q2-2015-results-earnings-call-transcript)

I wouldn't expect the 10nm chips at least until mid-2017, which should put
Intel neck in neck with TSMC and Samsung's 10nm processes, which at most might
be launched a few months later.

It also looks like IBM and its partners (Samsung/Global Foundries) will
actually _beat_ Intel to 7nm (probably early/mid 2019 for Samsung/GF - late
2019/early 2020 for Intel).

While IBM is talking about EUV lithography, Intel still seems to be
complaining about multi-pattern lithography, so it seems pretty clear that
Intel is behind IBM for 7nm. They also haven't said anything yet about what
materials they'll use for 7nm transistors, just that they will require
something different than Silicon.

The best part about this is that now Intel can't hide the x86 baggage in
mobile behind its one generation ahead process node, which made Atom more or
less competitive (at least in performance and power consumption, but not in
price).

With ARM chips on very similar process nodes and arriving at the same time on
the market, there should be no contest for the ARM chips in mobile.

~~~
robin_reala
Also it’s not ‘chip power’ but ‘number of transistors’. Common
misunderstanding.

~~~
jfoutz
Yeah, even without the step to 10nm, the third generation 14nm chips will
probably be a bit faster than the second generation. Density can't be improved
but there is surely efficiency to be realized.

------
nickpsecurity
It doesn't really bother me as we've seen it coming for years. Anyone playing
smart is not relying on a process node jump rather than better architected
systems. I think the fact that they bought Altera and might do on-board FPGA
logic more than balances out here. I'll take an FPGA-accelerator on their on-
chip NOC over an incremental increase in performance/energy any day. Even big
companies such as Microsoft are wisening up to the fact that a proper split
between CPU and FPGA logic has significant advantages.

I'm curious to see what AMD will do in response to both the delays and Altera
acquisition. Wait, a quick Google shows AMD to be so bad off that a FPGA
company (Xilinx) might buy them. Lol. Ok, well the market is about to get
interesting again one way or the other.

~~~
AnimalMuppet
I don't even want to think about the antivirus implications of running FPGA
code.

~~~
monocasa
Eh, as long as it's on the other side of a hardware based IO-MMU, I'm not
super concerned.

~~~
nickpsecurity
Those are overhyped so as to be buzzwords. All the IO-MMU really does is make
the data come to and go from a certain point of memory. What it does when it
hits the system software or applications is a whole, different risk area. See
OS process separation vs all the ways it's bypassed with app & kernel-level
vulnerabilities.

So, you consider that the FPGA might sabotage data you send through it or what
comes from it. Be monitoring or doing validation on both.

------
RockyMcNuts
Kind of wondering what this means relative to competitors.

Intel is at 14nm now since 2014 and Samsung recently got to 14nm in Galaxy S6?
And Samsung and TSMC have similar roadmaps for 10nm? So conceivably others
might be catching up to Intel in fab? Say it ain't so? (I'm asking because I
don't follow these things closely but that was the picture I got.)

If Intel doesn't maintain their big edge in fab I'm not sure they can charge
the kind of premium they have been. 64-bit ARM is going to start looking
mighty attractive for a lot of use cases.

~~~
amaranth
Samsung's 14nm isn't as dense as Intel's because it's sort of a hybrid of a
20nm process and a 14nm one. TSMC's 16nm is apparently just their 20nm process
but with FinFETs so will be the least dense of the three. I suspect their 10nm
will also end up less dense than what Intel puts out but we'll have to wait
and see on that.

As far as timetables for production, recent rumors put TSMC's 10nm plans at
2017 as well, delayed from their original Q4 2016 goal. Haven't see anything
about delays on Samsung's side so they might actually get there first.

------
whazor
I think the current techniques are becoming too complicated and Intel is now
fully going to focus on EUV. The new EUV machines are reaching 70%
availability on average, according to the producer ASML[1].

[1]
[http://www.asml.com/asml/show.do?lang=JA&ctx=5869&rid=52080](http://www.asml.com/asml/show.do?lang=JA&ctx=5869&rid=52080)

------
narrator
If Moores law ends with 14nm, I wonder what we'll be doing 10 years from now.

~~~
mrb
It is very obvious what we will be doing, and this has been discussed many
times: add more metal layers.

Intel processors only have a dozen layers which stack up to less than ~1 um.
The numbers of transistors/layers could in theory be increased by 1000x if the
layers were stacked ~1 mm high. How to do this with lithographic processes is
an open question, but it is absolutely doable in theory. No physical limits
prevent us from doing that.

~~~
knd775
Heat would be a massive issue with more layers, right?

~~~
chucky_z
From a purely seat-of-my-pants-im-trying-to-remember-college point of view, I
believe the heat is caused far more by pumping tons of electricity, rather
than physical size/layout.

A big problem (and also probably why they're so thin) is that at a certain
size latency becomes a _huge_ issue. This is where clock speed increases come
into play (electrons move faster) along with die decreases (electrons can
travel shorter distances).

If you can run 100mph, but you have to run 200 miles vs. someone who can walk
1mph, but only has to walk 10 feet... I wish I had some more concrete examples
but I can't come find anything off the top of my head.

~~~
t0mbstone
Heat is caused by resistance when the electricity moves through the metal. The
more metal the electricity is flowing through, the more material there is
incur resistance and generate heat, correct? If so, then more layers = more
heat.

~~~
ars
> Heat is caused by resistance when the electricity moves through the metal.

Sort of. But if you _reduce_ resistance you increase heat since more current
will flow.

On the other hand, if you _increase_ resistance AND also keep the current the
same _then_ you'll get more heat. But! to keep that current constant you must
increase the voltage.

So it's not so simple as "resistance = heat".

> The more metal the electricity is flowing through, the more material there
> is incur resistance

Depends on if the metal is in parallel or series. If in parallel, then the
more metal the lower the resistance, if in series then higher resistance.

> If so, then more layers = more heat.

Right result, wrong method of getting there. More layers (which would be in
parallel) would be _less_ resistance. But less resistance means more current
flow (since they'll keep the voltage the same), and more current flow means
more heat.

------
MCRed
I saw another article that referred to this as a sign of the slowing of
Moore's law. However, Moore's law has its variances so I'm not really worried
about that.

What I do wonder about is why we are not seeing more cores as we go down to
smaller nodes. 2 and 4 cores are common now, but have been seemingly for a
decade. Why aren't we seeing 8, 16, 32 and 64 cores? If you reduce the feature
size and effectively thus double the surface area available, why not increase
the cores? It seems the new area is going into integrated GPUs (never as good
as discrete GPUs, but certainly cheaper) and cache. Cache can improve
performance but not like more cores. While intel does a tick/tock design
revision, each core seems to grow to fit the available space, with only adding
a few instructions, which only add marginal utility. Not the same as doubling
the number of cores, which would double theoretical performance.

Under Erlang/Elixir, we are able to get close to linear speedup from
additional cores. I understand other languages struggle with multi-threaded
programming, but should CPU designs be hobbled simply because the software
industry is not where it should be?

Am I missing something?

~~~
dragonwriter
> Why aren't we seeing 8, 16, 32 and 64 cores?

Intel has 8-core i7s, up to 18-core Xeon processors, and up to 61 cores in
Xeon Phi coprocessor packages.

> If you reduce the feature size and effectively thus double the surface area
> available, why not increase the cores?

Because, outside of narrow domains, software that can effectively use lots of
cores doesn't exist, so you don't provide good bang for the customers buck by
doing that. For most customers, there's no utility for that.

> Cache can improve performance but not like more cores.

And vice versa -- more cores can improve performance, but not like cache.
Which is more useful depends on software and workloads.

> Under Erlang/Elixir, we are able to get close to linear speedup from
> additional cores.

On the right kind of workloads. And, the people with those kind of workloads,
have many-core processors available.

~~~
cft
Any web server that serves at scale can readily use 1024 cores... Nginx,
servers built in Go, Erlang and many more. It would reduce hosting costs and
complexity substantially.

~~~
JoachimSchipper
It's not as easy as you seem to think to e.g. (de-)multiplex a single TCP port
to/from 1024 cores, and that's before you actually try to keep any application
state in sync. _Lots_ of stuff breaks at that level of concurrency.

~~~
socceroos
First part makes sense, but the last part doesn't. Keeping application state
in sync doesn't need to affect the throughput of events coming out of a multi-
threaded application.

------
harshreality
Chris Mack has been vocal on this. And not only was he probably right about
Moore's Law (defined as scaling that decreases the cost per transistor) being
dead last year[1] (the cost per transistor curve has been flattening out), but
now Intel can't even keep pace with process shrinks _at any price the market
will bear_.

That doesn't mean progress will _stop_ , however[2], but rather that progress
(and a revised definition of Moore's Law) will be defined by chip redesigns
and particularly specialized functionality that doesn't take many gates to
implement but makes chips more valuable.

[1] [https://www.youtube.com/watch?v=IBrEx-
FINEI#t=1m13s](https://www.youtube.com/watch?v=IBrEx-FINEI#t=1m13s)

[2] [http://spectrum.ieee.org/semiconductors/processors/the-
multi...](http://spectrum.ieee.org/semiconductors/processors/the-multiple-
lives-of-moores-law)

------
aburan28
I just read about how they were delaying the AVX512 until 'Knights Landing'
(Xeon Phi) and with Haswells mediocre improvements Intel has really not come
up with anything substantial in years. Hopefully the recent Altera acquisition
will help them innovate

~~~
chinhodado
> with Haswells mediocre improvements Intel has really not come up with
> anything substantial in years

Not really. This statement is true regarding desktop CPUs, but we all know for
at least five years now Intel's focus is not desktop CPU performance anymore,
but mobile. Hence most of the improvements we see are for mobile, like better
embedded graphic (Sandy/Ivy Bridge forward) and improved power consumption
(Haswell).

~~~
wtallis
Intel really shouldn't get credit for the Sandy Bridge IGP, because that's
just where they caught up to the NVidia IGPs that they'd banned. The first
generation of Core series mobile chips represented a major step backwards from
the user's perspective because Intel would no longer let NVidia make chipsets,
so Intel's IGPs no longer had to compete against the GeForce 9400M and 320M.
Ivy Bridge was the first time Intel actually moved the market forwards in
terms of mobile IGP performance.

------
saosebastiao
But will it have non-disabled HTM?

EDIT: Its a real question. Working HTM would negate pretty much any bad news
from Intel in my mind.

------
oldmanjay
Did the BBC forget a comma in the title? I'm having a hard time parsing it.

Edit: or perhaps a dash? Really it's just a horrible title all around.

~~~
Cyph0n
Yes, a dash; “chip-making changes” makes much more sense. Horrible title
indeed.

------
aburan28
Moore's law plateaued years ago. Sure they are adding more cores but thats
because they have made no progress on the clock speed in nearly a decade.
FPGA's are going to be the next go to for performance until cpu clock speeds
improve

~~~
mikeash
Moore's Law is about transistor count, not clock speed. They used to go
together, now they don't, but Moore's Law is still doing OK. This is an
indication that it may be coming to an end, finally.

~~~
bargl
Richard from DotNetRocks does an Awesome show on this.
[https://www.dotnetrocks.com/default.aspx?showNum=1130](https://www.dotnetrocks.com/default.aspx?showNum=1130)

