
Linux-running MIPS CPU available for free to universities – full Verilog code - alexvoica
http://blog.imgtec.com/mips-processors/mipsfpga-opens-up-the-mips-architecture-to-universities-worldwide
======
rasz_pl
>teaching MIPS as the most elegant example of a RISC processor

elegant as in simplified to the bone, but also a market failure compared to
not so reduced ARM

>You’ve been here for two months, and now you want to give our IP away!

haha, nice try Imagination Technologies, you arent giving anything for free.
Later on in the blog post is a mere mention of all the proprietary IP, patents
and licenses they are NOT granting/licensing. This is a huge win for
Imagination, somehow they managed to convince a ton of universities to base
their curriculum on Img proprietary design, this is as big as Nvidia "helping
out" with heterogenous computing courses resulting in universities universally
(hah) ignoring OpenCL, and exclusively teaching proprietary CUDA.

~~~
userbinator
_but also a market failure compared to not so reduced ARM_

There are tons of MIPS SoCs out there, mostly in various Chinese devices (the
ones which are too cheap for ARM?) so I wouldn't say they failed completely,
but in terms of performance or power efficiency MIPS is definitely behind
compared to ARM or x86:

[http://www.extremetech.com/extreme/188396-the-final-isa-
show...](http://www.extremetech.com/extreme/188396-the-final-isa-showdown-is-
arm-x86-or-mips-intrinsically-more-power-efficient)

AFAIK all the patents on early x86 have expired, and IMHO that's a far more
interesting architecture to study...

[http://zet.aluzina.org/index.php/Zet_processor](http://zet.aluzina.org/index.php/Zet_processor)

~~~
solarexplorer
I disagree. This comparison is extremely unfair because they used a chineese
clone instead of the real CPU/compiler from MIPS...

~~~
userbinator
What would the "real CPU from MIPS" be, and how much difference would that
make...? Loongson is a licensed design.

As for compilers, neither ARM's nor Intel's compiler were used for the other
CPUs, so I think that's a fair comparison. ...and I thought one of the reasons
to choose a very simple RISC like MIPS was that its simplicity made compiler
optimisations easier?

~~~
solarexplorer
AFAIK Loongson just licensed the patent necessary to implement the MIPS ISA
but the implementation was done by chineese academia without any intervention
from MIPS. You cannont judge the quality of MIPS processors in general by
looking only at one chineese clone...

------
cbd1984
Given that OpenCores has a ton of open-source cores on it already, why does
this matter?

[http://opencores.org/](http://opencores.org/)

~~~
alexvoica
This matters because you get access to the full Verilog code for a modern CPU
and a complete toolchain to boot Linux and write software. This also matters
because these two vital elements (hardware and software) are coming straight
from the source.

Open cores might get close to an implementation, but usually they break code
compatibility or implement older versions of the architecture, which limits
your ability to run (or update to) a modern Linux kernel or use a standard
toolchain from established providers.

~~~
solarexplorer
But the reason they break code compatibility or implement older versions of
the architecture is that parts of the ISA are patented by MIPS. Other ISAs
like OpenRISC, SPARC and RISC-V don't have these limitations.

~~~
alexvoica
Yes, that is true. MIPS Technologies held patents on the MIPS ISA and most of
those were transferred to Imagination when we completed the acquisition.
However, many of these patents are also owned by an internationally-backed
consortium which includes ARM: [http://www.arm.com/about/newsroom/arm-
announces-participatio...](http://www.arm.com/about/newsroom/arm-announces-
participation-in-a-consortium-to-acquire-rights-to-mips-technologies-mips-
portfolio.php)

I think this announcement is particularly important because it gives students
the chance to study a piece of RISC history. When I was in University studying
for my Electrical Engineering degree, we were asked to clone an 8-bit MCU.
While it was a useful exercise, everyone was dreaming of seeing a fully open
MIPS CPU. We were taught it yes, in the Computer Architecture course, but
never got a chance to see any RTL code.

RTL code + slides beats slides in my book so that's why I feel this
announcement is so important for me, personally - but also for universities
worldwide.

~~~
solarexplorer
You are right, I would haved loved this as a student too. But today there are
real open source alternatives. Especially in an academic environment it is
essential to be able to modify and share source code without restrictions so
you can experiment and collaborate as you wish. E.g. students should be able
to add custom instructions, experiment with cache architectures, build
multicores, etc. All with the architecture they learned about in class.

~~~
alexvoica
So back to your point, a lot of universities teach computer architecture based
on MIPS since it was defined by Patterson and Hennessy (Hennessy also co-
founded MIPS Computer Systems Inc. and went into production with MIPS R2000
based on the MIPS I ISA).

MIPS is a very popular architecture, having shipped in over 800 million
devices last year.

Now these universities that teach MIPS in their coursework have a chance to
enhance the course by giving students access to the RTL too. When those
students leave university, they will have the skills required to understand
and work with a commercially-available CPU architecture.

~~~
rjsw
David Patterson lead the Berkeley RISC project which is the ancestor of SPARC,
he didn't have anything to do with MIPS.

~~~
alexvoica
Patterson and Hennessy worked together to write
[http://www.amazon.com/Computer-Architecture-Fifth-Edition-
Qu...](http://www.amazon.com/Computer-Architecture-Fifth-Edition-
Quantitative/dp/012383872X)

The vast majority of practical references in the book are based on the MIPS
architecture (as an example of a RISC processor).

~~~
rjsw
The MIPS architecture isn't defined by that book. Earlier editions used DLX
for the practical examples.

------
glabifrons
Hopefully, this will get more traction than OpenSPARC did. I was really
surprised that one didn't get adopted heavily. It runs Linux (and Solaris and
OpenBSD), is multicore, CMT, low power.

Reference:

[http://opensparc.net/](http://opensparc.net/)

[http://www.oracle.com/technetwork/systems/opensparc/openspar...](http://www.oracle.com/technetwork/systems/opensparc/opensparc-
operating-systems-1544128.html)

~~~
alexvoica
There is also the RISC-V ISA ([http://riscv.org/](http://riscv.org/)) being
developed at Berkeley and the lowRISC SoC incorporating a 64-bit RISC-V CPU
([http://www.lowrisc.org/](http://www.lowrisc.org/)) by a team in Cambridge.

------
alexvoica
The package includes a microAptiv CPU (MIPS32 Release 3) written in Verilog, a
getting started guide, and various files for debugging, simulation and
synthesis (free SDK, tools from Modelsim and Xilinx, etc.)

