
Intel's 10nm Is Broken, Delayed Until 2019 - ry4n413
https://www.tomshardware.com/news/intel-cpu-10nm-earnings-amd,36967.html
======
nimos
I think 2019-2020 will be super interesting for hardware. Intel, Samsung,
Gloflo, TSMC could all have competitive 7/10nm nodes. Unless either Intel or
AMD makes some crazy IPC gains they should be fairly competitive with each
other and it will be interesting to see what the ARM giants can do as well.
Hopefully Chinese investment into DRAM/NAND starts to come to fruition by then
too.

~~~
hajile
We're to a point where N nm nodes is meaningless. I want a list of feature
dimensions to compare. That's the only meaningful way to do a rough comparison
these days.

~~~
lmilcin
You can think of power consumption as a resource -- if you reduce power
consumption of existing features you can put more new features. The actual
size isn't really that important (other than the cost of silicon wafer).

To significantly reduce power consumption you need improved process and this
is where smaller nodes are so important, because they are currently the only
really viable way to significantly reduce power consumption.

~~~
indiv0
Now I kind of want to see the data on power consumption/transistor count over
time.

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hinkley
“Because of the production difficulties with 10nm, Intel has revised its
density target back to 2.4X [from 2.7X] for the transition to the 7nm node.”

Ouch. A day late and a dollar short.

They claim that this new node will still be better than TSMC’s new node, but
we are now in leapfrog mode aren’t we? Where you have a year advantage on your
competitor and then they will have the best tech but you’ll be halfway to
unseating them again?

~~~
mtgx
And I bet they just mean TSMC's 7nm node there, but that's very misleading. By
the time Intel has its 7nm node ready, TSMC will be ahead with its 5nm node.

~~~
matthewmacleod
That’s possible, but intel’s 7nm is likely to be better than TSMC’s 5nm
regardless

~~~
hinkley
Can Intel work apace on their 7nm node when the previous one is behind
schedule by two years, or does this derail those plans?

~~~
eco
I'm no expert on this but I do know that their 7nm will switch to their long
in-development EUV lithography process. I'd assume the work on 10nm is
completely separate from their work on 7nm (there are even rumors that they'll
just abandon 10nm if 7nm is ready before they work out the problems with
10nm).

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codemusings
Can someone explaing why it's important to increase the density instead of
increasing the size of a CPU?

Knowing nothing about chip design I'm probably thinking about this the wrong
way but socket backwards compatability aside is it not feasible to simply
increase the chip size? Is a higher density more rewarding?

~~~
Nokinside
Power, heat and the speed of electrical signal.

Power use increases quadratically with voltage. You want small transistors to
keep the voltage and power use from getting out of hand. You also need to
increase voltage if you want to increase clock speed.

Electric signal travels in a conductor roughly 15 cm/nsec. With 3 GHz clock
speed the electric signal travels travels roughly 50 mm in one clock cycle.
Largest microchips are 30 mm across. You can't double the dimensions without
dealing with the signal lag. Delivering the clock signal to every part of the
chip in sync is already a problem. Modern microchips use lots of extra
circuitry just to deliver the clock signal properly.

~~~
fyi1183
Do you have a good source on how clocks work in modern designs? From the high
level down to the actual circuits?

I've always wondered why you can't generate clocks locally, but in a
synchronized way. So basically like clock regions, but without having to add
extra logic for data that goes between regions.

~~~
dragontamer
You can do this. Its called a "bus". CPUs communicate over a bus (ex: AMD's
SerDes, which creates the Infinity Fabric. Or Intel's "Mesh Network") with
each other on the die itself.

CPU Cores use a singular clock. But when cores communicate or the L3 cache
communicates (cache coherency is needed if you want that mutex / spinlock to
actually work), then you need some kind of communication mechanism between the
CPU Cores. Those clocks are likely "locally generated", but there needs to be
a translation mechanism between Bus -> Core.

~~~
fyi1183
It's possible I misunderstand you, but I don't think we're talking about the
same thing.

With buses, you have different clocks and data moves between them. Like you
said: CPU core 1 has its own clock, the bus between them has its own and
different clock, and then CPU core 2 has its own clock which is yet again
different. And in those cases you actually _want_ different clocks, because
you want to be able to boost CPUs independently from each other.

What I meant goes in another direction: instead of having a single powerful
clock source for e.g. a CPU core, you have multiple smaller clock sources
distributed throughout the core, but synchronized to each other so they run at
the same frequency and phase. So data can move freely like it does today, but
clock signals don't have to be distributed as far, which would hopefully make
clock distribution easier and less power hungry.

It seems like such a thing should be possible, but perhaps there are good
reasons why it isn't done?

~~~
dragontamer
Two things:

1\. Clocks don't use a lot of power. Think of a pendulum: there's a lot of
movement but the energy constantly swings between gravitational potential
energy and kinetic energy. Although there's lots of movement, the device uses
very little energy. Similarly, a clock circuit (called an oscillator) barely
uses any electricity: it mostly "Swings" energy back and forth between an
inverter and a capacitor.

2\. Distributing a clock over a long distance similarly uses very little power
(!!) due to transmission line theory. You can effectively use the parasitic
capacitance in wires themselves to effectively do this pendulum effect for
efficient long-distance transmission of clocks. See:
[https://en.wikipedia.org/wiki/Transmission_line](https://en.wikipedia.org/wiki/Transmission_line)

This gif shows an animation of the pendulum effect in a longer-transmission
line:
[https://upload.wikimedia.org/wikipedia/commons/8/89/Transmis...](https://upload.wikimedia.org/wikipedia/commons/8/89/Transmission_line_animation_open_short2.gif)

\----------------

I guess things could be de-sync'd for more efficiency. But your question is
kind of like "Well, can't we get rid of V-Tables in C++ to make branch-
prediction more efficient??"

I mean, we can. But V-Tables / Polymorphism really doesn't take a lot of time.
We only do that if the performance gain really matters.

~~~
fyi1183
Interesting, thanks. I'll see if I can grok this from the link you gave.

I do have one follow-up question though: I was under the impression that clock
trees contain repeaters in the form of CMOS inverters. Wouldn't those have
dynamic leakage which the transmission line stuff doesn't account for?

~~~
dragontamer
I'm not really an expert at the VLSI level, I'm simply thinking from a PCB-
perspective (and I just know that some of the same issues occur in the smaller
chip-level design).

From my understanding: yes, the CMOS inverters will certainly use power. But
you can minimize the use of them through some passive techniques.

Looking into the issue more, it does seem like a naive implementation of
synchronized clocks can become costly. But at the same time, I'm seeing a
number of research papers suggesting that people have been applying
transmission-line techniques to the clock distribution problem.

I've always assumed that it was something that was commonly done at the chip
level, but apparently not. These papers were published ~2010 or so.

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hindsightbias
If necessity is the mother of invention, then we'll need a lot better software
shortly.

~~~
tzahola
Bye bye JavaScript

~~~
bearjaws
Sure Javascript could be more efficient but it's not like everyone developing
it is waiting for the 2nm Intel process to fix it...

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FBISurveillance
It seems like we're going to have to stick to 16GB of RAM on MacBook Pro for
another 1.5 years or so, aren't we?

From what I understand LPDDR4 as part of Cannon Lake is directly affected by
this delay.

~~~
dasmoth
_From what I understand LPDDR4 as part of Cannon Lake is directly affected by
this delay._

Do we have confirmation of this? It seems startling to release yet another
generation of laptop CPUs without this... but I admit I can’t find anything to
to the contrary.

Pretty much anyone building mid-to-high-end laptops must be livid.

~~~
ksec
Coffe Lake does not support LPDDR4. Cannon Lake do support LPDDR4 but is now
delayed. As a matter of fact I am wondering if they might skip Cannonlake and
go Icelake instead.

There is no other rumoured "lake" in between, so yes, another generation
without 32GB RAM Laptop.

These information are widely available everywhere, not sure what you want as
confirmation.

~~~
dasmoth
The linked article mentions “Whiskey Lake” as an intermediate 14nm range
(actually it says “desktop”, but I’ve seen it mentioned in a laptop context
elsewhere). But I fear you’re right that LPDDR4 support is still being left
for Coffee Lake...

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loser777
A good time to bring up: [https://newsroom.intel.com/editorials/moores-law-
setting-the...](https://newsroom.intel.com/editorials/moores-law-setting-the-
record-straight/) >Second, in today’s world Moore’s Law can be delivered only
by a few companies. Every new process node gets harder and therefore more
expensive. [...] >So, no, Moore’s Law is not ending at any time we can see
ahead of us.

while Moore's original paper:
[http://www.monolithic3d.com/uploads/6/0/5/5/6055488/gordon_m...](http://www.monolithic3d.com/uploads/6/0/5/5/6055488/gordon_moore_1965_article.pdf)
was always about the trend of putting _more_ components in a chip being more
cost effective than keeping the number of components constant. Surely if this
were still the case we'd have seen Skylake++++ with cores << n by now.

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numbsafari
Does this create a situation where Apple will be forced to switch away in
order to differentiate, or does Intel plan to offer other kinds of
improvements to their larger customers? Sounds like greater vertical
integration will become a key differentiator. Admittedly, if the gaps between
ARM and x86 chrome books are any indication, there’s still some room for Intel
to be competitive. But does that hold for someone targeting a higher price
point and with more control end-to-end?

~~~
swagtricker
Apple has already announced that they'll start using their own chips by 2020 -
Intel's problems may be part of the reason why:
[https://9to5mac.com/2018/04/02/report-apple-to-begin-
switch-...](https://9to5mac.com/2018/04/02/report-apple-to-begin-switch-from-
intel-chips-in-macs-by-2020/)

~~~
redial
Apple has announced no such thing.

I suggest you actually read the article you linked.

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wolfi1
Are we talking about the lithographics process itself as a problem or other
manufacturing problems like VIAs, etching, diffusion? The article is a liitle
bit vague on the actual problems Intel is experiencing. But I doubt Intel will
us, anyway ;)

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bitL
So only NUCs will get Cannon Lake after all? With rumors that it contains a
discrete Radeon 500 GPU it might be the first cheap Steam Box for everyone...

~~~
sliken
Ha, "cheap". Have you looked at the AMD+Intel hybrid CPU prices? I don't think
either AMD or Intel is particularly interested in that being a price/perf
leader. Especially from the AMD side who already sells zen CPUs with AMD GPUs
inside.

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HugoDaniel
Ok, so they are delaying it again without a reasonable explanation why except
that "it is hard". But the real question is:

Does it meltdown ?

~~~
jlebrech
your meltdown question gave me an idea, what if they had extremely fast cpu
that were designed to meltdown and you use them like a consumable.

~~~
sp332
I think a missile designer did this one time. The missile wasn't expected to
exist very long after it was turned on, so they cranked up the power on the
CPU and didn't include much of a heatsink. Saved weight but testing was very
expensive.

~~~
cesarb
It was memory, not CPU:

[https://groups.google.com/forum/message/raw?msg=comp.lang.ad...](https://groups.google.com/forum/message/raw?msg=comp.lang.ada/E9bNCvDQ12k/1tezW24ZxdAJ)

"He went on to point out that they had calculated the amount of memory the
application would leak in the total possible flight time for the missile and
then doubled that number. [...] Since the missile will explode when it hits
it's target or at the end of it's flight, the ultimate in garbage collection
is performed without programmer intervention."

