
MIPS R3000 - tosh
https://en.wikipedia.org/wiki/R3000
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opencl
MIPS is a fun architecture (other than the delay slots that plagued early RISC
ISAs) and implementing a subset of it on an FPGA is still a pretty common
undergraduate university course project. I was kind of amazed just how simple
it is to get a basic CPU working, though even the 1988 version was quite a lot
more sophisticated than the class project version (multiple cache levels,
having an MMU, probably much better branch predictor, etc).

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AnaniasAnanas
Why does everyone seem to hate delay slots? I understand that it makes writing
assembly more annoying but most people use a compiler anyway.

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alain94040
It makes the hardware implementation more complicated. The delay slot was
perfect for the 5-pipeline original design. Once you try to push this to out
of order execution (executing more than one instruction per cycle), the delay
slot just doesn't make any sense.

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blu42
That's my understanding as well. Software-wise, I, for one, have not had
issues with reading or writing code with branch delay slots -- automatic nops,
at worst. I guess it all depends how early in one's development they were
introduce to the concept of delay slots.

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PopePompus
I'm honestly confused - why is a wikipedia page about an old computer
architecture on the front page of HN?

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news_to_me
Because it's interesting! I think it is, at least.

From the guidelines:

> What to Submit

> On-Topic: Anything that good hackers would find interesting. That includes
> more than hacking and startups. If you had to reduce it to a sentence, the
> answer might be: anything that gratifies one's intellectual curiosity.

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pinewurst
It's still my favorite RISC processor and the only one that I actually liked
coding in assembler (SPARC wasn't fun at all).

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mepian
How annoying were the branch delay slots?

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x0re4x
You could always put NOPs into delay slots by default and replace them later
with something more useful.

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jawnv6
no, you could not "always" find something useful to put there later. gross
exaggeration

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mrguyorama
You misunderstood parent. They meant you can always nop the branch delay, and
you might find something more useful for it later

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jawnv6
that may have been what they wanted to write. unfortunately they wrote
something wrong and misleading instead. i understood what they wrote perfectly
well and the implication therein isn't, somehow, my fault

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mrguyorama
The "always" qualifier does not apply to anything after the "and". Why do you
assume it does? You are being very combative and pedantic so I assume you have
a diehard rule for this that you can reference? Like some english grammar
handbook?

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segfaultbuserr
Alternative history time: what if MIPS R4000 hasn't been killed by Pentium?
Would we be running R10000-compatibles now?

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snvzz
Even more fun alternative history: What if Motorola didn't end 68000 with the
68060?

68060 released earlier than the pentium, and regardless it had about twice the
performance per clock. But then Motorola decided to abandon 68k to focus on
PowerPC.

Going further back: What if IBM picked 68000 over the 8086 for the PC?

I'm hoping RISC-V will put an end to x86. It's about time.

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tempguy9999
I thought motorola did their own RISC chips, the 88000.

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protomyth
They did two that I know of, the 88000 and M.Core. The 88000 had some issues
(I do believe floating point) and was really expensive.

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cwt137
I remember reading a computer architecture book that used a fictional MIPS
instruction set and used washing and drying clothes as an example of how to
pipeline / do parallel instructions. Does anyone remember the name of that
book?

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opencl
That description probably applies to several computer architecture books, but
the one I read was like that and called "Computer Organization and Design: The
Hardware/Software Interface".

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cwt137
This is the book. Thanks for your help

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segmondy
I loved this CPU, programming it using spim, then actually getting to write
some PSX code.

