
EUV Lithography Finally Ready for Chip Manufacturing - moreati
https://spectrum.ieee.org/semiconductors/nanotechnology/euv-lithography-finally-ready-for-chip-manufacturing
======
quincunx
Really curious, how can - from a signal processing perspective - 100
applications of a 193 nm wave, come to define 7 nm features? This can't be
additive, is there some form of modulation going on on the surface of the
silicon? Anyone know?

~~~
dogma1138
Nothing in 7nm is actually 7nm in size same goes for all other nodes.

That said patterning and interference is used to create subwavelengnt
features.

~~~
quincunx
Interference of a 193nm wave can only yield a 193nm wave, it being additive.
I'm curious what is done to get to 7nm.

~~~
anonytrary
Could a subtractive mechanism work? For example, if you want to create a 5nm
bump, but you only have a 20nm thick tool to draw bumps, you could draw
"everything except the 5nm bump".

In other words, draw a 20nm thick annulus around a 5nm center, thereby having
achieved the desired result: drawing a 5nm object with a 20nm tool.

That's a toy example, idk quite how that would translate to photolithography.

~~~
josaka
They do something like this with sidewall patterning:
[https://en.wikipedia.org/wiki/Spacer_patterning](https://en.wikipedia.org/wiki/Spacer_patterning)

------
Lind5
There are still some pieces that need to come together on this
[https://semiengineering.com/issues-and-tradeoffs-for-
euv/](https://semiengineering.com/issues-and-tradeoffs-for-euv/) and
[https://semiengineering.com/unsolved-litho-issues-
at-7nm/](https://semiengineering.com/unsolved-litho-issues-at-7nm/)

------
baybal2
>EUV Lithography Finally Ready for Chip Manufacturing

I have heard it every year, for the past 10 years

~~~
ISL
This is the first time I've heard of a 250W 19nm laser. That's a huge step
forward.

~~~
Already__Taken
The article mentions 13.5nm. Is 19nm the wavelength used to blast the tin that
re-emits as the the 13.5nm EUV source? Is that where the power is going to
result in a few watts at the printing surface?

~~~
no_flags
First question, no, they use CO2 lasers which emit in the um range, not nm.
Probably a typo.

Second question, the loss of power is due to two factors: 1) Conversion
efficiency of CO2 laser pulse to EUV light pulse. This is in the single digit
range as a percentage. 2) Transmission loss of EUV from light source to wafer.
EUV mirrors reflect in the ballpark of 50% of the light, and there are many of
them inside the scanner, so you have .5 * .5 * .5...

------
madengr
If TSMC is getting 21E9 transistors on a 12 nm process (i.e. Nvidia Volta),
then I assume a 1 nm process would be almost 3E12 transistors. That's insane!

Unless power dissipation drops 144x, I can't see that happening, unless it's
for memory applications. Crazy to think about though.

~~~
deepnotderp
Dennard scaling is what would allow that to happen. Unfortunately, the lesser
known cousin of Moore's Law is essentially dead.

