
Tin Plasma Extreme Ultraviolet Radiation Makes 5nm Integrated Circuits Possible - car
https://www.trumpf.com/en_US/applications/euv-lithography/
======
chc4
If you're interested in chip fabrication, I heartily recommend watching
[https://youtu.be/NGFhc8R_uO4](https://youtu.be/NGFhc8R_uO4) \- it goes over
the evolution of how they make transistors all the way up to 2009 state of the
art, with a follow up talk in 2013
([https://youtu.be/KL-I3-C-KBk](https://youtu.be/KL-I3-C-KBk)).

Both of them mention how Intel is sinking billions of dollars into ASML to try
and get this process working, and how impossible everyone thinks it is, so I'm
skeptical that they finally got everything squared away now :)

~~~
deepnotderp
TSMC and Samsung are also exploring EUV, so it's not just Intel. New
lithography is necessary to continue shrinking, otherwise mask costs will rise
exponentially (literally).

~~~
tlb
Can you explain the exponential rise in mask costs with shrinking? My naive
understanding is that you simply can't resolve features below some fraction of
the wavelength. How do more expensive masks get beyond that?

~~~
testvox
What you can do is basically use partially overlapping beams to energize an
area smaller than any of the individual beams (think venn diagram). Its a
similar technique (except in 2 dimensions) to radiation therapy where multiple
beams of radiation are passed through healthy tissue such that their
intersection point is on cancerous tissue. That way only the cancerous tissue
receives a highly damaging dose of radiation while the healthy tissue receives
significantly lesser dosages.

~~~
deepnotderp
That doesn't usually work because the the diffraction limit PSF is usually
Gaussian and therefore the overlapping region can have lower fluence than the
peak regions.

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RcouF1uZ4gsC
Reading this, I realized that I have no ability to differentiate actual in use
fab technology from science fiction. What the engineers and scientists do in
modern fabs is in my mind more impressive than the entire Apollo program.

~~~
kregasaurusrex
A lot of people talk about how wide-reaching the technologies spun out from
NASA in the Apollo Era were; whereas I see the research that goes into making
chips smaller has an equal if not greater reach. Considering how widespread
the modern IC is these incremental improvements need to become more and more
novel, to the point where entirely new approaches need to be designed to
combat the limits of physics itself.

~~~
joe_the_user
The weird thing, in a sense, is that tech that seems close to nanotechology
and nanomachines exists simultaneously with extremely mundane tech.

Trumpf is generating nanoscale EUV but I'm still hammer nails into the wall to
support my coat hanger rod. What's up? Where's my flying cars, etc.

~~~
choonway
You are willing a needlessly complex solution to a problem that can be solved
more efficiently using other methods.

You don't need a flying car - you need a hole which you can jump in and pop
out at your destination with the least hassle.

~~~
adrianN
Is that a pitch for the Boring Company?

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baybal2
A tidbit, a one of more lunatical proposal for the next gen fab design is to
build it around a multimegawatt cyclotron, and have the light source problem
"solved for good"

The genuine problem with tin plasma laser is its power efficiency. An early
adopter runs can bare with 0.02% energy efficiency, but imagine, say, a few 20
line fabs and their power consumption.

Another very important advantage of this design would be getting a more
stable, easily tunable, and more narrowband light source. Tin plasma has
around 1nm deviation in its spectrum, while a cyclotron can get to picometres
on an arbitrary wavelength.

And with all above, you get a supremely tempting option to try diffractive
optics, and do away with all geometry imposes nonsense of EUV reflective
optics...

~~~
guepe
I had a similar idea of using synchrotron to generate very low wavelength
light for lithography... I guess costs are an issue!

~~~
baybal2
The "lighbulb" in 3400 costs as much as a small research synchrotron already

~~~
epicureanideal
What's 3400?

~~~
baybal2
[https://www.asml.com/-/media/asml/files/products/twinscan-
nx...](https://www.asml.com/-/media/asml/files/products/twinscan-nxe3400b.pdf)

~~~
madengr
A 26x33 mm die would yield 86E9 transistor. Pretty impressive.

~~~
eigenloss
Not a useful comparison. A single neuron is far better networked to its
neighbors and far more complex/nonlinear than a transistor. There are already
chips out there with 1e11 transistors, but they don't run "ai" even a little
bit.

Assuming you need something like 1e5 transistors to approximate one neuron,
you'd need like 100m^2 of die area and interconnect to actually emulate a
brain.

~~~
anticensor
And you would still lag due to speed of light issues.

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pfdietz
One of the applications of shear-flow stabilized Z pinches is to generate
short wavelength light from xenon plasmas.

~~~
ttul
This is why I read HN.

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londons_explore
Why are people putting lots of effort into extreme UV generators when we could
just use x-rays? We know plenty of ways to generate and focus x-rays...

~~~
robbiep
Just a guess as I am not in the industry but I would imagine has to do with
the photoresists and masks - perhaps we don’t have ones that work with X-ray.
Not much good using a wavelength that passes through or is unabsorbed by the
resist material!

~~~
Itsdijital
IIRC we don't even have masks that can really take EUV, the mask is destroyed
after each exposure.

~~~
torpfactory
I think the masks can take it but their is a ton of difficulty in inspecting
the masks themselves for defects. IIRC the leading candidate at the time I was
in the industry was to actually expose wafers and then scan the wafers for
defects which originated on the mask, hoping to not confuse these with other
process defects. Not sure how they ended up solving that one.

~~~
jacquesm
Do multiple exposures and see which defects come up more than once?

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torpfactory
Yeah - typically print the entire wafer then compare dies within a field
(usually there are multiple dies exposed in a single exposure) to see which
defects are in the same place on each field. This won’t work if there is only
one die per field, as could be the case for an exceptionally large server
chip. In that case you probably need to predict what the image will look like
based on design files and then compare with the actual image and look for
differences. You could also e-beam scan the whole wafer but this can take a
while (like 30 days when I was around), night damage the wafer, and bumps up
against the reliability of E-beam components. It wasn’t being seriously
considered.

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bprater
For the curious: 100,000,000 transistors per square millimeter, from the site.

~~~
pflanze
I'll be making an attempt here to compare that number to the complexity of
programs in software. It's the first time I try to do this and I'm sure I
don't know enough to make a good comparison, anybody please correct me.

The binaries of Firefox on Debian Stretch (oldstable), when just counting the
main program binary and .so files, amount to about 100 MB of compiled code.
These are stripped hence will mainly consist of binary code and constants.

Making a flip flop in hardware requires 6 transistors IIRC. What if I compare
1 bit in software with 1 flip flop in hardware--OK, code is constant (could be
etched as a PROM, but that's a useless comparison), but represents some
complexity that probably needs more transistors to represent. E.g. an if
statement (after evaluating a value to be dispatched on) needs a conditional
jump assembly instruction (8 bytes?), and perhaps another jump instruction
when the success branch is finished (another 8 bytes). This comes down to 128
bits, 768 transistors with my stupid calculation; enough to route data etc.?

So, encoding a program of the complexity of Firefox (binary part) as hardware
would then need 100e6 _8_ 6 = 4.8e9 transistors. Given 100e6 transistors per
mm^2, this would need 48 mm^s chip area, a chip 7mm*7mm, not far from what
CPUs use?

Thus, today's web browsers and CPUs seem to be comparable in complexity? Or, a
web browser could be encoded entirely as hardware and about fit on a chip? I
find that unexpected and a bit surreal, loading a huge program like Firefox is
just bringing in the same amount of complexity into the running system as
there already is active in the CPU? Or, another line of expectation in my
thinking is, CPUs are very small compared to the large programs, programs are
being serially executed with a smallish set of instructions precisely because
complexity in Hardware needs to stay small. Actually maybe that's not really
true?

I'd welcome better insights.

~~~
eigenloss
You could probably do some estimate based on the relative entropy, which
should be vaguely comparable between hardware and software

~~~
pflanze
Are you talking about Kullback-Leibler divergence? Will have to read up on
that. Or can you clarify what you mean?

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techsin101
What if we utilized the 3rd dimension just a wild idea. Also designed chips as
long rectangular, more surface area.

~~~
gameswithgo
we have been in various ways for a long time. as you stack higher and higher
it gets harder to get the heat out, and its already really tough to get the
heat out.

Like intel's fastest gaming processor, the 9900k, the major difference is
better heat dissipation material between the die and heat spreader.

laptops and phones are mostly all thermally limited

die shrinks help with this, but only if you don't increase performance as you
do it.

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lstodd
Let's do hard gamma lithography already.

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j_coder
I can imagine on a few decades company's data center on a single square meter
chip :)

~~~
olliej
That would be colossally inefficient - essentially the size of the chip means
that electrons would be taking multiple cycles to get from one side to the
other. The solution would be localizing processing into distinct processing
units on the one die. At the point you’ve reinvented multiple cores and it
starts becoming cost effective to split them into separate chips to improve
yields :)

~~~
pixl97
That is only on a clock locked chip. There are chips with designs where
different parts of a chip where clocks run at different cycles.

~~~
olliej
Most modern chips already use numerous clocks (aside from anything else
propagation delays for the clock signal is already a problem).

The problem is not simply "because clock cycle" it is "if electron takes Xns
to get from one execution unit to the next, then that's Xns of functionally
idle time". That at best means additional latency. The more latency involved
in computing a result the more predictive logic you need - for dependent
operations the latency matters.

An asynchronous chip does not avoid that same problems encountered by a
multistage pipelined processor, it's purely a different way to manage varying
instruction execution times.

But this doesn't answer the killer problem of yield. The larger a single chip
is the more likely any given chip is to have errors, and therefore the fewer
chips you get out of a given wafer after the multiple weeks/months that wafer
has been trundling through a fab. Modern chips put a lot of redundancy in to
maximize the chance that sufficient parts of a given core survive manufacture
to allow a complete chip to function, eg. more fabricated cache and execution
units than necessary, at the end of manufacture any components that have
errors are in effect lasered out. If at that point any chip doesn't have
enough remaining cache/execution units, or an error occurs where it can't be
redundant, the entire chip is dead.

The larger a given die is the greater the chance that the entire die will be
written off.

That massive ML chip a few days ago worked by massively over prescribing
execution units. I suspect that they end up with much greater lost area of a
given wafer than many small chips, which directly contributes to actual cost.

