
The Foundry at the Heart of DARPA’s Plan to Let Old Fabs Beat New Ones - rbanffy
https://spectrum.ieee.org/nanoclast/semiconductors/processors/the-foundry-at-the-heart-of-darpas-plan-to-let-old-fabs-beat-new-ones
======
walrus01
There is a special IBM chip Fab in upstate New York that makes things for the
NSA and DoD. They don't care if things are on a slightly older process.

See also, the DoD trusted foundry program

[https://www.google.com/search?q=dod+trusted+foundry+program&...](https://www.google.com/search?q=dod+trusted+foundry+program&oq=dos+trusted+foundry+pro&aqs=chrome.1.69i57j0.6638j0j4&sourceid=chrome-
mobile&ie=UTF-8)

------
WiseWeasel
This piece has more technical details on their architecture and expected
performance:

[https://www.top500.org/news/darpa-picks-research-teams-
for-p...](https://www.top500.org/news/darpa-picks-research-teams-for-post-
moores-law-work/)

------
mechagodzilla
As a computer architect, I’m really curious what their practical capabilities
will be for this process. There’s definitely a market for low volume / high
performance chips if they can develop something interesting (ie mask costs
similar to 90nm but performance closer to 7nm).

~~~
dev_dull
There’s security benefits (probably why it’s funded by darpa). It makes
producing a lot of high performance chips economical outside of SE Asia.

------
Invictus0
What exactly is the monolithic 3D integration process? In what way is this
technology superior to the current state of the art?

~~~
deepnotderp
Monolithic 3D is also sometimes called "sequential 3D". In essence, instead of
current 3D integration which fabricates several 2D chips, then thins them,
adds TSVs, aligns and then finally bonds them, Monolithic 3D makes 3D chips
layer by layer.

The advantages are that it can have extremely dense chip to chip connections,
as much as ~10,000X as dense as TSVs (literally) and no ESD diode capacitance
(can be as much as ~50fF!!).

The disadvantages are that copper interconnects melt above ~400 degrees
celsius, and we are around ~1200 degrees celsius to make transistors. There
are a few ways around this but they usually result in crummier transistors.

~~~
nhaehnle
From what I understand, another disadvantage of monolithic 3D are the yield
implications.

When you fabricate several 2D chips and then integrate them, it allows you to
test those 2D chips for errors separately before the integration, which should
give you better yields overall.

~~~
deepnotderp
Yes, that's a major problem as well since it's an exponential issue.

------
hinkley
What stops us from wrapping the circuits around the sides of the chip? Holding
onto them? Or the fact that stacking gets you more layers than 2 1/2?

~~~
kragormonkey
Wrapping around sides isn't easy because chips are cut from a single large
wafer pretty late in manufacturing. The sides aren't exposed until the end.

Besides, it won't help much. Usually when people want to shrink chips, it's
often because shorter links. This means lower latency (ie faster) and lower
heat loss. Wrapping or stacking doesn't help those.

------
forkandwait
Can someone recommend a book on chip fabrication?

~~~
novaRom
Keywords: VLSI, CMOS, MOSFET

You can find many good books, especially from 80th-90th

