
Intel Buys Altera for $16.7B - rbanffy
http://www.bloomberg.com/news/articles/2015-06-01/intel-buys-altera-for-16-7-billion-as-chip-deals-accelerate
======
ChuckMcM
I find this an interesting move. Not many remember that Lattice Semiconductor
was nominally[1] spun out of Intel in '83\. Back in the early 80's the
"computer" companys like AMD, Intel, and National were also making chips to
help connect them to the chips around them. And people had started building
something called Programmable Array Logic (PALs) which was trademarked by AMD
so folks also called them Gate Array Logic or GALs. The idea was that you had
this microprocessor that had one interface or needed a simple peripheral, and
this programmble chip could provide it.

I arrived at Intel just after the folks who started Lattice had left and the
position of Intel was that programmable logic was a neutral idea at best, and
generally bad or unsuitable for any sort of volume idea which is where Intel
wanted to play.

But the interesting thing about the 22nm node is that you can put a whole lot
of programmability into a pretty cost effective FPGA, and so now the pendulum
hit ASICs and now is starting to find FPGAs in "general purpose" production
products. And here we are with Intel buying an FPGA company.

[1] My memory is fuzzy on the exact details, whether it was just a bunch of
engineers who decided to quit and moved over to Lattice when it was founded or
if Intel helped with the founding by trading some fab capacity and engineers
in exchange for some equity in the new company.

~~~
neutronicus
I don't know much 'bout the wider world, but FPGAs are hot right now in atomic
physics and quantum computing, e.g.

[http://journals.aps.org/prl/abstract/10.1103/PhysRevLett.109...](http://journals.aps.org/prl/abstract/10.1103/PhysRevLett.109.080502)

[http://journals.aps.org/prl/abstract/10.1103/PhysRevLett.109...](http://journals.aps.org/prl/abstract/10.1103/PhysRevLett.109.080501)

results which were only really possible when those labs started switching to
FPGAs from the DACs they'd been using previously.

~~~
matthiasl
Is "DACs" a typo for "DSPs"? If you really do mean DACs, can you elaborate on
what those DACs were doing and how that was replaced by FPGAs?

~~~
neutronicus
The experiments use independent time-varying voltages on a set of electrodes
to move a trapping potential well (and the ion in contains) along a path.

They need high-quality voltage waveforms on those electrodes to make sure they
don't lose the ion or disturb its quantum state, and the DACs they had in '10
didn't have the update rates of the FPGA apparatus they built in '12 and they
improved transport times by something like a factor of 100 by making the
switch.

~~~
mng2
I looked at Bowler's thesis. The DAC chips set the performance, the FPGA is
just a natural way of interfacing to them.

[http://www.nist.gov/pml/div688/grp10/upload/Bowler15_thesis-...](http://www.nist.gov/pml/div688/grp10/upload/Bowler15_thesis-2.pdf)

------
m_mueller
I hope Intel puts their weight into FPGA now instead of just seeing this as
taking out a potential (future) competitor. IMO the technology has a lot of
premise, especially in HPC where hardware often gets very specific tasks, so
general purpose chips are a waste.

Edit: It looks like they've already been pursuing this, I wasn't aware of
Xeon+FPGA pairings yet: [http://www.extremetech.com/extreme/184828-intel-
unveils-new-...](http://www.extremetech.com/extreme/184828-intel-unveils-new-
xeon-chip-with-integrated-fpga-touts-20x-performance-boost)

~~~
amelius
Any good examples where FPGAs outperform standard CPUs?

~~~
pdkl95
In addition to the benefits that others have already mentioned, when you use
an FPGA, you can customize your hardware to provide task-specific features. An
interesting example would be this demoscene project by LFT (Linus Åkesson):

[http://www.linusakesson.net/scene/parallelogram/](http://www.linusakesson.net/scene/parallelogram/)

"For this demo, I made my own CPU, ... cache, ... blitter with pixel shader
support, a VGA generator, and an FM synthesizer."

In his explanation for why he wrote his own CPU in the FPGA, Linus explained
"...I was able to take advantage of the added flexibility. For instance, at
one point the demo was slightly larger than 16 KB, but I could fix this by
adding some new instructions and a new addressing mode in order to make the
code compress better."

~~~
listic
I knew something like this _had_ to exist. Shouldn't this approach extend to
modern hardware? E.g. surely there must be cases where it is effective to use
custom FPGA-based hardware fit for the job, rather than (or in addition to)
CPU and GPGPU?

I heard counter-arguments to the tune of 'hardly anyone wants to program their
FPGA' which sounf strange to me: after all, hardly anyone wants to program
their pixel shaders, either.

~~~
kevinnk
The real problem with FPGAs is that for 99% of use cases, CPU/GPGPU is good
enough. And in the cases you really do need the extra speed, its rare you also
need the flexibility, in which case you'd make an ASIC. There is a niche for
FPGAs (especially in prototyping), but it's not as big of a market as you
would imagine.

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beambot
The next (obvious) question: What's gonna happen w/ Xilinx.

For the longest time, the FPGA market has been dominated by Xilinx and Altera.
With one joining Intel, it seems logical to expect a response?

~~~
aswanson
I hope the develop open and cheap compilation tools to force xilinx to do the
same.

~~~
bjackman
I believe the Xilinx tools are actually free of cost. Still, though, open
source FPGA tools are desperately needed.

edit: even if they just opened up the bitfile format. I believe it's a similar
situation as GPU instructions sets though: managers saying "no because
patents".

~~~
cottonseed
I recently wrote a place and route tool for Lattice iCE40 FPGAs [0]. The
bitstream was reverse engineered by Clifford Wolf and others as part of the
IceStorm project [1]. We're using Yosys [2] for Verilog synthesis, also
written by Clifford.

[0] [https://github.com/cseed/arachne-pnr](https://github.com/cseed/arachne-
pnr)

[1] [http://www.clifford.at/icestorm/](http://www.clifford.at/icestorm/)

[2] [http://www.clifford.at/yosys/](http://www.clifford.at/yosys/)

~~~
FullyFunctional
Wow, that is pretty awesome. I didn't expect this to have arrived that
quickly.

Does it support user constraints on relative placement (and routing)? Self-
timed logic, such as NULL Convention Logic [1], doesn't fit well with the
synchronous FPGA paradigm, but can be implement on those if the feedback loops
are tightly controlled [2]. I'd like to play with that :)

[1]
[http://en.wikipedia.org/wiki/Asynchronous_circuit](http://en.wikipedia.org/wiki/Asynchronous_circuit)

    
    
        http://www.amazon.com/Designing-Asynchronous-Circuits-Convention-Synthesis/dp/1598299816
    

[2]
[http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=543867...](http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=5438673&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D5438673)

~~~
cottonseed
Whoa, I had no idea you could do async circuits on an FPGA (although I can't
get to [2] right now, the site is under maintenance). Right now, I only
support IO constraints. The IceStorm project hasn't documented the timing
model yet but it is in pipeline. Is it possible to do what you want with
vendor tools? Anyways, email me and we can chat about what you'd need.

------
akuma73
I don't really understand this deal.

Altera and Intel already have a fab agreement and Intel is desperate to get
customers into their mothballed fabs.

All this talk of technology collaboration could be accomplished with strategic
partnerships/licensing that would certainly be less than $16.7B.

This looks like a case of a foundry player buying their customer to prevent it
from defecting to TSMC in the future. To me this is a sign of weakness.

~~~
silverpikezero
Rumor has it that Altera was unhappy with Intel's process and was going to
bail. Intel was so dependent on their cooperation that acquisition started to
look good.

~~~
anontera
There is a lot of truth to this - Intel's process (and their tools!) is a
FUCKING NIGHTMARE

------
BenoitP
With Java being a sort of common API for lots of programmers to reach the
hardware, I have always wondered if we would ever saw hardware that would
directly implement the JVM bytecode, or even JavaSE.

Apparently Altera has something called JVXtreme[1], which claim x55 peak and
x15 sustained performance increase.

From the pdf: "JVXtreme accelerates the actual execution of Java by executing
87 of the most commonly used Java byte codes in hardware."

[1]
[https://www.altera.com/en_US/pdfs/products/ip/ampp/documents...](https://www.altera.com/en_US/pdfs/products/ip/ampp/documents/jvxtreme-
java_acc.pdf)

~~~
tjdetwiler
ARM has something similar:
[http://www.arm.com/products/processors/technologies/jazelle....](http://www.arm.com/products/processors/technologies/jazelle.php)

~~~
makomk
Had. I believe all modern ARM cores have totally dropped support for executing
Java bytecode natively in favour of traditional JIT compilers.

------
Sophistifunk
This is pretty damned exciting IMO. Intel has a long history of thorough
documentation and high-quality tools, available to anybody for a reasonable
price if not free. Basically the polar opposite of every single player in the
FPGA space. Their tools are _garbage_ , cost a mint, and documentation is lax.

------
whoisthemachine
I had no idea Altera was worth that much... they always seemed like such a
small-time company when we used their products in class.

~~~
PaulHoule
Certainly FPGA users see them as a distant second to Xilinx, but that may be
why they need to be bought. Also, Altera is making 14mm parts at Intel's
foundry which suggests they could integrate pretty easily with Intel's CPU
products.

~~~
typon
I don't know which FPGA users you're talking about. Huawei, one of the largest
FPGA users in the world, has been buying from Altera for a long time now.

Altera's software is miles ahead of Xilinx's. And their hardware is pretty
close, with Xilinx getting the edge.

~~~
minthd
>> Altera's software is miles ahead of Xilinx's.

Can you please expand on that ?

Also what about partial reconfiguration , isn't xilinx the leader ? isn't that
important for general compute ?

~~~
typon
By software I mean their place/route and synthesis tool, Quartus. The
algorithms used in Quartus, based off of VPR (Versatile Place/Route) is the
reason Altera is in the position they are now, relative to a decade ago when
they were struggling quite a lot.

Place and route in digital circuits is an NP-hard problem. Xilinx solves this
problem using analytical place and route (solving a giant system of
equations), explained here a bit more: [http://www.xilinx.com/products/design-
tools/vivado/implement...](http://www.xilinx.com/products/design-
tools/vivado/implementation.html)

Altera's tool uses Simulated Annealing. Historically, Altera's tool has been
faster and easier to use, allowing user's to implement larger designs and
synthesize them quicker. However, I don't know the state of things RIGHT NOW,
but I'm pretty sure this was the case 2 years ago.

Altera's chip design/layout is lacklustre compared to Xilinx's though.

Also, partial reconfig is a very important feature, but it's not used by all
customers. Most people just want large FPGAs so they can fit large designs on
them, have really fast I/O (Transceivers) and meet timing on their circuits.

~~~
minthd
I know xilinx created a whole new tools(which they releases a couple years
ago), and [1] says they moved from simulated annealing. So at least according
to the article, they aren't behind altera.

[1][http://www.eejournal.com/archives/articles/20120501-bigdeal](http://www.eejournal.com/archives/articles/20120501-bigdeal)

------
sudioStudio64
Xeons with FPGA's are something that there high end customers would consume in
major volumes. Some of the investment banks have been doing FPGA acceleration
for algo trading for several years.

I wonder what broadly available FPGA's would mean for systems development,
though...could be pretty interesting.

------
rbanffy
I was reading about the differences between CLDCs and FPGAs and got curious:
why are CLDC offers so much simpler than FPGAs? Considering the same
technology and feature sizes, I'd expect CLDCs, since they lack the
reconfigurability of FPGAs, to be able to hold more complex designs.

~~~
ZenoArrow
What's a CLDC? I've never heard of them before. Do you mean CPLD?

[http://en.wikipedia.org/wiki/Complex_programmable_logic_devi...](http://en.wikipedia.org/wiki/Complex_programmable_logic_device)

~~~
rbanffy
Of course, yes. CLDC is something that collided with CPLD in my brain,
probably due to a Java-induced trauma many years ago. CLDC is a Java ME
profile (a very simple smartphone from another age).

------
zokier
I wonder if in addition to the obvious high-end Xeon+FPGA combo we are going
to see smaller Quark+FPGA devices too for the embedded marker. It would make
lot of sense, but Intel on the other hand never much cared for embedded.

------
programmernews3
I hear they are doing this to get ARM out of the FPGA+SoC space.

~~~
rjsw
But ARM+FPGA hybrids are available from Xilinx as well.

~~~
danellis
Not so much get them out of the market, but to be a viable competitor in that
market. Perhaps in much the same way as they're trying to do with Quark
against regular ARM SoCs.

------
listic
So, it's not like Intel is struggling really? I heard news of them laying off
a large part of their workforce, while relocating to Hillsboro.

------
ksec
Intel should have bought BroadCom as well

------
jreimers
"Altera’s devices can have their function updated, even after they’ve been
installed in end-devices. While they’re sold in relatively small volumes,
programmable logic usually requires the latest in production technology
because it’s some of the largest chips in the industry."

Somebody at Bloomberg is obviously a little confused about FPGAs.

------
shmerl
Are dedicated video encoding / decoding chips some of those made by Altera?

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chrisseldo
I thought this said, "Intel Buys Africa for $16.7B"

