

Lola-2: A Logic Description Language - dchest
http://www.inf.ethz.ch/personal/wirth/Lola/index.html

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dchest
For the 2013 edition of "Project Oberon" book, Niklaus Wirth rewrote the
Oberon system for the custom RISC CPU, which he designed in Verilog language.
It seems like he wasn't a fan of it, so he created Lola-2 in 2014 and wrote a
transpiler to Verilog:

"Now textual descriptions of hardware are common place, the preferred
languages being Verilog and VHDL. With the view of a teacher, I have the same
grave objections against them as for the wide-spread programming languages:
they are by far too complex. Thereby they make it difficult and pitfall-prone
for beginners, apart from causing headaches for teachers. I felt that Lola
could play the same role for HDLs as Oberon for PLs, easing learning for
beginners and relieving teachers from headaches."

~~~
zeckalpha
Neat!

Sounds similar to what happened with Bluespec, though not Niklaus Wirth of
course: [http://csg.csail.mit.edu/IAPBlue/workshop/Augustsson-
designe...](http://csg.csail.mit.edu/IAPBlue/workshop/Augustsson-designer.pdf)

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userbinator
From the "Translating from Lola to Verilog" document:

 _Also omitted is a facility of open-collector signals. This is no severe
restriction, as this technology can be considered as outdated._

What? I2C and 1-wire are "outdated"?

~~~
weinzierl
I think "facility of open-collector signals" means utilizing the open-
collector to realize a logical AND without a real gate. I don't know enough
Lola, VHDL or Verilog to say why they have to treat this kind of AND
specially.

For the I2C it's enough that the driver has an open collector transistor and I
think you wouldn't model that in the HDL anyway.

