
Lmarv-1: A RISC-V processor you can see. Part 1: 32-bit registers - peter_d_sherman
https://www.youtube.com/watch?v=yLs_NRwu1Y4
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peter_d_sherman
Also:

LMARV-1 (Tangible RISC-V) Part 2: Redesigning and testing the register file
[https://www.youtube.com/watch?v=W-B32C_jKbA](https://www.youtube.com/watch?v=W-B32C_jKbA)

LMARV-1 (Tangible RISC-V) Part 3: Designing the ALU
[https://www.youtube.com/watch?v=KGBUtKRBKZs](https://www.youtube.com/watch?v=KGBUtKRBKZs)

LMARV-1 (Tangible RISC-V) Part 4.1: Designing the shifter
[https://www.youtube.com/watch?v=SuUChAF3gaw](https://www.youtube.com/watch?v=SuUChAF3gaw)

LMARV-1 (Tangible RISC-V) Part 5: A horrible mistake, and memory
[https://www.youtube.com/watch?v=uerjjKOmO94](https://www.youtube.com/watch?v=uerjjKOmO94)

LMARV-1 (Tangible RISC-V) Part 6: ALU, testing, instruction controller
[https://www.youtube.com/watch?v=_Uzxi_MFtP0](https://www.youtube.com/watch?v=_Uzxi_MFtP0)

LMARV-1 (Tangible RISC-V) Part 7: Testing the tester boards
[https://www.youtube.com/watch?v=HbKT-
WX8Pmc](https://www.youtube.com/watch?v=HbKT-WX8Pmc)

LMARV-1 (Tangible RISC-V) Part 8: Testing the revision D ALU
[https://www.youtube.com/watch?v=zeYNixZqgko](https://www.youtube.com/watch?v=zeYNixZqgko)

