
Designing a CPU in VHDL, Part 1: Rationale, Tools, Method - luu
http://labs.domipheus.com/blog/designing-a-cpu-in-vhdl-part-1-rationale-tools-method/
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cottonseed
I'm also an (ex?) compiler engineer and I've played a little with FPGAs and
computer architecture. In addition to the obligatory processor design, I
recently created a open-source place and route tool for iCE40 FPGAs:

[https://github.com/cseed/arachne-pnr](https://github.com/cseed/arachne-pnr)

Together with Yosys (a Verilog synthesis tool):

[http://www.clifford.at/yosys/](http://www.clifford.at/yosys/)

and the IceStorm bitstream creation tools:

[http://www.clifford.at/icestorm/](http://www.clifford.at/icestorm/)

it provides a full Verilog-to-bitstream open source toolchain for the iCE40
FPGAs. There is also a low-cost (~$21) USB development board:

[http://www.latticesemi.com/icestick](http://www.latticesemi.com/icestick)

Unfortunately, this toolchain doesn't support VHDL, so I can't try out the
OP's TPU.

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Zardoz84
If someone like to try VHDL or Verilog and not have FPGA board, could try EDA
Playground :
[http://www.edaplayground.com/x/Cs2](http://www.edaplayground.com/x/Cs2) (An
32 bit ALU)

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gshrikant
This is amazing! I've been looking for an online HDL for learning and trying
out ideas on the fly and with no IDE at hand. Thanks for the link!

~~~
Zardoz84
^_^

I have plans for eventually build a VHDL implementation of TR3200 CPU with it.

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bisrig
My best advice: synthesize early and often, and spend the time to poke around
in the synthesis schematic viewer - Webpack still includes this I believe.
It's a great way to compare what you wrote in code to the logic you intended
to implement in your mind's eye (or better yet, your notebook).

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JoachimS
And read the design guidelines from the FPGA vendor of the device you are
targeting. Xilinx, Altera (Intel), Microsemi and Cypress all have different
rules for mapping things like memories, write enables etc.

Xilinx is happy to not reset registers, Altera will generate a bigger design
if reset is not stated in the code.

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andmarios
We did similar projects as part of our ECE degree. In general we would start
with boolean algebra and logic design, then proceed to computer organization
and last to computer architecture (one semester each).

Your project would be at the computer organization level. IIRC adding a
pipeline would move it to computer architecture level.

I understand that reading outside a class may be a bit boring, but these
courses gave us a much better understanding of key concepts and issues; from
basic boolean operations (i.e how to do them right, how to optimize them), to
basic concepts (e.g. 2's complement, base-2 arithmetic, FSMs, flip-flops), to
more advanced concepts (e.g complex logical components, datapath, control), to
various issues (e.g hazards, async / sync design), etc (i.e all these you
probably won't implement as cache, OoO execution, virtual memory).

Knowing —to a certain degree— all these made the project easier and much more
fun since we could actually have crazy ideas and try to implement them.

I don't know the current state of literature, but when I took the courses (12
years ago) the Patterson and Hennessy books (Computer Organization and Design,
Computer Architecture) were terrific.

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lfowles
As of 2007-2011, Patterson and Hennessy books were in use in courses I took as
well. Great stuff, but the treatment on GPUs was a little out of date even a
year or two after being published (GPGPU was just getting started and evolving
rapidly).

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rdc12
Their Computer Organization and Design, had a new edition in 2013, that may
cover GPU stuff better, havn't read it myself thou.

Still havn't seen a book that covers SIMD very well?

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lfowles
* Features the Intel Core i7, ARM Cortex-A8 and NVIDIA Fermi GPU as real-world examples throughout the book

Sounds promising. The 4th edition just had the GPU content stuffed into an
appendix.

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Svenstaro
For those who really want to get into HDL stuff but are put off by the weird
syntax, I highly suggesting taking a look at MyHDL[0]. It's a very nice Python
lib with good docs and active development. I actually implemented a CPU in it.
It can output to VHDL and Verilog and can even generate simple structures for
you.

[0] [http://www.myhdl.org/](http://www.myhdl.org/)

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alain94040
Please do yourself a favor and use Verilog instead. I understand that VHDL
forces you to write cleaner code, but it's also frustrating for no good
reason.

Also, start looking into pipelining ASAP. Implement one micro-arch, benchmark
it, then try to do better. It's a great way to learn.

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p1esk
+1 for Verilog. SystemVerilog is the way to go.

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krapht
I like VHDL. Verilog and non-blocking vs blocking assignments can trip you up
so easily. As for verbose code, you spend way more time debugging and thinking
about how to structure a program than you do writing text on the screen.

~~~
blackguardx
I prefer Verilog but what you say is true or at least should be true if you
want to end up with a good, easily debuggable result.

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jamieiles
I've been working on a similar project for a couple of years now
([http://jamieiles.github.io/oldland-cpu/](http://jamieiles.github.io/oldland-
cpu/)) and these are very rewarding projects - there's a great mix of hardware
and software so there's always something interesting to work on.

One of the most valuable lessons that I've learnt from this is to treat the
FPGA as a validation target, and the FPGA tools purely as a way to produce
that image - they're entirely unfriendly to develop in. If you use verilog
then verilator gives lightening fast simulations and you can use it to verify
the hardware against.

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bobp127001
>bonus points goes to the people who realise there is an odd thing about the
form of the baz (branch if Ra is zero) instruction.

Is this because the second argument is another register (presumably containing
an address to branch to) instead of a label?

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rdc12
Just before the loop there is this instruction, "load.l r7, $mul16_fin".

Prehaps this is so the assembler/linker/loader doesn't need to resolve what
address the label ends up having

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foobarge
Also note, an other cool project:
[http://moxielogic.org/blog/](http://moxielogic.org/blog/) (a ex co-worker.)

"Moxie is a general purpose bi-endian load-store processor, with sixteen
32-bit general purpose registers and a comprehensive ISA consisting of two-
operand variable width instructions. There are moxie implementations that run
on both Altera and Xilinx FPGA architectures, a number of simulator ports
(including QEMU), and a complete GNU toolchain for C/C++ development."

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p1esk
Here's a good book guiding through an implementation of a simple 8 bit
processor (based on 8080 architecture) with VHDL:
[http://www.amazon.com/Design-Computers-Complex-Digital-
Devic...](http://www.amazon.com/Design-Computers-Complex-Digital-
Devices/dp/0130402672) The same author also wrote another book later where he
shows a design of ARM like 16 bit CPU with pipelining.

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sklogic
And this is what you can use if you want to implement an instruction or two in
Verilog without having to implement the rest of the CPU. Plus a flexible
compiler toolchain:
[https://github.com/combinatorylogic/soc](https://github.com/combinatorylogic/soc)

(never mind it being multicycle, it was done this way for a reason, and
dropping in a RISC design should be fairly trivial.)

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hharnisch
> Verilog is the C99 of the HDL world, and you can get in quite a mess as a
> beginner if you don’t understand it well enough.

I found both to have their little quirks, but personally liked Verilog syntax
a little better - modules concept made a lot more sense coming from a software
background. Do you have an existing instruction set you're planning on
supporting?

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gjkood
For those interested in other FPGA boards, Digilent makes a whole series of
affordable ones.

[https://www.digilentinc.com/Products/Catalog.cfm?NavPath=2,4...](https://www.digilentinc.com/Products/Catalog.cfm?NavPath=2,400&Cat=10&FPGA)

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JoachimS
I can recommend the boards from TerAsic. Solid design and Readable
documentation. Altera ships boards from TerAsic for their courses. Good value
for money.

[http://www.terasic.com.tw/en/](http://www.terasic.com.tw/en/)

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eggie5
I't s a viable concept. In school we built a functional pipelined-MIPS
processor in verilog: [https://github.com/eggie5/SDSU-
COMPE475-SPRING13](https://github.com/eggie5/SDSU-COMPE475-SPRING13)

