
Altera Discloses Heterogeneous SiP Devices That Integrate HBM2 DRAM with FPGAs - luu
http://newsroom.altera.com/press-releases/nr-dram-sip.htm
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jhallenworld
I'm curious what the latency of this memory is.

You can do this without the SIP using something called Hybrid Memory Cube:
[https://en.wikipedia.org/wiki/Hybrid_Memory_Cube](https://en.wikipedia.org/wiki/Hybrid_Memory_Cube)
The bandwidth is huge and uses a serdes interface. Even so, it would be nice
if there were advancements in low latency high capacity memory (without low
latency, you need parallel work to make use of all the bandwidth).

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zombees
Sounds like Intel's acquisition is working out nicely. Perhaps part of the
plan?

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caminante
I'm skeptical of this post's appropriateness for HN. It's a canned press
release, has 17 points and only 1 comment.

Can someone explain the significance (if any)?

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tinco
It doesn't matter if it's a canned press release or not. What matters if
there's something new on the market that's relevant to startups. I'm not an EE
so I don't follow it completely, I think their introducing a new line of FPGAs
that have on board DRAM. That could be very good news if they're priced right,
though I don't see in the article how much ram exactly..

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caminante
You're asking the same questions I did, ;-).

The reason you're asking the same questions has less to do with lack of domain
expertise and more to do with the (lack of) quality info in the press release.

