

Intel Demos 48-Core Prototype Chip - adeelarshad82
http://www.pcmag.com/article2/0,2817,2356557,00.asp

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anigbrowl
Intel research page here: <http://techresearch.intel.com/articles/Tera-
Scale/1826.htm>

Interestingly, it's x86 compatible, although the individual cores are only
around atom-powered. It's built out of 24 'tiles' of 2 cores each with a
25gB/s internal bus, and: _Each tile (2 cores) can have its own frequency, and
groupings of four tiles (8 cores) can each run at their own voltage._

Very much a lab project right now, but impressive nonetheless.

~~~
seiji
Interesting: "Each core can run a separate OS and software stack and act like
an individual compute node that communicates with other compute nodes over a
packet-based network."

I'm going to ding them a few points for trying to birth a new acronym though.

~~~
jcapote
This hardware just screams: "run erlang on me plz"

~~~
sketerpot
The lack of memory sharing, plus the scalable low-latency network on chip,
would be the Platonic ideal for Erlang.

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wmf
This looks like nothing more than a rehash of the MIT RAW project from 10
years ago. (but this time with x86!) Tilera's shipping products look more
interesting than this Intel research project. The power management might be
interesting but I can't find many details about it.

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modeless
Interesting that this is separate from Intel's Larrabee project
<http://wikipedia.org/wiki/Larrabee_(GPU)>. Larrabee also has the potential to
put 48 x86 cores on one chip but provides a fully coherent cache and a ring
bus instead of a mesh network with message passing.

The other major difference is that Larrabee includes a wide vector processor
in each core to run OpenGL/DirectX shaders or OpenCL kernels.

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sketerpot
No cache coherence? There's an interesting choice. I suppose it could be handy
for companies running "cloud data centers" who just want a bunch of cores with
a high-bandwidth low-latency packet-switched network going between them.

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RiderOfGiraffes
Other similar (in some sense) systems include the Inmos transputer based
machines such as the ParSys SuperNode and and Meiko CS-1 (and others), and
Danny Hillis's Connection machines CM1 and CM2.

These ideas have been around for a long time and are constantly being refined.
Not to say this isn't an advance, but I've worked on commercial machines of
this ilk.

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bitwize
Didn't Chuck Moore do this? And wasn't his version like a million times more
awesome?

~~~
sketerpot
He took a bunch of really minimal stack-based processors, added local
interconnect, and called it good. Intel is making something quite a bit more
complex, with cores that can run a typical operating system (Linux, right now)
and a full-fledged network for communications, complete with tiny routers.

~~~
bitwize
In other words, typically Intel-style MASSIVE OVERKILL. Splendid.

~~~
sketerpot
No, it's not overkill; it's a surprisingly clever and practical design for
data centers and (with a more FP-centric core) computing clusters. The cores
are relatively simple and get high performance/Watt for x86, and by fitting a
lot of them onto a die with shared motherboard/cooling/etc. and some amount of
DRAM sharing, they can lower the costs of machines that would ordinarily be
running a bunch of virtual servers on Xen.

As for the packet-switched network on chip, that's the way of the future: even
with simple routers, it scales way better than bus-based communication
methods, and is vastly easier to program than the nearest-neighbor
interconnect that Chuck Moore used.

I'm not trying to chew you out or anything; I just want to impress on you that
this is fascinating stuff, and not something to be simply pidgeonholed as
"massive overkill".

