
Icarus Verilog Simulator - luu
https://github.com/steveicarus/iverilog
======
kev009
Throwback and maybe not so useful anecdote.. the first startup I worked at
created an analog/mixed signal circuit design suite that seemed fairly
innovative. I am not a EE, so I really don't know how much of that was the
founder's kool aid, but the space did seem very under-served.. think
mainstream analog/mixed chip layout tools as everyone writing technical
documentation in MS Word and there being an opening for something like
FrameMaker.

Analog placement and routing is a lot harder than digital, and key to a lot of
this was simulation of many permutations. We found Gnucap and iverilog to be
capable tools versus the commercial simulators that cost six figures.

Chip design tools are an interesting space for sure, but I'm glad to be out of
it due to the slow pace of change by both tools vendors and design houses. The
startup has also never sold any software due to the quirkiness of the founder,
and the end of the experience cooled my desire to work in startup space
because so much is outside of your control even when you're in control if that
makes any sense.

~~~
blackguardx
Most chip design tool startups are designed to be bought by a big player. The
big guys (cadence, mentor graphics) don't really do much feature development.
They just buy startups that innovate around one feature. In many cases, these
startups make a plugin for one of the major tools. The plugins are able to
integrate pretty well because the founders of these startups are often former
employees of the big guys. Revolving door...

Your company might have had trouble brcause it is hard to convince engineers
to risk a million dollar tapeout on untested tools.

~~~
buserror
Funny bit is that they'll know buy pretty much any crap. I've worked lately
with a NAND controller IP that ticks /every single box/, has every single
feature and absolutely all the acronyms you can think of, and is the most
useless piece of cr _p_ ever* to use. It's so bad that I wish there was a
'passthru' mode so let me talk to the NAND flash on GPIOs, because it's likely
I'd have better performance anyway.

But, that's a brand new IP bought by cadence to add to their list, and
therefore it was also sub-licenced by some hardware designer somewhere (who
has no idea what 'software' is) from the feature sheet alone. Then it lands on
the poor unsuspecting person who needs to write the driver (me).

So yes, that startup/feature/IP cycle is a very weird economy indeed.

------
eggie5
I used Icarus for my undergrad verilog courses. We had to design a pipelined
MIPS processor. The way they taught the course was using Xilinx ISE on
windows. I didn't want to have to change my entire workflow and get a windows
computer just to use ISE. I even tried their linux build of ISE but it was
super buggy. Using Icarus on my MAC made my life much better and let me finish
my compe w/o using windows at all.

Check out the processor build all using the Icarus toolchain:

[https://github.com/eggie5/SDSU-
COMPE475-SPRING13/tree/master...](https://github.com/eggie5/SDSU-
COMPE475-SPRING13/tree/master/pipelined)

------
pdq
Verilator, which is also open source, is a much higher performance simulator,
as it compiles Verilog to C++ first, rather than traditional simulation like
Icarus.

[http://www.veripool.org/wiki/verilator](http://www.veripool.org/wiki/verilator)

~~~
blackguardx
But Icarus is also a synthesizer. Does verilator do synthesis?

~~~
zik
No it doesn't. It translates the verilog source into C which it compiles to a
native executable for simulation.

~~~
buserror
On a related note, ghdl [0] is a similar project but for VHDL. I spent a lot
of time using it before I switched to verilog, it's a pretty nice tool on the
other side of the fence.

[0]: [http://home.gna.org/ghdl/](http://home.gna.org/ghdl/)

