
Intel vs. NuFlare in multi-beam race - gooftiff
https://semiengineering.com/next-gen-mask-writer-race-begins/
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tlb
Why is mask write time such a big deal? They mention 24 hours as a general
upper limit, but given that silicon iterations take several weeks, it doesn't
seem like a major factor.

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turbohedgehog
Educated guess, one die will have many layers, requiring many masks for all
the layers

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dogma1138
Dies are one dimensional, making multi dimensional dies is the next challenge
in IC manufacturing.

Today we do use 2.5D transistors AKA FinFets but that's still as single layer.

Multiple masks are used however as creating the feature size expected today
with the wavelengths we have requires multiple patterning which means multiple
masks are used.

14nm today still uses the same 193nm lithography from 65nm if not earlier, the
only way to create features which are actually smaller than the wavelength of
the light is by using multiple hard mask and resist layers.

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turbohedgehog
Ah, they don't use masks for the metal and via layers?

