
Stanford Seminar – A Superscalar Out-of-Order x86 Soft Processor for FPGA - wolf550e
https://www.youtube.com/watch?v=vhHR6fNHyG8
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wolf550e
Slides:
[http://web.stanford.edu/class/ee380/Abstracts/190605-slides....](http://web.stanford.edu/class/ee380/Abstracts/190605-slides.pdf)

Author: [http://www.stuffedcow.net/](http://www.stuffedcow.net/)

The design was a PhD project that took a long time (I think 2011-2017, longer
than usual for such, I think).

The author now works at Intel.

The design was left unfinished, so no final benchmarks or even final clock
rate.

I was impressed watching this, but I have no idea how impressive it actually
is.

I wonder what experts int he field think.

I also wonder why there isn't an open source project to do something like this
(or finish this project, which I guess is open source?).

Would the techniques apply to an ARMv7 core? How much extra work is it to add
floating point and vector instructions (I guess a lot).

Would it be possible to teach a verilog compiler to do things that way instead
of the normal way which results in lower frequency?

