
Agile Paging for Efficient Memory Virtualization [pdf] - ingve
http://research.cs.wisc.edu/multifacet/papers/ieeemicro17_agile_paging_preprint.pdf
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crave_
"Even the TLBs in the recent Intel Skylake processor architecture, cover only
9% of a 256 GB memory."

Isn't that sort of a lot since the TLB is per context anyways?

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monocasa
The TLB is shared for the whole system. They added ASIDs so you can keep
multiple contexts around without flushing the TLB.

It's still not a great comparison though since TLBs are essentially cache. You
only need to keep your working set in them.

