

Hitting the Memory Wall: Implications of the Obvious (1994) [pdf] - hyperpape
http://www.di.unisa.it/~vitsca/SC-2011/DesignPrinciplesMulticoreProcessors/Wulf1995.pdf

======
phkahler
They don't consider a simple solution - static RAM. You can trade cost for
memory performance at any time. Although interconnect is becoming a
bottleneck, so we build bigger SRAM caches.

They also don't mention how compute requirements often scale faster than the
memory size. Some algorithms can be written in very cache friendly ways which
take advantage of this.

