
How the Father of FinFETs Helped Save Moore’s Law - matt_d
https://spectrum.ieee.org/semiconductors/devices/how-the-father-of-finfets-helped-save-moores-law
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tails4e
This guy is seriously impressive. As the article mentions the BSIM models
developed by him at Berkeley are the corner stone of all transistor
simulations today, modelling thousands of subtle effects - an impressive feat,
not only to build the accurate picture of a transistor and its environment
(the effects on the transistor function from being near others, etc) but also
to do it in a way that allows modern EDA tools to simulation 100k+ at once in
a reasonable amount of time.

It's also impressive he made impacts in so many different aspects,
transistors, solar cells, optical, etc. Well deserved award.

~~~
eternauta3k
If anyone is interested in what these transistor models are like, there's an
excellent online course by Yannis Tsividis:

[https://www.coursera.org/learn/mosfet](https://www.coursera.org/learn/mosfet)

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cooper12
The fascinating part of this article is the path it took for FinFETs to go
from a theoretical all the way to fruition. You have things like him hearing
about a DARPA grant last-minute from a surfing buddy. He also was working in
different areas throughout his career. Great quote:

> His career soon took a detour because semiconductors, he recalls, just
> seemed too easy. He switched to researching optical circuits, did his Ph.D.
> thesis on integrated optics...

~~~
eternauta3k
> him hearing about a DARPA grant last-minute from a surfing buddy

I was very disappointed to go the article and find that Hu does not in fact
surf:

> Hu had heard about the DARPA funding from a fellow Berkeley faculty member,
> Jeffrey Bokor, who, in turn, had heard about it while windsurfing with a
> DARPA program director

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DeathArrow
Unfortunately, it's not Moore's law that make the chips run faster, but
Denard's scaling and that seems to no longer work. [0][1]

[0]
[http://www.eng.auburn.edu/~agrawvd/COURSE/READING/LOWP/Boh07...](http://www.eng.auburn.edu/~agrawvd/COURSE/READING/LOWP/Boh07.pdf)

[1] [https://cartesianproduct.wordpress.com/2013/04/15/the-end-
of...](https://cartesianproduct.wordpress.com/2013/04/15/the-end-of-dennard-
scaling/)

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tanilama
So he made the biggest achievement in his life at the age of 48, and waited
another another 15 years for it to become reality. Never too late.

~~~
eternauta3k
I imagine most academics never see the impact of their work.

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bogomipz
What an amazing career. I had a couple of questions. The articles states:

>"The main problem was power. As features grew smaller, current that leaked
through when a transistor was in its “off” state became a bigger issue. This
leakage is so great that it increased—or even dominated—a chip’s power
consumption."

How exactly does residual current start to dominate? Does this mean that
current starts to leak into neighboring transistors and inadvertently turn
them on?

>"Hu saw the fundamental problem as quite clear—making the channel very thin
to prevent electrons from sneaking past the gate?"

I would have thought that making the channels thinner make current flow
through them easier. Why does making them thinner prevent current leakage
exactly?

~~~
PhantomGremlin
The word leakage used in the context of the article refers to a single
transistor, not neighboring devices.

See this Wiki article. What is commonly called "leakage" is more formally
called "subthreshold conduction". The two n+ areas of the FET are the source
and drain. In that particular picture a conducting channel between those two
would be formed when Vg is positive. The problem is that, for a variety of
reasons, when the devices are that small it is difficult to keep current from
flowing between drain and source even if Vg is zero.
[https://en.wikipedia.org/wiki/Subthreshold_conduction](https://en.wikipedia.org/wiki/Subthreshold_conduction)

In a "traditional" FET, as shown above, the channel is formed in the region
below the gate.

If you look at the "FinFET’s Features" illustration in the IEEE article the
orange area is where the channel can be formed. It is no longer simply "below"
the gate, but instead exists as a three dimensional structure. This gives the
gate voltage more control of the current flowing between source and drain.

~~~
brennanpeterson
A reasonably good physical picture is to imagine the transistor as a hose. The
gate is a valve, and basically works by smushing the channel closed. In
standard planar designs, the hose is smushed from the too, and eventually, you
cannot close off that flow. A finfet let's you smush that channel.closed from
three sides. And a nanowire or sheet let's you close it from all sides.

You can reasonably ask: why not make it really small and make sure it closes.
The reason is that you need current to drive the computation process.

So anyway, you balance these factors at each node, which is what BSIM lets you
do.

~~~
bogomipz
>"And a nanowire or sheet let's you close it from all sides."

Interesting so is this why we see the research into carbon nano-tubes or is
that something else?

>"So anyway, you balance these factors at each node, which is what BSIM lets
you do."

What is BSIM here?

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lawrenceyan
I've seen Professor Hu on campus a few times, and it was a really cool
experience being able to talk to him in person. I only wish I could have taken
a course with him, but he doesn't do as much teaching unfortunately these
days.

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Causality1
We're really good at scaling and getting more performance per watt but it
seems like our performance per transistor is essentially stagnant. Is this an
area where we could focus development as silicon shrinking dies?

~~~
eternauta3k
Scaling _is_ improving single-transistor performance, specifically the
switching time / transition frequency.

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0xff00ffee
I had no idea he started work on FinFETs in the 90's. That's crazy because I
worked on them at Intel during the first process (which was an absolute beast
to bring up), and I just assumed they were a new tech. Funny that often the
people on the cutting edge don't get a chance to appreciate the history.

~~~
bogomipz
>"That's crazy because I worked on them at Intel during the first process
(which was an absolute beast to bring up)"

Could you elaborate on this? Do you mean bringing the the process node/fab
online? More so of a beast than other other nodes? Cheers.

~~~
0xff00ffee
No, I can't elaborate because I wasn't on the process team, I just used their
parameters. I watched the agony on faces of friends on-call 24/7 who owned the
yields... that was close enough for me. :)

Yes, I meant bringing up the process node.

Yes, more so than other nodes, but for context I only go back to p854, so
earlier might have been worse.

~~~
eternauta3k
Were you in charge of the models? If so, any resources you could share?
Conferences, books, whatever.

~~~
0xff00ffee
Oh hellz no! I was just a consumer. Lots and lots of people use the process
files for all kinds of modeling (hundreds of models). And every time a new one
comes out we all spend a month switching over to it... and another month
explaining to our bosses why everything got worse!

The people in charge of the model need to be very smart, very diplomatic, and
very thick-skinned because every release they have literally hundreds of
managers and project leads screaming at them.

~~~
eternauta3k
I know what you mean. Designers are more worried about simulation results not
changing, than they are about matching reality better :)

