

Intel's 10nm 'Cannonlake' delayed, replaced by 14nm 'Kaby Lake' - Moshe_Silnorin
http://www.techspot.com/news/61103-intel-10nm-cannonlake-delayed-replaced-14nm-kaby-lake.html

======
eloff
The article is saying 10nm is delayed indefinitely. The supporting evidence is
not there. Intel is not commenting, and kaby lake likely just means that 10nm
will take more time. After 14nm broadwell was delayed a year, this is not a
big surprise to anyone.

The day will come when feature shrinkage will end for silicon based chips, but
it is not this day. I hope!

~~~
jolan
Just seems like they're backing off from publicly committing to a timeline
(and probably giving themselves more time to get 10nm right). Which makes a
lot of sense given how 14nm went and how long it took to get yields up to
acceptable levels.

[http://forwardthinking.pcmag.com/none/329835-intel-sees-
path...](http://forwardthinking.pcmag.com/none/329835-intel-sees-path-to-
extend-moore-s-law-to-7nm)

> Krzanich said the company thinks it signaled too much of its intentions to
> the industry about its 14nm plans, so "we'll be a bit more prudent in
> releasing information" about new manufacturing nodes. He wouldn't commit to
> the company's familiar Tick/Tock cadence of releasing a new process node one
> year and a new architecture the following year, though Smith said the
> company expects to be on a "fairly normal cadence" and "will talk about 10
> nm in the next 12 or 18 months when appropriate."

They've stated in the past and recently reiterated that they have a clear path
to 10nm.

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Retric
A significant fraction this slowdown relates to Intel’s integrating graphics
with their CPU's which not only costs silicon, but also adds heat. Intel has
then traded most of their process gains into improving the terrible graphics
performance to a near acceptable level at the cost of minimal CPU gains.

Sadly without real ed: competition Intel quickly stagnates. And AMD is still
far behind the curve.

~~~
batou
I'm using a 5 year old laptop with intel graphics. It's fine for everything
other than CAD and gaming. The former I don't do and the latter I have an
XBox.

Perhaps the market isn't there so this is no biggy?

~~~
freehunter
The PC gaming market certainly is there, and Intel graphics are very good
these days. There are few games that cannot be played on Intel graphics now,
compared to back in the GMA 900 days when almost nothing at all would run on
an integrated chip.

~~~
dlevine
Also, the GMA series of graphics chips were actually integrated into the
motherboard rather than the CPU. By going with processor graphics, Intel has
managed to reduce by at least one the number of chips that goes into a system,
allowing for even smaller designs than before.

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solomatov
It seems that we almost reached the limit of Moore's law. 5nm seems to be a
physical limit at least for sustainable changes of current technologies.

~~~
bryanlarsen
Reference "The Boy who cried Wolf". That pronouncement has been made and
proven wrong way too many times for anybody to take it seriously. Eventually
the wolf will come and the limit will be reached, but until it happens nobody
will believe it.

~~~
solomatov
But how is this is possible? Diameter of silicon atom is 0.2nm and we need at
least several atoms to create a transistor. I am sure Intel will be able to
fulfill its roadmap to 4nm, maybe 2nm, but at this size quantum effects are so
large, that everything should be changed.

~~~
ZenoArrow
It'll be interesting to see the parts that silicon photonics and molecular
assembly come to play in meeting the future process nodes.

I agree with those who say we'll reach a cost barrier before we reach a
technical barrier. If I were to make a wild guess, I'd say 7nm will be that
limit, and that it'll be about 5 years away (Moore's Law is already broken and
isn't likely to be fixed any time soon, hence the slower timeframe).

~~~
marcosdumay
A cost barrier is the most common manifestation of a technical barrier.

There's no way silicon microlitography will keep working once transistors are
just a few atoms big. In fact, at 10 nm tunnel currents should be already a
big problem on all sides of the transistors, and not constrained to the gate -
channel insulation anymore.

~~~
ZenoArrow
>"There's no way silicon microlitography will keep working once transistors
are just a few atoms big."

That's why I mentioned molecular assembly.

>"In fact, at 10 nm tunnel currents should be already a big problem on all
sides of the transistors, and not constrained to the gate - channel insulation
anymore."

That's why I mentioned silicon photonics.

> "A cost barrier is the most common manifestation of a technical barrier."

It can be, but not always. We can definitely move beyond 7nm, we've already
done it in the lab, but knowing if we can find ways to afford the costs of
manufacturing below that point is not as clear.

[http://www.purdue.edu/newsroom/research/2012/120219KlimeckAt...](http://www.purdue.edu/newsroom/research/2012/120219KlimeckAtom.html)

------
asanagi
I think we'll enter a paradigm where R+D costs will drive the price of
successive generations of CPUs back up to the level of the early '90s or even
before. We're near the end of the road scaling down the same designs with
improved photolithography techniques. Eventually, we'll find a new dimension
to optimize on, and then rapidly progress in that direction, which will lower
prices again.

------
jezfromfuture
This was like news 3 weeks ago , now its just known facts..

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MikeNomad
I would think the Cannonlake delay is more about HVAC / Clean Room
environmental controls for particles at 10nm than the actual chip fab.

~~~
MikeNomad
Yeah, the litho process is largely the same. Thanks for furthing the idea I
was trying to get across: The hang up is not in the production process, it's
in the environmental controls.

To put it another way, if I manufacture on a smaller die size, I have to
control for smaller pieces of junk in the air. If I don't, I will get poor
(read, not cost effective) yields, making production in that environment a bad
business decision.

