

 Altera's Secret Processor Unveiled: a Quad-Core ARM Cortex-A53 - rbanffy
http://www.eetimes.com/author.asp?section_id=36&doc_id=1319935&itc=eetimes_node_193&cid=NL_EET_ProgrammableLogicDL_20131031&elq=8f9b1617db444809bf1cac376e20c796&elqCampaignId=2136

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jwise0
As far as I can tell, the AArch64-ness of these parts is only half of the
(very exciting!) story ... the _really_ interesting thing is that these are
being manufactured on Intel's 14nm FinFET process. To date, I didn't think
anyone was doing FPGAs on Intel's process except for Achronix, and they're
relatively low-volume... so high-volume FPGAs (and with ARM cores, no less!)
on a leading-edge Intel process is truly astounding.

These will be ghastly expensive parts, that much is for sure, but they have
the potential to be _really_ fast. I've always been a Xilinx user, but I will
absolutely give credit where credit is due here: Altera seems to have pulled
off something pretty remarkable. I'm excited to see what performance is like
when these actually show up.

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FullyFunctional
There's also Tabula. Amusingly, both Achronix and Tabula claims to be the
first [FPGA] vendor on Intel's fab.

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hershel
Have anybody used tabula? What is their pricing/performance levels? Is their
marketing true?

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carterschonwald
I do know that they have Conal Elliot and that he's been exploring compiling
Haskell to their space time architecture. Though I gather that's still a ways
off from being for general consumption

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lambda
I wonder how much more successful FPGAs would be if you could actually write
your own compilers for them.

As of now, as far as I can tell, none of the major FPGA vendors actually
document the actual format of their programming. You have to use a compiler
from them to compile a netlist down to the raw bytecode that's actually sent
to the FPGA to program it.

This means that there are many potential uses of an FPGA that you just can't
do. For instance, you can't write a GLSL shader compiler that compiles down to
an FPGA on the fly, or compile OpenCL to an FPGA, or add a language extension
that compiles certain highly parallelizable statements in your language down
to an FPGA.

It seems that FPGA manufacturers are missing out on an awful lot by not
actually opening up their hardware to experimentation by third parties. Anyone
know why exactly they act this way?

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jwise0
You can write the tools you describe on top of any existing tool stack --
you'll just have to use the hardware description language as an IL. (Indeed,
many tools already do this.)

You could write your own synthesis front-end and place-and-route back-end, but
they're not like any compilers you've ever seen before. (A recent Coursera
class [1] went into pretty good detail about how synthesis and place and route
work.) I think that the unfamiliarity is probably why there are no Open Source
toolchains for it.

For Virtex-II platform, Xilinx provided a tool to edit bitfiles, called JBits
[2], but it seems to be well and truly dead[3].

[1]
[https://www.coursera.org/course/vlsicad](https://www.coursera.org/course/vlsicad)

[2]
[http://www.xilinx.com/labs/projects/jbits/](http://www.xilinx.com/labs/projects/jbits/)

[3] [http://forums.xilinx.com/t5/Virtex-Family-FPGAs/Question-
abo...](http://forums.xilinx.com/t5/Virtex-Family-FPGAs/Question-about-
JBits/td-p/33215)

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lambda
Sure, you could use tools that target the HDL as an IL, if you wanted to write
that code yourself and then ship it to your customers as a binary blob, as
their HDL compilers need to be specifically licensed, and aren't, as far as I
know, something designed to be used as a back-end component in shipping
software.

But that limits its usefulness for something like, say, writing a GLSL
compiler so you can use your FPGA as a GPU, and are then able to run arbitrary
GLSL code on it.

I agree that it's definitely a much different than writing a compiler backend
for a CPU. You are definitely going to have different abstractions that will
apply well to it. But that's fine; that's what I'm interested in, writing a
compiler for a very different kind of platform. The problem is, as far as I
can tell, they don't document their actual bitstream format, so you must use
their licensed tools any time you actually want to compile something new for
the FPGA. And that precludes a lot of use cases.

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ChuckMcM
As the author points out in the comments these are targeted for "high end"
applications like crypto processors. I've got one of the Zedboards [1] and I
really like the basic board, but damn if it isn't nearly impossible to set up
with Xilinx tools. The Quartus tools from Altera are a bit better but they too
have their quirks. I keep hoping pg will get a chance to fund a startup that
is doing the HDL equivalent of PHP :-)

[1] http:://www.zedboard.org

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selimthegrim
I know these guys just applied to YC:
[http://tempoautomation.com/](http://tempoautomation.com/)

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frisco
I don't think that a robot like Tempo Automation's is the issue. We have low
cost cncs and pick-n-place machines, and more importantly places like sierra
circuits. The harder problem is, like ChuckMcM described it, an easy to use
high level abstraction over the hardware to simplify and accelerate the design
process. Fabbing a board isn't the hard part.

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joars
Wow, am i mistaken here or are we witnessing the shift to an computing
landscape where fpga's with hardcores like arm are the de facto standard vs
asic's of today? And will this remove xilinx from the throne of fpga market
leader?

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hershel
This chip will probably cost $8000 or more. equivalent asic's will cost much
less.And yes,the problem with ASIC is the higher development cost(NRE), but
companies like baysand and especially easic offer low NRE chips with
performance/price close(r) to ASIC.

The nice thing about those companies, is that this low NRE and possibility to
do low volumes , might open ASIC's to startups and niche applications.

One such example is VMC that builds bitcoin mining chipsets using easic.

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subway
I can't help but wonder how much this would have impacted Bunnie's laptop
design if it were available when he began work.

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bryanlarsen
I don't think Bunnie would contemplate replacing a $10 CPU and a $20 FPGA with
an integrated one that costs $4K - $20K. :)

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aortega
Zynq, the Xilinx equivalent of this cost from 50 u$s up to u$s 4000. Also the
Zynq was already available by the time Bunnie started his project, that's why
I never like it.

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warble
how well does a DSP mine bitcoins?

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wmf
Poorly now that Bitcoin ASICs exist.

