
Will RISC-V Revolutionize Computing? - signa11
https://m-cacm.acm.org/magazines/2020/5/244325-will-risc-v-revolutionize-computing/fulltext
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klelatti
I like the idea of RISC-V, applaud the designers and wish it well, but there
is a lot of slightly purple prose here about the benefits of an open and
'free' ISA.

I can see how RISC-V works for SoC designers who either 1. Want to cut costs
to a minimum or 2. Want to add their own proprietary extensions to distinguish
it from the competition. I'm less sure that it works for everyone else.

The instruction set running on your Raspberry PI is the same as that running
on your iPhone which in turn is the same as that running on an Ampere Server.
Do we really want to be faced with a multiplicity of distinct ISAs?

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ksec
It kind of "depends".

People are talking about cost of licensing, but the cost of ARM are peanuts
compared to cost of design and fabrication. I am not even sure if the word
peanuts correctly describes it.

ARM has made changes that you no longer need some one-off fees before you
start producing "certain" ARM design. You get access to it and only paid for
it once you start making revenue.

RISC-V makes sense for tiny microcontroller that ships in tens of millions.
Western Digital saves millions every year just by switching to RISC-V for
Microcontroller used in their HDD.

RISC-V's main competition is the like of ARC and some other DSP. It is
competing with ARM in certain segment ( or the old ARM embedded segment ). But
it is not competing ARMv8.

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klelatti
Agree 100%.

No argument that RISC-V is both interesting and has a lot of value. Just not
that enthused by the "a new golden age" and "will eventually supplant x86 and
ARM" commentary being presented (primarily) on the basis of ISA customisation
without a broader discussion of the pros and cons and wider market issues.

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ncmncm
Me, I'm ready for a RISC-VI or RISC-W.

It would be quite a lot like RISC-V, except it would:

\- have rotate instructions in the core set

\- have popcount instructions in the core set

\- represent bool `true` with ~0 in the ABI

\- have all the add, subtract, and comparison instructions set two registers
(in addition to the destination), one to 0 and the other to ~0, according to a
test of the result.

\- have conditional branch and conditional move designate a register to be
tested for equality to zero. Conditional move would move from one of two
register sources, either of which could be the same as the destination.

\- have two ISA registers fixed at 0 and -1.

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Pet_Ant
Sorry, but why do you need it in the base set? If it’s a modular chip that
also works for other applications then the base should be as slim as possible.
As long as your targets all support it and likely any desktop chips would.

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ncmncm
"As slim as possible" includes popcount and rotate, along with add and shift,
if you seriously mean for a design to be useful.

