
TLB and Pagewalk Coherence in X86 Processors - jsnell
http://blog.stuffedcow.net/2015/08/pagewalk-coherence/
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bgilroy26
If -- like me -- you have never gone through a university Operating Systems
course, you might find the following short Udacity videos helpful.

This one motivates virtual memory:

[https://www.youtube.com/watch?v=3kRBVdnLBW4](https://www.youtube.com/watch?v=3kRBVdnLBW4)

This one gives a high level view of how everything works:

[https://www.youtube.com/watch?v=l7HoguhFVQ4](https://www.youtube.com/watch?v=l7HoguhFVQ4)

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nkurz
_Perhaps this suggests that memory accesses from pagewalks are cached in the
L1 cache (i.e., pagewalks compete for L1 cache space)?_

Is there actually doubt about this? I'd been taking for granted that page
walks went through the standard cache hierarchy on recent Intel, but I guess I
don't have a definitive source for this belief.

