
HardCaml: Register Transfer Level Hardware Design in OCaml - edwintorok
https://ujamjar.github.io/hardcaml/
======
avsm
I've coincidentally just ordered an Altera SoCKit to play with this more over
the summer. There's a nice tutorial on getting started with HardCaml and the
SoCKit at [https://ocaml.io/w/HardCaml](https://ocaml.io/w/HardCaml)

------
gricardo99
What's the motivation for this? I've seen a few HDLs recently similar to
this[1][2].

I'd love to know why someone would develop one of these HDLs rather than work
with one of the "mainstream" HDLs (i.e. system verilog, VHDL, System C)?

[1] - [http://www.clash-lang.org](http://www.clash-lang.org)

[2] - [https://chisel.eecs.berkeley.edu/](https://chisel.eecs.berkeley.edu/)

~~~
krupan
If you have ever worked with a mainstream HDL you know how frustrating they
can be.

~~~
gricardo99
care to give an example?

I've worked plenty with HDLs (mainly system verilog) from large ASIC projects
to smaller FPGA prototyping projects. I could guess at a couple ways these new
HDLs could possibly address some of the pain points, but it's not clear that's
even their purpose.

------
cmrdporcupine
HDL newbie here -- how does this compare to Chisel (Scala -> Verilog)?

~~~
doc_holliday
Here are some module design equivalents:
[http://www.ujamjar.com/hardcaml/chisel.html](http://www.ujamjar.com/hardcaml/chisel.html)

As far as performance of what it synthesises down to, I have no idea as I have
used neither.

Are you complete newbie to HDL?

~~~
cmrdporcupine
Not total newbie, I've played with System Verilog and Chisel. Done some
fiddling in simulators. But never synthesized to FPGA, though I have a board
here I'll find the time to play with someday. I'm a software guy dabbling in
hardware.

