

Pebble Time Smartwatch Teardown - mzehrer
https://m.youtube.com/watch?feature=youtu.be&mc_eid=fa34acfcfc&mc_cid=8210b1c2af&v=MDJ0EOkU_Fg

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quadrature
Got to love Dave's commentary, Always learn a thing or two from his teardowns.

I wonder if anyone from pebble can comment on the FPGA, I thought that was a
bit odd as well, Is it just so that the processor can sleep as much as
possible and doesnt have to wake on small trivial things ?.

~~~
ctz
Probably to drive the memory LCD. The drive timing in the datasheet looks
pretty tight (about 2.2MHz), and bit banging at that rate will leave the uC
unable to much else during a screen update. Ideally, you want to make use of
the STM32F439's 2D graphics accelerator to do graphics legwork, then the DMA
controller to write out to the screen.

The FPGA could even have been provided by the LCD vendor to provide a more
standard interface.

~~~
ctz
Replying to myself: this was actually confirmed by one of the developers on
reddit:

[https://www.reddit.com/r/pebble/comments/37lg95/ifixit_pebbl...](https://www.reddit.com/r/pebble/comments/37lg95/ifixit_pebble_time_teardown/crnr78a?context=10000)

