Ask HN: Could a soft FPGA be designed in an HDL to run on a hard FPGA? - peter_d_sherman
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peter_d_sherman
This is purely a theoretical question. Think virtual machine but in FPGA
terms.

Could a meta FPGA, an FPGA that runs on top of an FPGA, be created in an HDL
language? Why or why not?

Yes, if it worked, it would probably be much slower and less functional than
the original FPGA, and would serve no commercial purpose.

But theoretically, could it be done? Why or why not?

~~~
tlb
I don't see why not.

If you define an FPGA as taking a bitstream configuration input, then you'd
have to write (in Verilog) an engine to interpret that input and configure
some LUTs and routing switches. Routing switches are efficiently implemented
in an FPGA, but emulating one might require hundreds of other switches. So
it's going to be very inefficient.

~~~
peter_d_sherman
Interesting! I ask the question from a theoretical standpoint only. Yes, it
would be slow if it was done, no question about that! But maybe it could find
use as a way of testing/validating a correct HDL FPGA design before
manufacturing actual hardware...

~~~
banjo_milkman
Many ASICs are tested as 'soft' designs on FPGAs before becoming ASICs, which
is essentially the same idea. It is a lot faster than verilog simulators.

