

NeoVGA: Neo Geo Line Doubler in VHDL - sizzle
http://mikejmoffitt.com/wp/?p=270

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jwise0
Very good work.

PLLs can be a little scary if you're instantiating them by hand for the first
time, but as long as you know the incantation to do it on each platform, it's
not too bad. Both platforms (Altera and Xilinx) have 'megafunction' wizards
that can generate the PLLs for you; alternatively, if you have a library of
stuff around to copy and paste, that works too.

If you need something to copy and paste a very basic PLL from (i.e., none of
the advanced features, like variable feedback or chained PLLs), my Xilinx
basecode[1] has an example, as does my Altera basecode[1].

Cool to see more people experimenting with FPGAs!

[1]
[https://github.com/jwise/vterm/blob/master/VTerm.v#L1](https://github.com/jwise/vterm/blob/master/VTerm.v#L1)
[2]
[https://github.com/jwise/c5g-basecode/blob/master/demo.v#L2](https://github.com/jwise/c5g-basecode/blob/master/demo.v#L2)

