
Samsung announces first 3nm PDK - kristianp
https://www.anandtech.com/show/14333/samsung-announces-3nm-gaa-mbcfet-pdk-version-01
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baybal2
To add to that, I recently heard that Intel is about to jump the Synopsys ship
for Cadence.

I was completely dazzled thinking "what to they get from that?" until it hit
me that only Cadence has 7nm TSMC and Samsung workflow ready.

This made me thinking, is Intel finally thinking about doing 7nm tapeouts at
TSMC or Samsung?

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rathel
> only Cadence has 7nm TSMC and Samsung workflow ready.

I think you're not right, unless I am missing something.

[https://news.synopsys.com/2018-04-30-TSMC-Certifies-
Synopsys...](https://news.synopsys.com/2018-04-30-TSMC-Certifies-Synopsys-
Design-Platform-for-High-performance-7-nm-FinFET-Plus-Technology)

[https://news.synopsys.com/2018-06-22-Synopsys-Custom-
Design-...](https://news.synopsys.com/2018-06-22-Synopsys-Custom-Design-
Platform-Accelerates-Robust-Custom-Design-for-Samsung-Foundrys-7LPP-Process-
Technology)

~~~
baybal2
Well, nice to know that. Nevertheless, Cadence was first to get to 7nm, and is
still ahead with never versions of 7nm processes like 7HPC.

To my knowledge, they are the only one who have just anything workable for EUV
based processes.

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bufferoverflow
That's pretty wild. Most atoms are 0.1-0.2nm in diameter.

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exabrial
Kinda makes me wonder what the absolute limit is. Is a 3 atom transistor
possible?

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creatornator
Going much smaller than we have right now, and you run up against some exotic
issues--if you decrease the dielectric thickness, you run the risk of break
down between the gate and source/drain under normal operating conditions. Your
steady current rating also drops dramatically if the other feature sizes are
decreased. I would probably say a 3 atom MOSFET is not possible, since at that
scale you can't really have an effective dielectric between the atoms, and the
conductors connected to the "single-atom terminals" will have a bulk effect on
the behavior.

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permatech
> if you decrease the dielectric thickness

This is why people are moving away from planar transistors to "FinFets" and
eventually having an "all around gate"

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donnietb
Can someone elaborate on how this translates to the actual performance of GPU.
What is the performance jump (will this allow to run 4k x 4k per eye VR
headset) when compared to current GPU generation ?

Today Even with Nvidia 1080 cards running 2k x 2k per eye headsets is not an
easy task and beyond a smooth VR experience.

~~~
ksec
GPU scales really well with transistor count and You can expect about double
the performance with best of 7nm, and likely another double for 3nm. So you
are looking at 4x the performance.

Of course this does not take into account about TDP, Clockspeed, Memory Speed,
Cost of Die Size etc. What is technologically possible may not be economically
possible. We are going to need much faster memory, GDDR7? or HBM3, how much
would those cost?

And a 3nm ( Whether that is from Samsung or TSMC ) Nvidia GPU will likely be
2022 or 2023 at the earliest.

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blattimwind
> And a 3nm ( Whether that is from Samsung or TSMC ) Nvidia GPU will likely be
> 2022 or 2023.

That seems really optimistic to me.

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ksec
Edited a bit, Nvidia has always been late ( or waiting for it to mature ) to
leading node. So in reality we are looking at 2024 / 2025 for mainstream part.

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HeWhoLurksLate
That _still_ sounds quite optimistic to me.

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syntaxing
I'm super curious in the semi technology to create 3 nm layers or beyond.
There's not many processes to choose from to begin with thats scalable with
adequate uniformity. Do they use some sort of MBE process?!

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baybal2
Rumours heard by me were of apple's tapeout on 7nm being tragically low yield
in between 30 to 40% (throwing away half of the wafer,) but also that TSMC
eventually got 7nm yields into sane values.

New processes almost always have a yield drop, followed up by recovery, but
anything below 50% is really unprecedented.

Apple 12 is not that of a huge chip. It is big for a mobile SoC, but smaller
than say a mainstream gaming grade GPU.

I greatly doubt the use of MBE, most likely some regular kind of epitaxy + a
lot of process control and swearing to get it right. MBE would've increased
cycle times way too much (need for ultra deep vacuum and 0 impurities)

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ItsTotallyOn
The information in the article is incorrect. The PDK gives more performance OR
more power, but not both. Other reporters have this correct, while this
article is incorrect.

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IanCutress
Samsung's own slides state:

Fmax +50% Power @ Fmax -40% Power @ isoperf -50%

Different parts of Samsung aren't talking to each other.

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elorant
I was under the impression that at this scale you have quantum tunneling
issues.

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basementcat
You have "quantum tunneling" well before this process node. Otherwise, flash
memories wouldn't work.

