
Why Doesn't Intel Put Say 1GB of L2 Cache in CPUs? - henning
https://www.quora.com/Why-doesnt-Intel-put-say-1GB-of-L2-cache-in-CPUs?share=1
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soganess
A tangentially related question I've wonder for a while is:

What type of improvements can be made to L3/"L4"(I'm unsure if that is what
intel calls crystalwell and its derivatives) to improve the latency such that
access related penalties/IPC lose reach the same diminishing return point that
512KB of L1 provides to registers.

[https://www.anandtech.com/show/14694/amd-rome-epyc-2nd-
gen/7](https://www.anandtech.com/show/14694/amd-rome-epyc-2nd-gen/7)

It almost looks like AMD is doing just that. The first 4MB of L3 is almost as
fast as L2. That said there seems to be quite a steep penalty for 8MB, and
reaching 16MB is only a hair faster than going out to main memory. I translate
that last concession as AMD not believe such an event will occur very often.

The penalty for values greater than 16MM is especially slow when one considers
the added "hop" the Rome architecture has with regards to it's memory
subsystem. Intel's offerings don't seem quite as hampered when working with
larger sizes but do incur more of a penalty for using L3 at all. Perhaps
someone with a CE/EE background could shed some light on the matter?

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johnwish007
Intel is so focused on server chips it forgot all about the desktop. AMD is
killing it.

