
Designing a CPU in VHDL, Part 2: Xilinx ISE Suite, Register File, Testing - skywalker_
http://labs.domipheus.com/blog/designing-a-cpu-in-vhdl-part-2-xilinx-ise-suite-register-file-testing/
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jeffbush
My recommendation for anyone starting CPU design is to not use the vendor FPGA
tools for simulation. The simulators they bundle are often crippleware, and
the vendor IDEs are painful. You're going to spend the majority of your time
debugging your design in simulation, so setting up a good environment is
important. There are a lot of great open source simulation tools now:

    
    
      - Verilator (Verilog) -- http://www.veripool.org/wiki/verilator
      - Icarus Verilog -- http://iverilog.icarus.com/
      - GHDL (VHDL) -- http://home.gna.org/ghdl/
      - GTKWave (waveform viewer) -- http://gtkwave.sourceforge.net/
      - For people who want to be a bit more cutting edge, there's also Chisel: https://chisel.eecs.berkeley.edu/
    

If you're an emacs person and using Verilog, I'd also recommend Verilog Mode:
[http://www.veripool.org/wiki/verilog-
mode](http://www.veripool.org/wiki/verilog-mode)

I invoke the vendor FPGA synthesis tools from the command line with my
makefiles, which saves me the hassle of using their GUIs

The one case where I think the GUI is useful is is the netlist viewer, which
can help you understand what the synthesis tools are producing. This is
especially helpful when starting out.

~~~
blackguardx
What about floor-planning or post place-and-route netlist viewing? Some things
are pretty hard to do without the vendor's tools. Also, Xilinx tools are
universely renowned for being terrible, but Altera's toolchain can be pretty
decent. It at least approaches the quality a 90s programmer would expect.

~~~
jeffbush
You know, I've personally never needed to use the floor-planning tools. It
seems like a pretty advanced option. Of course, using open source
simulators/command line flow doesn't preclude opening the floor planning tool
in the GUI when you need it (my command line based synthesis flow just invokes
the same tools that the GUI does).

I find the post place-and-route netlist viewer inscrutable. I have debugged
some synthesis issues by generating the post synthesis simulation model in
Verilog and digging through that in a text editor. Maybe that's a weird way to
do it, but I find it much faster and easier, especially when I know the signal
names I'm looking for.

My main problem is with the Altera GUI tools. It's a personal preference thing
obviously, but I'm pretty attached to my editor, as are most people.

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therobot24
I remember doing this stuff in my computer architecture classes, Xilinx is
incredibly powerful but also incredibly painful to use.

~~~
baldjinx
I agree that the Xilinx tools are not so easy to use, but I feel that they are
far from painful.

I am amazed with the functionality of the free version of ISE (both in
simulation and floor plan design). I have used this software to prototype and
implement a 3rd order pipelined sigma-delta modulator on a FPGA, and several
simple CPLD projects which didn't require simulation.

The simulator is far from crippled. I was able to read input from a binary
test vector file into the simulator, run it though the model, and save the
output to file. I found this very useful during development to compare the
VHDL implementation with the prototype I had written in C.

