
J-Core Open Processor - ingve
http://j-core.org/
======
zokier
Oh Renesas are ex-Hitachi; well that explains a lot how such a unfamiliar name
is one of the top chip companies. Reminds me of the convoluted pattern where
Motorola split into Freescale who were acquired by NXP who in turn are ex-
Philips. Occasionally I feel the need for some sort of chart of the semi
industry to keep track who is who.

~~~
bgorman
Fun fact: Broadcom is now actually a former HP spin-off spin- off
(HP->Agilent->Avago), but is now worth more than Hewlett Packard Enterprise,
HP Inc, Agilent and Keysight combined.

~~~
ksec
> Broadcom is now actually a former HP spin-off spin- off (HP->Agilent->Avago)

Um... Not Strictly true. Broadcom is; Broadcom. Avago purchased Broadcom, and
uses its name, but traded using AVGO ( I could never understand why ).

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mattst88
Oh, the website is back up. It's been down for months and the project seemed
to have gone into stealth mode (or maybe died). Still no news for about three
years though. Unsure why this is being posted now, unless I've missed some
news.

Interesting project, if it is still alive.

~~~
eggsome
I think they are still alive, there are some talks like this one that are not
listed on their website:
[https://www.youtube.com/watch?v=o0milqmt4ao](https://www.youtube.com/watch?v=o0milqmt4ao)

Personally I think they need someone with the time to engage with/build a
community. At the moment they only seem to have people actually building
things, nobody is acting as an evangelist.

~~~
freemint
Neat, i've been following them for years but never saw that one!

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ncmncm
I am seeing more and more of what look like viable alternatives to RISC-V.
Agner Fog has an ISA with vector instructions that should influence all future
designs. The Bitmanip extension to RISC-V is likewise an education, and should
inform any future designs.

RISC-V itself? The core design seems very academic. Seriously, who omits
rotate instructions?

~~~
CalChris
Yeah, RISC-V omitted rotate from its 47 instruction base ISA. You don't get to
be that small without cutting the unnecessary and rotate would require a
barrel shifter which in turn would rarely be used. Instead, rotate (rol, ror,
rori) can be found in the _“B” Standard Extension for Bit Manipulation_.

~~~
ncmncm
Rotation costs exactly the same to implement as shifting, and shares the same
hardware, so has about zero marginal cost.

"Academic."

~~~
microcolonel
An "academic" design is better than the armchair design of somebody who
doesn't know how barrel shifters are implemented. Sure, you could microcode
it, but are the instructions really that big?

~~~
sifar
The parent is right. The HW is not much different. You don't need to microcode
them.

~~~
microcolonel
If you don't have a barrel shifter in your design, but your design is
microcoded, you may choose to implement a rotate with a few μops, much the
same way that you would write it in software.

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jchw
Neat, although I’d like to hear some motivations and maybe how it stacks up to
other open cores.

> Numato provides a GPL-licensed python3 tool to flash bitstreams onto their
> board. [TODO: port to python 2]

Well, they have a great sense of humor.

~~~
freemint
There was a publication in IEEE COOL Chips 21 (2018) [978-1-5386-6103-1/18]
which compared a closed source implementation by a company (whose founder was
involved in the creation of SuperH i think) of SH2 with RISC-V and an historic
(pirate (as in patents were not expired then)) implementation of SH2 called
Aquarius by some hobbyist.

The comparison seems to have some methodological flaws. But one result is,
that is unaffected by them in my opinion is "that 2 stage SH2 re-
implementation" needs fewer FPGA resources than "that 2 stage RISC-V re-
implementation" on the same hardware at the same clock.

That honestly does not say much but it is the best comparison i am aware of.

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cereal_console
I recently did technical deep dives on my late model Volvo XC90 and XC60. I
was amazed to still see SuperH SH4 processors in use in various parts of the
telematics system.

~~~
xeeeeeeeeeeenu
All CASIO graphing calculators use them too.

~~~
bpye
Had fun hacking on one of these calculators back in secondary school.

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freemint
I've been following them for a while.

The community communication has lot's of room for improvement. For example the
mailing list is down for over an year. The website is not really updated. All
communications happens p2p over eMail or is not logged like the IRC. This is
frustrating.

Their roadmap did not work out because no plan survives contact with the
enemy. From what i gathered J4 and J64 were targets in which there was not so
much interest. (The customer demand was for J1 and even smaller ones from fabs
who want to add it to their library.) They actually made it past J2 since J1
is available here
[https://github.com/cr1901/jcore-j1](https://github.com/cr1901/jcore-j1) .
Note: this is hosted by a community member not J-Core itself.

The past development model seem to have been: Develop solution in house for
client at SE-Instruments, ask if they can open source it later.

There was a push on #j-core on Freenode for a new source release last week but
nothing has materialized yet.

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tachyonbeam
Neat, but it looks like this hasn't been in development since 2016. I would
think it's probably best to use a RISC-V design if you want an open RISC CPU
core to put on an FPGA. You'll get better compiler and tool support, and
probably a wider variety of available designs.

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ch_123
They had a rather ambitious roadmap, seems like they didn't make much progress
past J2 (as least in terms of what has been released)

~~~
freemint
There is a J1 release:
[https://github.com/cr1901/jcore-j1](https://github.com/cr1901/jcore-j1)

