

A Look at Altera's OpenCL SDK for FPGAs (2013) - ironchief
http://www.anandtech.com/show/7334/a-look-at-alteras-opencl-sdk-for-fpgas

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morrad
As someone who regularly writes RTL for FPGAs during their day job, I like the
idea, but am skeptical about the follow through.

For years now, various companies have tried to make cross compilers to be able
to synthesize C style code into RTL. The name for this basic idea is "High
Level Synthesis" (HLS). For applications like digital signal processing, HSL
is actually decent. Having a stream of data moving through some transform is
easy to express in C (and OpenCL), and easy to translate into a relatively
efficient data pipeline in RTL when compared with making one "by hand". But
this isn't the only thing that is going on within the FPGA. It is clunky and
inefficient to create state machines or controllers, interact with inbuilt
memory blocks, or interface with other modules not built in the HLS language.

Since inefficiencies cost resources, you end up trading your decreased
development time through using HLS for possibly increased device costs, and
some ambiguity in terms of the architecture of the hardware your synthesize.
Since these tools haven't been broadly embraced by the FPGA coding community,
the support for them doesn't tend to last long either.

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apendleton
I would guess that the interesting comparison isn't this vs. alternate FPGA
approaches, but this vs. alternate OpenCL targets (GPUs, especially). For
people that already have OpenCL written to solve their problem, they're going
to want to know if the performance will be better per unit cost as compared to
whatever they're running it on now, and it sounds like at least in some cases
the FPGAs will do better than GPUs, so it's still a net win even if you could
do it even faster by writing Verilog.

Obviously it won't work for every problem, but the problem classes you mention
being a poor fit (state machines, etc.), nobody is using OpenCL for anyway...
super-branchy code like state machines performs badly on GPUs, which are
currently the main OpenCL targets.

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ironchief
For those that like to dig deeper, here is a white paper by Altera on
"Implementing FPGA Design with the OpenCL Standard" [PDF]
[http://www.altera.com/literature/wp/wp-01173-opencl.pdf](http://www.altera.com/literature/wp/wp-01173-opencl.pdf)

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ssalenik
(Article is from October 9, 2013)

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dang
Thanks! Added to title.

