
The Sail ISA specification language - bryanrasmussen
https://github.com/rems-project/sail
======
wizzwizz4
I wonder whether you could use Sail to make a compiler that figures out how to
compile things. Then you could re-target it just by giving it a description of
the new processor instead of a description of the old one.

~~~
Peter_Sewell
There's work along these lines (substantially predating Sail, but one could in
principle do much the same starting from Sail specs) by Dias and Ramsey, e.g.
the POPL 2010 and 2011 papers at
[https://www.cs.tufts.edu/~nr/](https://www.cs.tufts.edu/~nr/)

~~~
ampdepolymerase
This is how Go's assembler works.

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UncleOxidant
When I worked at a large US-Based CPU company about 10 years ago I was always
wondering why we didn't have a tool like this. Instead the ISA semantics were
described in multiple word docs. Everything was mostly* manually created from
those docs - it was fraught with the possibility of error. I did hear from
someone who had worked at the same company in the 90s that they had had a tool
akin to Sail back then that was based on an ML language (Oh, and it seems Sail
is written in OCaml!) - it seems like Nirvana had been achieved then, but then
paradise was lost by the time I was working there.

*'mostly' because there was a research group that was working on tools that would read the word docs and do some automation, though they seemed mostly still experimental... and it also seemed like a really bad way to approach the problem, but they were working with what the designers were used to - Word Docs.

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imglorp
Curiously, not the first with this name in the hardware description space.
SAIL (all caps), the Stanford AI Language, was an Algol flavored beast from
the 70s. VLSI Technology (eaten by Philips) used it for internal CAD tools
like place and route, layout, etc. in the 90s. They liked it so much they had
an internal tools group maintaining it, along with very heavy use of
ClearCase.

[https://en.wikipedia.org/wiki/SAIL_(programming_language)](https://en.wikipedia.org/wiki/SAIL_\(programming_language\))

[https://en.wikipedia.org/wiki/VLSI_Technology](https://en.wikipedia.org/wiki/VLSI_Technology)

~~~
UncleOxidant
I thought I'd heard of this before. In fact when I saw "Sail" here in the
title I figured it was the one you were referring to.

------
ithkuil
Can it model an ISA like the Mill?

~~~
monocasa
Yeah, at it's core, Sail is an RTL. It shouldn't have a problem with the Mill,
but it probably isn't the most ergonomic arch for Sail.

~~~
GregarianChild
Sail is _not_ at the register-transfer level (RTL) [1].

Why? Because Sail does not offer abstractions for clocked digital circuits,
which is what characterises the RTL. The most widely used DSL for the RTL is
(System)Verilog [3]. Instead, Sail is a stand-alone DSL for the ISA (=
instruction set architecture). The purpose of the ISA level is to talk about
that a processor looks from the outside, to the programmer (most specifically
to the compiler writer). Sail is a minimal programming language with a single
purpose: writing ISA specifications, which means writing an interpreter for
assembly language. Technically, Sail is a simple imperative language with
first-order functions. What makes Sail suitable for specifying ISAs is its
typing system. Sail supports types that are frequently used in ISA
interpreters, such as dependent typing for numeric types and bitvector
lengths. Sail is closely related to Arm's ASL (= architecture specification
language) [2].

Since Sail is Turing-complete, any ISA can be modelled, including Mill. For
the same reason any RTL can be modelled, for example by coding up an
interpreter for an RTL language like Verilog, but that would be mighty
inconvenient.

[1] [https://en.wikipedia.org/wiki/Register-
transfer_level](https://en.wikipedia.org/wiki/Register-transfer_level)

[2] [https://alastairreid.github.io/ARM-v8a-xml-
release/](https://alastairreid.github.io/ARM-v8a-xml-release/)

[3]
[https://en.wikipedia.org/wiki/Verilog](https://en.wikipedia.org/wiki/Verilog)

~~~
monocasa
There are RTLs that aren't HDLs.

For instance one of GCCs intermediate representations really reminds me of
Sail.
[https://gcc.gnu.org/onlinedocs/gccint/RTL.html](https://gcc.gnu.org/onlinedocs/gccint/RTL.html)

~~~
GregarianChild
I see now where the confusion comes from: the abbreviation RTL is overloaded
to (1) register-transfer _level_ (as e.g. Verilog) and (2) register-transfer
_language_ (e.g. GCCs intermediate representation you cited). I think the
former use is much more widespread. I agree GCC's register-transfer _language_
is close to Sail.

