
TSMC Announces 2x Reticle CoWoS for Next-Gen 5nm HPC Applications - rbanffy
https://fuse.wikichip.org/news/3377/tsmc-announces-2x-reticle-cowos-for-next-gen-5nm-hpc-applications/
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SECProto
Without reading through the links given in the article for some terminology,
this read like the turboencabulator [1].

[1]
[https://www.youtube.com/watch?v=MXW0bx_Ooq4](https://www.youtube.com/watch?v=MXW0bx_Ooq4)

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baybal2
Very few mortals will ever see anything of use from it.

Most of that advancement will go to XXL sized chips for companies with too
much money.

Its a big irony that reticle sizes became a competition point after so many
years of them getting smaller.

Those interposers are dud pieces of silicon with just metal on them, and they
can be easily done by decades old equipment with 200-300nm process. The
problem is that even 2 decades old equipment don't use 1:1 masks anymore, so
they are also limited by reticle sizes.

For all practical use cases, Intel's EMIB, and better organic interposers
still have much more appeal

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deepaksurti
>> Those interposers are dud pieces of silicon with just metal on them, and
they can be easily done

Worse is better in HW as well? [1]

[1]
[https://www.dreamsongs.com/WorseIsBetter.html](https://www.dreamsongs.com/WorseIsBetter.html)

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mechagodzilla
The primary advantage of something like this over doing multiple die on a
normal organic package is the increased bump density, allowing for more I/O,
but it doesn't really help you with power density at all.

It's not that hard to be power-limited at well below even single-reticle
sizes, though, in which case this doesn't really help at all. I could see AMD
moving to something like this for integrating HBM in a future
epyc/threadripper part, where they might want to add a lot of not-
particularly-power-hungry silicon.

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mensetmanusman
What is 2x Reticle CoWoS? Is this something like double patterning?

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baybal2
They can get you an interposer double the old size

