

A look at the 100-core Tilera Gx - ojbyrne
http://www.semiaccurate.com/2009/10/29/look-100-core-tilera-gx/

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ComputerGuru
_That_ is incredible. Coming at this as a computer engineer, I'm astounded by
the theoretically capabilities of this chip and the opportunities it opens.

With any true massively multi-core solution (greater than, shall we say, 16
cores), it's no longer efficient to get more "bang for the buck" by simply
threading or running multiple processes.

Tilera is forcing the developer to truly begin architecturing the software
stack at the hardware level. You have a complex "hive" of processing units
specifically designed to carry out particular highly-complex tasks in addition
to a huge array of "general purpose" (and I use that term lightly) cores that
can be configured to do pretty much whatever you need them to.

What's brilliant here is the on-core "packages" and what they do. This Tilera
really is amazing in that everything is there, and it doesn't _look_ like
they're compromising on performance in order to get the kitchen sink in there
too.

With the Gx, you can basically string together the available specific-purpose
processing units with blocks of the general-purpose processing units - each
block configured to run a particular task - and sort of chain the commands
through. Of course it does require writing special software, but developing
for such hardware seems to be quite enjoyable! All it would require to become
downright mainstream would be for Tilera to ship with a decent compiler/API
that lets developers easily choose what the general-purpose processing units
will be doing and string together the blocks in an easy and logical way, and I
think they may have a real winner on their hands.

One sentence summary: imagine the Tilera Gx as a hardware implementation of
just about any software solution of your choice. An on-die webserver. A
single-chip RDBMS. Whatever your wildest dreams desire...

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Tamerlin
One thing that I found particularly interesting is the way that it partitions
groups of processors per application. It reminds me of the way that IBM's
Scalable Power 2 system worked.

This Tilera chip looks remarkably similar, just a LOT smaller, and less FP
oriented; although I suspect that in computational applications, the
contemporary GPU solutions, including Larrabee, will probably blow it away, it
looks like something that has a lot of potential in I/O bound applications
like web servers and DBMS's, as others have pointed out.

If they can get enough developer interest, they could have a winner on their
hands. I could see this sort of thing being very popular in web server farms,
as well as in data centers.

