
Global Foundries discloses 7nm process detail - rbanffy
https://www.semiwiki.com/forum/content/6879-exclusive-globalfoundries-discloses-7nm-process-detail.html?utm_content=buffere2e76&utm_medium=social&utm_source=twitter.com&utm_campaign=buffer
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Animats
Yet another fab pushing deep ultraviolet lithography as far as it will go for
7nm, rather than going to "extreme ultraviolet". "Extreme ultraviolet" is
really soft X-rays. The "light source" is either a synchrotron, or an
incredible kludge where droplets of tin are vaporized by lasers. They also
produce totally incoherent light, while the ordinary processes use lasers
producing coherent light, which focuses better.

Deep ultraviolet light source: [1] Little box.

Extreme ultraviolet light source: [2] Two floors of equipment.

Nobody really wants to go to EUV with the existing sources. The industry hopes
for an EUV source that isn't insanely expensive, incoherent, dim, and an
operational headache. But there's nothing better coming along in the near
term. Intel and Samsung have chosen to build EUV fabs, to be ready in 2019,
maybe. Everybody else is trying hard not to.

[1] [http://www.oxxius.com/LUV-series-266nm-280nm-CW-
laser](http://www.oxxius.com/LUV-series-266nm-280nm-CW-laser) [2]
[http://www.anandtech.com/show/10097/euv-lithography-makes-
go...](http://www.anandtech.com/show/10097/euv-lithography-makes-good-
progress-still-not-ready-for-prime-time)

~~~
13of40
I know nothing about this area, so this is kind of an ELI5 question, but: If
the wavelength of the light defines the _lower_ limit of detail size, why
can't they switch to actual x-rays, which we already seem to be really good at
producing?

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Animats
If you go too far into the X-ray range, the high-energy X-ray photons
penetrate the masks.

~~~
sbierwagen
One fun fact about EUV lithography that I learned recently: the masks and
optics all work by reflection, since EUV photons aren't very "optical"\-- you
either have a thin film that EUV ghosts right through, or a thick film that
stops it. Changing the _type_ of atom doesn't much matter, there's not really
anything akin to a pigment for energetic photons that's _also_ thin enough to
be used for nanometre lithography.

But EUV doesn't like to reflect much, either, so the mirrors are made of
stacks of metal films, which absorb a lot of the light and need active
cooling. So that's the reason EUV sources have to be so much brighter than LUV
sources: the optics eat most of the light getting it to the wafer.

EDIT: elaborating on UV optics.

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sytse
The optics are reflective because almost everything absorbs EUV.

~~~
sbierwagen
Or rather, stuff either absorbs EUV or doesn't absorb it. I edited the parent
comment to elaborate.

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bit_logic
There's a perfect storm coming for Intel. For years they were able to sit on
fat server margins because of superior fab process and CPU architecture. Now
GF/Samsung/TSMC is competitive in fab technology and AMD has Zen. The days of
high server margins are coming to an end.

~~~
kowdermeister
And they probably know this. However if those margins were there, they can now
invest in another technology their competitors can't or won't.

~~~
simcop2387
They've been trying with the low power server market (better $/W ratios) but I
don't think I've seen much fanfare about their offerings. It's still largely
been in ARM's court for that still, though it's still a niche space
comparatively.

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visarga
This will help everything equally, but there are much more gains to be made by
moving compute closer to memory and benefiting from increased bandwidth.
That's the technology I am expecting most gains to come from.

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microcolonel
By moving closer you don't gain bandwidth, you reduce latency.

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dom0
... and not by that much ...

... which is why projects targeting this are actually about scheduling tasks
across nodes, not moving processing actually closer to the memory in the
"let's put the CPU in the memory" sense.

~~~
microcolonel
Well, for many types of compute, transaction latency is everything. Every time
you cut the difference in half, you cut the latency in half and get twice as
many dependent responses. Shrinking the process produces huge improvements.

HBM exists for a good reason. You wouldn't stack dies (and hence reduce
available thermal dissipation) if it didn't make a big difference.

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dom0
It's in the name - HBM increases bandwidth. It does reduce latency a bit
(since the electrical path is shorter), but the bigger and more fundamental
latencies (row and columns) have not changed in many many years and are
unlikely to. (It'd be possible to make them lower by proportionally higher
power use and lower density, a trade-off which no one seems to be willing to
make).

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bitL
How is GF's 7nm process in comparison to Intel's 10nm process? Is Intel still
much denser like with 14nm vs the rest of "14nm"?

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awalton
Take a look at the table in the article; most everyone who is calling their
next process "7nm" is roughly on par with Intel's _10nm_ process that they
just booted up to mass production.

The nm wars are worse than the MHz wars because chip foundries are so
reluctant to publish process details, but suffice it to say that Intel hasn't
given up as much ground as companies like GF and Samsung would rather you
believe.

~~~
indolering
Ars has a nice review[0] of the process improvements that Intel has invested
in.

0: [https://arstechnica.com/information-
technology/2017/03/intel...](https://arstechnica.com/information-
technology/2017/03/intel-is-keeping-moores-law-alive-by-making-bigger-
improvements-less-often/)

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15charlimit
Always relevant for informational purposes when chip manufacturing is
discussed:

[https://www.youtube.com/watch?v=NGFhc8R_uO4](https://www.youtube.com/watch?v=NGFhc8R_uO4)

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internalfx
So now a transistor is only like ~35 atoms across!

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thechao
No.

The feature size is 7nm. That's like saying the tightest radius in your CNC
mill's tooling is 3mm. The stuff you make is far larger. Just look at the SRAM
area: it's .0269 square _microns_. And SRAMs are tiny compared to "gate" RAMs,
like you'd see in a book.

~~~
joezydeco
The first line in that slide still blows me away.

 _17 million gates per square millimeter_.

~~~
thechao
Yeah. I'm gonna attempt a Fermi analysis to try give an idea of how much room
is still "down there". 1 sq um is 100,000,000 sq angstroms. The unit cell of
crystalline SI is probably around 50 sq A. That gives about 2,000,000 unit
cells per sq micron. My guess would be about 5,000,000 "surface" atoms. The
SRAM is .025 of that---perhaps 120000 atoms. SRAMs are cubes, so about
40,000,000 atoms cubically. Assume an SRAM is about the size of 8 transistors
(that's a big SRAM): that's about 5,000,000 atoms per transistor. I'm going to
fudge it down to 500,000 atoms, to be conservative.

The smallest logic I've heard of is a transistor using 7 atoms _in toto_. That
is a factor of 70,000x, or about 16 generations.

Now, how we'll get there, I don't know. Also, I think the generation gap will
probably widen to 5, or more, years. So... 75 to 100 years of "room"?

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xenadu02
My understanding is that the active gate region is far smaller already so
there is less room to scale than you might think.

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thechao
The active region is smaller, but this is an argument about total bulk. IBM
has shown functioning transistors with only a handful of atoms, already.

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xenadu02
Yes, but that's the limit. Quantum effects mean we'll probably never see a
single-atom transistor. Even if we did that's only a few more scalings. The
rest of the features won't shrink as much anyway.

We can see the end of the road. AFAIK no one has any clue how to even start
thinking about 2nm or beyond. No one is even certain we will hit 5nm.

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Lind5
[https://semiengineering.com/inside-fd-soi-
scaling/](https://semiengineering.com/inside-fd-soi-scaling/)

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Symmetry
I wish we had a comparison of drive currents but I'm sure that information
isn't publicly available yet.

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wiremine
I don't follow foundry details closely... what are the practical ramifications
for moving to 7nm, and how small can they get before physics gets in the way?

~~~
snuxoll
Physics are already getting in the way, that's why we have FinFET, tri-gates,
and likely GAAFET (Gate All Around) in the near future. All of these
technologies in fab processes are already in high use to combat quantum
tunneling and current leakage.

