
A New Golden Age for Computer Architecture - wheresvic1
https://cacm.acm.org/magazines/2019/2/234352-a-new-golden-age-for-computer-architecture/fulltext
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gbrown_
Previous discussion
[https://news.ycombinator.com/item?id=19023734](https://news.ycombinator.com/item?id=19023734)

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bem94
There is _so_ much to unpack in this article. I pick this claim: That RISC-V
is a simple(r) architecture and therefore meaningfully easier to verify[0].

The base RISC-V ISA is indeed very small. However, to compete with
ARM/MIPS/x86 usefully as an application core, one must include many standard
extensions. All of which add comparable complexity to the ARM/MIPS feature
which they ape. It feels wrong to assert then without some serious
qualification that RISC-V is simpler or easier to verify. A RISC-V core is no
more or less complex to verify than a comparably featured ARM/MIPS core.

That said, and open ISA like RISC-V can really lead the way in terms of shared
verification IP. _That_ is the benefit to an open ISA, not it's simplicity,
but the fact that it becomes worthwhile for people to share their verification
infrastructure. Unfortunately, I haven't seen much of this yet. riscv-formal
is amazing, and the riscv-compliance suites are getting better, but proper
constrained random stimulus generation and coverage collecton? Not yet, at
least, not out there in the open source world. I really wish that Western
Digital had included their verification infrastructure when they open sourced
Swerv [1].

Really enjoyed the article otherwise!

0 - A reasonable person might disagree this claim is being so explicitly made,
but that's what I took from it.

1 -
[https://github.com/westerndigitalcorporation/swerv_eh1](https://github.com/westerndigitalcorporation/swerv_eh1)

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tlb
Here are 3 errata I picked from the Xeon E5 series [0]:

> REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page
> Boundaries with Inconsistent Memory Types may use an Incorrect Data Size or
> Lead to Memory-Ordering Violations

> Changing the Memory Type for an In-Use Page Translation May Lead to Memory-
> Ordering Violations

> When a Link is Degraded on a Port due to PCIe* Signaling Issues, Correctable
> Receiver Errors May be Reported on The Neighboring Port

The 1st is related to ISA complexity, the 2nd and 3rd aren't.

Based on a quick scan, I think 24 of the first 100 errata are ISA-complexity
related. So "meaningfully easier" might be justified, but many problems come
from peripherals or the MMU rather than the instruction decoder.

[0]
[https://www.intel.com/content/dam/www/public/us/en/documents...](https://www.intel.com/content/dam/www/public/us/en/documents/specification-
updates/xeon-e5-family-spec-update.pdf)

~~~
bem94
x86 is undoubtedly a very complex beast, so ARM/MIPS are fair _er_
comparisons. Never mind the fact that a Xeon CPU is boggling complex on top of
that. I think you are right about how problems are more likely to come from
interractions with peripherals, especially the MMU. Most of these things are
not architecturally specified, so it's an orthogonal problem to ISA
complexity.

Bugs in instruction decoders are something of a false flag in my opinion. They
are no less important than other bugs, but they are much easier to find as
well, because the problem space is more manageable. A little more complexity
in an instruction decoder is not, in my opinion, enough justification to
exclude otherwise useful instructions or functionality.

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gumby
> The limit of TDP led directly to the era of "dark silicon," whereby
> processors would slow on the clock rate and turn off idle cores to prevent
> overheating.

We used to do this in the 1990s with PHS cell phones in Japan: you certainly
didn't need to listen to the microphone until a call was actually connected,
and even then the caller might listen and not talk, so after connection you'd
listen to the microphone but still not start up the voice compression chips
until the noise got above a threshold (so a bit of the moshi moshi would get
cut off -- no big deal).

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slurpeedog
Golden age has been over long ago.

