
FPGA 101 Lessons/Labs - homarp
https://github.com/litex-hub/fpga_101
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panpanna
This seems to be using some sort of homegrown python system (migen) for fpga
development.

If you really want to learn fpga/asic development do yourself a favor and
learn a real hardware description language such as verilog or vhdl. It is
really not that hard. If you have some minimal knowledge in digital systems
you will be up and running in a few hours.

And with a good teacher it will be really fun:

[https://www.fpga4fun.com/](https://www.fpga4fun.com/)

~~~
tails4e
I Fully agree. Learning Verilog, or ideally SystemVerilog, to a basic level is
important to have as a foundation for when you may need to build more advanced
designs. I'm in favour of more high level languages being developed for HW
generation, but I've yet to see a true replacement language for the main HDLs.
For a counter and blinking led example, Verilog is very easy to
read/understand for a beginner.

~~~
Traster
I would always say that the important thing is the paradigm you need to adopt
when writing RTL. Whether it's VHDL or systemverilog, the differences are
details. It's like programming C# vs Java, they have the same core concepts.
But if you hand a C# Developer VHDL/SystemVerilog/Prolog they're not going to
have a good time.

~~~
tails4e
That's a good point,the dataflow can be confusing to understand at first,
especially when used to a purely procedural paradigm. In a way its similar to
the differences between functional and imperative programming, and you first
need the right mindset/basis for how it works before you can be productive.
Once you understand the concurrent nature being described by HDLs, it begins
to make sense - I always elaborate my HDL (actually usually other folks code)
so I can see the dataflow that's being inferred graphically and it's very
useful

