
RISC-V Vector Extension 0.7 by Krste Asanovic [video] - childintime
https://www.youtube.com/watch?v=F66F1nT1T8o
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childintime
Despite using only 1.5 major opcodes "this is by far the largest RISC-V
extension". The end result may be a "design by committee", a relatively
complex beast, though there is a simpler subset for small micro-controllers.
Is there any truth in this?

~~~
_chris_
Designing a good vector ISA is _really_ hard.

The problem is "vector" is an entire category of architecture-style and
machine designs; it's not a problem domain. So some people want vector for
their very narrow domain (ML? IOT?), and other people want vector for some
other narrow domain (HPC? media?), and other people want it for "general-
purpose" compute (whatever that means).

Hard questions: what data types do you support? Do you support mixed-types? Do
you support expanding operations (64x64=128?)? Do you support reductions? How
do you support conditional/branching execution? How do you support
interrupts/exceptions? Do you support register file reconfigurations? How do
you do function calls? Context switches?

Looking at the evolution of Intel's SIMD ISAs, they started from small 64-bit
integer-only multimedia stuff (MMX), and are now at AVX's 512b masked
execution with scatter/gatters and exponentials and reciprocals... there's a
lot of complexity you can add to a vector ISA. :0

~~~
childintime
RISC-V wants to go beyond AVX, on several dimensions (parameterized hardware,
generic code base, low-end to high-end hardware, symmetry with scalar RISC-V
instructions). So if this proposal succeeds in delivering an outline of the
final extension (the concepts to iterate and improve on), that would be a
milestone worth celebrating (not doubt as I did ;).

