
MIST – FPGA-Based Amiga and Atari ST - doener
http://harbaum.org/till/mist/index.shtml
======
brudgers
The actual computer is [purportedly] available at the linked website:
[http://lotharek.pl/product.php?pid=96](http://lotharek.pl/product.php?pid=96)

------
bane
This supports more than just the Amiga and ST. Better page here
[http://lotharek.pl/product.php?pid=96](http://lotharek.pl/product.php?pid=96)

------
armitron
It's (kind of) unacceptable that this has VGA out instead of HDMI. What were
they thinking?

~~~
duskwuff
VGA is much easier to generate on an FPGA. Also, the project is a few years
old.

~~~
nitrogen
What makes that so? Do most FPGAs lack serial outputs that could generate
HDMI/DVI signals? It seems to me that VGA would be harder since you need a
DAC.

~~~
wannabeehwdev
Common FPGAs are limited to sup-GHz speeds. Common DACs (afaik) are parallel,
letting them be driven at lower clock speeds than equivalent serial digital
devices.

1920 x 1080 x 24bpp x (10/8 due to TMDS 8b/10b encoding) 60hz ~= 3.5 gigabits
a second, / 3 (3 data lines in DVI/HDMI) = just over a gigabit per data line,
plus surely some overhead that I don't know about. I'm not an EE but it sounds
like it would be hard to generate a >1GHz signal on a <1GHz FPGA.

Whereas with an analog signal driven by 3 8-bit DACs, you're dealing just
dealing with 1920 x 1080 x (VGA overhead) * 60hz = a 120~ megahertz signal
that can easily be generated by any FPGA. (the 24bpp is irrelevant because it
is being transferred in parallel)

~~~
gima
What (I think) I know of the subject:

For a resolution of "1920 x 1080 @ 60Hz" the FPGA needs to run only at the
pixel clock's frequency, which is "only" 124.416 MHz (1920x1080x60 / (10^6)).
Then on every pixel clock cycle, the FPGA needs to present each bit of what
makes-up-a-pixel on it's output pins. In case of 24bpp, that would require 24
dedicated output pins. In addition, a dedicated DVI transmitter chip would be
required to serialize and encode that 24 wide bus to those DVI-compliant three
differential signal lines in addition to doing the 8b/10b encoding. Roughly.

Or the FPGA could have a high-speed serializer built-it which could replace
the dedicated chip.

~sigh~ I wish I knew enought about electronics to play around designing such a
serializer, it tickles my fancy :)

~~~
rjsw
The Parallella board has an HDMI transmitter connected to the FPGA, it uses
the same generation of FPGA as the Mega65 that is described elsewhere in the
thread.

