
  Tilera launches new generation of multicore embedded chips for communications - prakash
http://venturebeat.com/2008/09/21/tilera-launches-new-generation-of-multicore-embedded-chips-for-communications/
======
soundsop
Some more info at Ars Technica:
[http://arstechnica.com/articles/paedia/cpu/MIT-startup-
raise...](http://arstechnica.com/articles/paedia/cpu/MIT-startup-raises-
multicore-bar-with-new-64-core-CPU.ars)

and a paper published at the ISSCC conference:
[http://www.scribd.com/doc/6151332/TILE64-Processor-A-64Core-...](http://www.scribd.com/doc/6151332/TILE64-Processor-A-64Core-
SoC-with-Mesh-Interconnect)

------
13ren
_Tilera is targeting the chips at high-end networking equipment that would
otherwise use digital signal processing chips from Texas Instruments._

DSP is a special case, where scaling is easier. Anyone have more details on
how general their approach is?

 _EDIT_ <http://www.tilera.com/technology/technology.php>

They address the multi-core hardware bus problem (iMesh/Tile packet
switching), but not the multi-core _software_ problem. Previously on HN:
<http://news.ycombinator.com/item?id=295530>
<http://news.ycombinator.com/item?id=295152>

