
Latency numbers every programmer should know - sajid
http://www.eecs.berkeley.edu/~rcs/research/interactive_latency.html
======
jasonzemos
Two things are striking if one right-arrows through each year from the
beginning: the wall for local circuit latency hit around 2005/2006, and the
limitations the speed of light puts on global latency _from the beginning_.
The harsh takeaway I get from these presentations is that the speed of light
is just not as stellar as we'd like, and that's a challenge.

~~~
marcosdumay
In normal circuit units, the speed of light is 30cm/ns. A very mundane number.

------
iammyIP
Anyone knows why the L caches could not simply be as large as our current main
memory, let's say 16gb L2 cache and 4gb L1 chache directly on the die - would
that be possible if price would not matter? What kind of problem is this?

~~~
nickpsecurity
Caches are usually built with static RAM (SRAM) while memories are DRAM.
Here's a simple explanation of the difference:

[http://computer.howstuffworks.com/question452.htm](http://computer.howstuffworks.com/question452.htm)

Basically, SRAM costs more to make. The memory fabs also use less expensive
tech with just a few layers vs the 10 or whatever absurd number CPU's and
their fabs require. There's a company that built a CPU for memory fabs
specifically to leverage what they said was a 100x cost difference.

There's been some use, like in IBM's high-end POWER, of slower memories for L3
or whatever that are WAY larger but still on chip. I'm not sure how that
panned out in terms of results.

~~~
ddayutah
You can also run out of space on the die. Silicon die sizes are limited by
physics and economic considerations. You can't put too many power hungry
transistors next to each other and still be able to cool the die. If problems
are random over the area, then if you increase the die size, there are more
errors per die, which drops your yield. Why not make the DRAM out of SRAM? I
think the answer is that the latency to access the DIMMs won't go down (it's
dominated by the distance from the processor to the modules). Ulrich Drepper
has a good paper on the topic:
[https://www.akkadia.org/drepper/cpumemory.pdf](https://www.akkadia.org/drepper/cpumemory.pdf)
It's a few years old, so the discussions of North/Southbridges is obsolete,
but the discussion of RAM tech (p. 5) is fundamental, and hasn't changed too
much (to my knowledge).

~~~
nickpsecurity
I overlooked size/errors. Good points. I now remember reading about such
issues under banner of Design for Manufacturing where they had those
considerations in the design flow. Far as paper, I'll look at it later. :)

