

Update on STM - wisesage5001
http://morepypy.blogspot.com/2013/08/update-on-stm.html

======
nn4
Obligatory anti STM hype links:

[http://queue.acm.org/detail.cfm?id=1454466](http://queue.acm.org/detail.cfm?id=1454466)
[http://webcache.googleusercontent.com/search?q=cache:HhZcU_j...](http://webcache.googleusercontent.com/search?q=cache:HhZcU_jucksJ:www.bluebytesoftware.com/blog/2010/01/03/ABriefRetrospectiveOnTransactionalMemory.aspx+&cd=1&hl=en&ct=clnk&gl=us)

Pretty much all the generalized (not functional) memory TM schemes with
adequate performance rely on hardware acceleration. If your design doesn't
support that your design is wrong.

------
kazagistar
Is there any plans to work hardware transactional memory into the mix?

~~~
kingkilr
Current HTM implementations limit the size of a transaction to the L1 cache,
so for the time being, no.

~~~
4buser
Even new Intel Haswell's STM?

~~~
sanxiyn
Yes, Intel TSX too has a limited transaction size.

