

The future of computers: 3D chip stacking - SkippyZA
http://www.extremetech.com/computing/119843-the-future-of-computers-3d-chip-stacking

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tcas
Xilinx's Vertex 7 FPGA uses a stacked design for the interconnects. The FPGA
logic is all 28nm, but sitting under it is a completely passive 65nm
interconnect layer.

[http://www.xilinx.com/products/technology/stacked-silicon-
in...](http://www.xilinx.com/products/technology/stacked-silicon-
interconnect/index.htm)

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roc
> _"chip stacking obviously works in synergy with Intel’s 3D FinFETs — though
> curiously there is no sign of TSV on Intel’s roadmap"_

Wouldn't chip stacking exacerbate heat dissipation issues? It seems to me that
desktop chips would stand to gain far less from this approach, so why should
it be surprising that Intel isn't rushing into it?

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IdahoEv
I wonder if you could etch channels for liquid coolant directly into every 3rd
layer or so...

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wmf
[http://www.eetimes.com/electronics-news/4077160/IBM-GIT-
demo...](http://www.eetimes.com/electronics-news/4077160/IBM-GIT-demo-3D-die-
with-microchannel-cooling)

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ksec
We know this for a long time. Few years down the road in sub 10nm, we will
reach the era where we cant shrink transistor endlessly. The problem with chip
stacking on die is how to get rid of the heat passing through each layer.

Stacking in itself has proven to be feasible by the Memory Cube. Where Heat
isn't much of a concern.

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Symmetry
I expect that what we'll see is a top layers of general purpose processing on
top next to the heat sinks, then lower power layers further down, like maybe a
layer of L3 cache then a stack of main memory. Probably also a lot of dark
silicon which is only lit up for special tasks, like media encoding or
encryption.

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ot
Wasn't that one of the innovations of Apple's A4 chip? Stacking the RAM chips
on top of the CPU core inside the same package?

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abuzzooz
The A4 does use this technology, but Apple certainly did not invent it (though
I wouldn't be surprised if they claimed so). It has been used in cell phones
for years, and only recently others are starting to adopt it, and extend it to
place two chips side by side on a Si substrate within a single package. The
reasons are purely economical. In the past, much benefit can be had just by
shrinking the transistor size. At the current feature sizes, though, physics
is not helping anymore and there is very little benefit in terms of raw
transistor and wire speeds, and power. So chip makers need to find more ways
to extend Moore's law a few more years. FinFETs and stacked chips are just
such ways.

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abuzzooz
I'm curious why my comment was downvoted? Just for future reference.

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m_eiman
Probably the rather off-topic _though I wouldn't be surprised if they claimed
so_ part.

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abuzzooz
Ah. Makes sense. Thanks.

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KeyBoardG
Hasn't chip stacking been the future of computers for 10 years? Especially of
SoC solutions.

