
Cache coherency primer (2014) - swah
https://fgiesen.wordpress.com/2014/07/07/cache-coherency/
======
bluetomcat
The moral of the story for software developers is to be aware of false sharing
and cache line bouncing when writing multithreaded code.

Seemingly innocent code like this will most likely cause completely
unnecessary inter-core traffic (assuming that the compiler has laid out a and
b adjacently, and they both fall within the boundaries of a single cache
line):

    
    
        unsigned a, b;
    
        void thread_a(void) {
            for (;;) a++;
        }
    
        void thread_b(void) {
            for (;;) b++;
        }

------
bluecalm
I don't know almost anything about hardware but that was very well written and
easy to follow. A pleasure to read.

~~~
camelspade
If you are more interested, Appendix C of "Is Parallel Programming Hard, And,
If So, What Can You Do About It?" by Paul McKenney
([http://kernel.org/pub/linux/kernel/people/paulmck/perfbook/p...](http://kernel.org/pub/linux/kernel/people/paulmck/perfbook/perfbook.html))
provides a very detailed description as well. It really helped improve my
understanding of how memory barriers and atomics work

~~~
stplsd
This is also a very good read:
[https://lagunita.stanford.edu/c4x/Engineering/CS316/asset/A_...](https://lagunita.stanford.edu/c4x/Engineering/CS316/asset/A_Primer_on_Memory_Consistency_and_Coherence.pdf)

~~~
camelspade
Thanks! :) Gonna add this to the list of books I need to read.

