
TSMC Details 5 nm - baybal2
https://fuse.wikichip.org/news/3398/tsmc-details-5-nm/
======
Symmetry
The thing that really jumped out at me was making the channel partially out of
germanium. Velocity saturation has been a limiting factor in our tiny modern
transistors for a while, playing its own minor part in the breakdown of
Dennard scaling. The article didn't say if the increase applied equally to
both electron mobility and hole mobility. Germanium tends to be better for
both but I my materials science background isn't good enough for me to guess
what it'll be in a Silicon/Germanium lattice. Temperature dependence is also
an equally interesting question since Germanium tends to deal with high
temperatures a bit better.

This won't help with leakage issues or the increasing importance of wire as
opposed to transistor capacitance. But it does look like a nice little win.

Speaking of wires, is TSMC still using straight copper or are they thinking of
incorporating cobalt? Or did Intel's experience with that scare them off?

EDIT: And speaking of cobalt again, I really hope they aren't being too
ambitious with this and that being too innovative doesn't bit them the way it
did with Intel at 10nm. Though the rumor mill isn't sure if it was the cobalt
wires or the Contact Over Active Gate (COAG) that was their main problem.

~~~
baybal2
> The article didn't say if the increase applied equally to both electron
> mobility and hole mobility.

Electron mobility is not high in silicon, but it has never been a "blocker"
before. In fact, the utilisation of strained silicon has gone down from 40nm
in later nodes.

Silicon however has truly terrible hole mobility, and the wider industry has
just started to realise that they have lost many years to fruitless pursuit of
high electron mobility, when the real blocker has always been a pFET.

It was very prudent of TSMC to quietly continue pFET RnD, despite industry's
fixation of HEMTs and 3-5 devices.

p.s. 5N is a COAG process from what they have just said.

~~~
brennanpeterson
The amount of Ge and thus strain has increased every node. All to make hole
mobility better.

No one in industry was confused about HEMTs, and the needs of pfets were well
known.

~~~
baybal2
> The amount of Ge and thus strain has increased every node.

Not really from what I know. The compressive strained channel was dropped out
for some FinFET designs, and I think tensile strained too in some because it
was exploding litho layer count. Can you tell your source?

Compare the amount of money spent on truly moonshot material science like
making 3-5 logic, and the amount of money spent on continuous improvement of
pfet performance for mainstream applications.

~~~
brennanpeterson
From device cross sections and working at both IDMs and suppliers. And reading
and visiting IEDM for a decade. You can keepmup with ost on semiwiki: but
really, just work under the assumption that people in the field are not stupid
and can do math.

Tensile strains has no litho impact, and counting layers in use was a job I
had.

Who spent on 3-5? It got press coverage, but never was part of much logic
research. It was a focus for power, laser, and led work.

Tsmc, Intel, applied, asm, and others spent vastly more on r&d than any
government or academic work, and it isn't published.

~~~
baybal2
I'll give you that. I haven't been involved with device and process
development since around 2009, when I lost hope getting into process
engineering.

So, were strained channels used with FinFETs on anything mainstream? I heard
the news of number of foundries dropping straining at around the time of first
finfets.

------
npunt
171.3 million transistors per mm^2 is mind boggling. Were Apple's A14 to have
the same area as their A13 (98.48mm^2) and maintain that density throughout,
you're looking at ~16+ billion transistors. Some comparisons:

\- Apple A13: 8.5 billion

\- Apple A12X: 10 billion (iPad Pro)

\- Nvidia Titan RTX: 18.6 billion

I wonder what kind of use cases are unlocked with 16 billion transistors in
your pocket. This node might be the one that gets us to AR.

~~~
jp555
There is no Moore's Law in optics & batteries.

The AR everyone imagines is much further away than most realize.

~~~
npunt
Agree, the popular idea of AR going around - wide FOV, fancy graphics, good
occlusion of incoming light, tiny footprint - is unlikely for a long time due
to optics. I think it’s foolish to try to execute that vision now, and why
I’ve always thought Magic Leap’s 'do it all' approach was completely wrong
(and demonstrated they didn't really have a clear vision for what would make
AR mainstream). The only way to achieve that vision for AR is to increment
toward it over a long time.

I see v1 as a simple narrow FOV heads up display in glasses frame with very
focused use case around place based notifications and heads up information. No
input at all, except Siri. Display only turns on when necessary. iPhone is
used for input and config, much like Watch was initially.

Even getting to this v1 is going to be a huge challenge in such a small form
factor, but a chip with this density will help with power budget. This node
consumes 30% less power and fits in an even smaller space.

~~~
SirHound
Siri-only input would make it a joke device. A device like that should be
multi-input. Voice, mouse, keyboard, your watch, phone, ipad etc.

~~~
npunt
What I meant was input via the device itself. You can't expect people to press
buttons on their glasses to get things done, that'd be a bad experience. The
only other hands-free input method is gaze tracking, which would be great, but
it may not make it into a v1 product.

Obviously there's input possibilities from other devices, and I mentioned
iPhone. Unlikely mouse and keyboard input for a long time - AR's unique
offering is freedom of movement, not being tethered to a desk.

Again, a v1 really has to be a minimal product that is first and foremost a
heads-up display for a narrow set of use cases. Else it'll be too bulky or
awkward - just look at the rest of the AR devices out there.

------
georgeburdell
And Intel is now headed by someone with a 100% finance/business background.
Intel is nipping at the heels of Boeing. Tens of billions of dollars in
dividends and stock buybacks announced that should be going to saving their
(and by proxy, the U.S.'s) manufacturing capability.

~~~
gameswithgo
they have jim keller though

~~~
sq_
True, but it seems to me that he's been most successful at companies that are
willing to place big bets on his team and put a lot of institutional weight
behind him. His work at Apple, AMD, and Tesla all seem to point towards that
conclusion. One wonders if an Intel that's less focused on hardware innovation
will see the same effects.

------
danaos
The title is kind of misleading.

> TSMC made every effort to avoid detailing the actual properties of that
> channel (every related question was met with the tautology: “those who know,
> know”). [...] We believe TSMC is employing a SiGe channel for the pMOS
> devices

~~~
baybal2
There is only one known high mobility material availing to easy integration
with silicon MOS process

None of InP, SiC, GaN, GaAs or other 3-5 materials been ever integrated with
silicon in a fab setting for IC production.

And only one material out there makes sense to use specifically for pMOS
production: high hole mobility is much rarer trait than high electron
mobility.

~~~
madengr
Isn’t MACOMs process GaN on Si, which is cheaper, but lousy thermal
performance compared to GaN on SiC. I thought they were touting GaN
integration with CMOS?

~~~
baybal2
GaN on Si is a thing from a completely different ballpark.

Here we talk about material integration per-device basis, not entire wafer
surface.

------
exikyut
> Our current estimates remain at 48 nm poly pitch and 30 nm metal pitch.
> Those dimensions yield an estimated device density of 171.3 MTr/mm².

I just sized up 1mm between my fingers.

Um. _WOW._ Really. Wow.

~~~
raverbashing
For reference a 64-bit Pentium 4 core was (drum roll) 125Million transistors.
And it was 100x bigger (112mm^2)

~~~
exikyut
Wow at that too.

To be honest, one of the things I was considering when posting the GP was the
sheer impossibility of leveling anything more precise than hand-wavy, drunk
opinions about the end-to-end security state of _that much_ , well, entropy.

It's gotten almost like a bizarre version of inverted quicksand, where instead
of it being bad because you're sinking into sand, it's bad because the sand is
shrinking into nothingness from between your fingers.

The next few years are going to be VERY interesting, I think.

IIUC, OOo and branch prediction have kind of been the CPU engineering meal
ticket workaround to "solving" the memory latency problem (IIUC), and now
everyone apparently has to rethink that.

My favorite would be the "disappearance" of the A20 line though. As in, it's
there, it's doing it's thing, but everyone collectively forgot it existed, and
now everybody needs a microcode update and an SGX cert respin AGAIN.

And all this without access to specialized tooling (the kind that evolves over
a decade, regardless of knowledge), AND the fact that we're (apparently?) only
forgetting about (seemingly?) little things at this point. Haha...ha...

------
jl6
On the other hand, I keep hearing people saying than nm is increasingly just a
marketing number - and indeed, for all of Intel’s difficulties I don’t see too
many chips beating Intel in single-threaded performance.

I say this as someone who bought a Ryzen-based system last year after
significant research.

~~~
gameswithgo
the transistors are actually getting smaller, that just doesn’t lead to more
clock rate any more

~~~
navaati
But less heat, which allows you to cram more stuff in a package, which _is_ a
win !

------
jonplackett
I’m starting to (almost) feel sorry for Intel now.

~~~
jokowueu
And 3nm planned for 2022 . They are moving at an incredible pace. They will
definitely hit a wall soon at this speed

~~~
baybal2
Which is their plan, as many people believe.

They want to drive the few competitors they have out of business quickly
before that happens.

Hence them accelerating node transitions in spite of not being able to recover
as much RnD money as they can.

Only really high margin products contend for <14nm node capacity, and nothing
else.

For as long as they maintain such high pace, and wide lead over competition,
competitors get nothing, while still having to spend the same astronomical
sums on fab retooling.

~~~
api
Where are they getting the money? Are they that profitable or state sponsored?

~~~
Arnt
Profitable.

Would be very profitable, if they had the income from their advanced processes
without the R+D expense for those processes.

------
magicalhippo
I remember reading a lot about a "brick wall" when they pushed towards EUV,
how challenging it would be to reduce feature size further etc etc. But it
seems they're moving along just fine. What happened?

------
sytelus
To put it into perspective, Coronavirus would just fit in 25 transistors long
at this scale! However, to be fair, it has 30 kilobases where each base is
2.5nm X 0.3nm. So we still have some way to go...

------
crakenzak
Game, set, match. it's over for Intel. They sat on their asses for too long
and now are getting eaten by the previous underdogs.

This shift is great news for literally everyone except Intel's execs' bonus
packages.

~~~
spectramax
I don't understand callous contempful comments against Intel's manufacturing
capabilities. There are incredible people making things possible fomr both
sides in one of the most advanced manufacturing processes in the world. I've
worked inside a fab and I can tell you that the industry is much more
appreciative of each other's competitors than the outside fanboys who are
largely pissed off at the executive decisions (lawsuits , etc).

This article is about TSMC's technical achievements and your comment has not
added anything to the discussion, time and again I see this rooting for
"underdog" behavior all too the same (just flipped the sides) from 2006. I
wrote about it here:
[https://news.ycombinator.com/item?id=22515546](https://news.ycombinator.com/item?id=22515546)

If you'd like to know what goes into shriking a process node from lithography
standpoint, I implore you to watch this:
[https://www.youtube.com/watch?v=f0gMdGrVteI](https://www.youtube.com/watch?v=f0gMdGrVteI)

and be in complete utter awe... Tell me if they are "Sitting on their asses"?

~~~
Valmar
Oh, please ~ Intel fucked up their 10nm process pretty hard, and they kept
trying to fix it for years. They also had to keep pushing their roadmap back
again and again for 10nm.

This is entirely due to Intel's awful management getting in the way. Intel's
engineers might be clever, but with shitty management, that can all go to
waste.

Intel's management have been sitting on their arses, more or less, when you
consider the fact that they've really been dragging their feet in terms of
progress.

AMD has made more progress in 3 years than Intel has made in 10...

Intel simply got too comfortable with their monopoly.

~~~
TomVDB
I know that Intel has major issues with 10nm, but I don’t know exactly what
went wrong.

Can you educate me?

I’m particularly interested in how management sabotaged the ability to get
10nm to work.

