
Big Trouble at 3nm - Lind5
https://semiengineering.com/big-trouble-at-3nm/
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Xcelerate
3 nm is nuts. I used to perform molecular dynamics simulations in boxes that
were 10 nm on each side. You can count the atoms lined up within 3 nm of
space.

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Taek
The actual gate pitch of a 7nm process is 54nm, and the interconnect pitch is
40nm. Though the name is "7nm", it's far from it.

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daveguy
The way I (not EE) understand it the size of a process considers just one
dimension. So transistors can be tightly packed along that axis and less
tightly packed along the other axis of a wafer.

Have the gate pitch / interconnect in the range of 40-54nm hit a more
difficult limit than the 7nm aspect? It seems like there is significant space
for improvement in those dimensions where you could still double density.
Should process nodes be referred to as 7nm x 54nm where new generations drop
gate pitch too?

Is there something inherent to the process that fixes the other dimensions
when you have a "7nm" node for that particular metric?

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tsenkov
Where does the increase in Software expenses for IC Design stem from?
[https://semiengineering.com/wp-
content/uploads/2018/06/nano3...](https://semiengineering.com/wp-
content/uploads/2018/06/nano3.png)

~~~
abainbridge
Good question. That's a strange graph in general. I think most items have
little to do with the node choice.

From the article:

> The $1.5 billion figure involves a complex GPU at Nvidia

I think the graph shows how much it costs a company in total to design a chip
at different nodes. In general, chip vendors add more functionality with each
generation. That seems to be what the graph shows.

The article says the graph comes from International Business Strategies. Their
web page tells me to install Flash, which was enough to prevent me looking
further:

[http://www.ibs-inc.net/#!reports](http://www.ibs-inc.net/#!reports)

Also, someone should tell them that IBS stands for Irritable Bowel Syndrome.

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mamon
It seems that Intel already is in the Big Trouble at 10nm, so 3nm seems even
more unrealistic goal.

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theshadowknows
Is decreasing the spacing of gates and increasing the density of chips the
only way to squeeze more performance out of chips?

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marcosdumay
It's not just decreasing spacing.

It's decreasing wire resistance and gate capacitance. That's what makes the
most difference. It is also about making things cheaper, because your costs
are constant for a wafer, but the use is measured by gate count.

That said, things are not that simple for a long time already.

~~~
deepnotderp
Wire and contact resistance has been steadily increasing and FinFETs actually
increased gate capacitance.

~~~
marcosdumay
As I said, things have not been that simple for a time.

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deepnotderp
TL;DR: FinFETs are running out of steam without a powerful "scaling booster"*
so GAA-FETs ?, wires suck and continue to suck and development costs are going
up so let's misrepresent that and use ridiculous numbers for it.

*Debatable: [https://ieeexplore.ieee.org/document/7890390/](https://ieeexplore.ieee.org/document/7890390/)

