

DDR4 memory interface - blue2jay
http://www.edn.com/design/pc-board/4432676/DDR4-memory-interface--Solving-PCB-design-challenges

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userbinator
I think there will soon come a day when DIMMs become _wider_ and not faster -
high clock frequencies are attractive for marketing purposes but as this
article points out, are increasingly harder to design for. DIMMs have been 64
bits wide since they appeared, to coincide with the P5's bus width, but modern
processors have much wider databuses, so it'd make more sense to maintain the
same clocks but widen each module.

Starting in the 90s there was a trend of replacing parallel buses with serial
ones (USB, SATA, etc.) but I think it's slowly beginning to reverse as people
realise the difficulties of using high frequencies (e.g. multiple lanes in
PCI-E).

Incidentally the term DIMM - _dual_ inline memory module - comes from the
doubled width over the existing SIMM, which was 32 bits wide. Maybe we'll see
128-bit-wide QIMMs in the future...

~~~
dfox
Because of latency difference between RAM and on chip caches you don't gain
too much by making wider data bus to RAM, because latency is still the most
limiting factor. Modern solution is to have multiple full memory interfaces
("channels") which give you the ability to both behave as if the memory bus is
wider as well as issue completely different memory transactions given that the
accesses are suitably aligned (which is more significant performance boost).

Also the general trend of weird (i.e. PCI) and serial interfaces in 90's was
motivated by per-unit costs at the expense of required engineering. Primary
motivator for PCI's reflected wave switching and multiplexed address and data
was to limit number of pins and number of required passive components on
motherboard. Serial interfaces that came after that (SATA, PCI-E) were
motivated by the fact that routing fast parallel synchronous buses for any
significant distances is hard problem because of propagation times, which have
to be roughly equal for all bus wires, which implies that PCB material
parameters have to be known and reasonably consistent (and that means
significant per-unit additional expense in PCB manufacture and testing cost).

Currently only interface that requires careful routing and design on PC
motherboard is memory interface, which can be made short enough that
manufacturing differences are negligible. (It's funny how TI has 20 page
application note on correct routing of USB2 which includes rules as "no vias
preferably, at most one", "no stubs", "controlled impedance" and "as short as
possible" while Intel's layout recommendations for USB2 can be summarized as
"it's differential pair, discontinuities do not matter much, use sensible
routing")

[edit: formatting + missing word]

~~~
kristianp
It seems part of the answer to the latency question is to stack the ram on top
of the dram controller, as mentioned in this recent article on Intel's Knights
Corner. [http://www.anandtech.com/show/8217/intels-knights-landing-
co...](http://www.anandtech.com/show/8217/intels-knights-landing-coprocessor-
detailed)

~~~
dfox
That is more of an answer to routing and signal integrity problems of fast
parallel interfaces, e.g. bandwidth. Most of the DRAM latency is inherent in
the DRAM array itself (actually getting the data between dram array and sense
amplifiers). Almost nobody cares about additional cycle of latency introduced
by registered dimms, as it is essentially noise compared to precharge latency
of the dram itself. This comes mostly from physical limits of what can be
manufactured with reasonable power dissipation and reliability (see how "CAS
Latency" grows at comparable rate to clock rate, ie. stays mostly comparable
in wall-clock time)

------
ChuckMcM
Sad to think I remember the days when you just wired D0 to D0, D1 to D1, D2 to
D2, etc.

~~~
femto
Sad also that I've still got pristine 6116 2Kx8-bit memory chips at home, and
maintaining the delusion that one day they might be useful.

[http://web.mit.edu/6.115/www/datasheets/6116.pdf](http://web.mit.edu/6.115/www/datasheets/6116.pdf)

~~~
TorKlingberg
Old RAM can be useful, for example if you want to run Ubuntu on an 8-bit
microcontroller:

[http://dmitry.gr/index.php?r=05.Projects&proj=07.%20Linux%20...](http://dmitry.gr/index.php?r=05.Projects&proj=07.%20Linux%20on%208bit)

~~~
MrBuddyCasino
I salute you, dmitry.

In order to run Linux on an ATmega1284p, that guy:

\- bit-banged 16MB DRAM

\- bit-banged SPI Flash

\- wrote an emulator for a 32Bit ARM & MMU

Apparently it takes 4h to but Ubuntu.

