
Thoughts on Low Latency Interrupt Handling - rbanffy
https://blog.adafruit.com/2018/04/22/thoughts-on-low-latency-interrupt-handling-samd51-microchipmakes/
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SpaceNugget
The actual article is at [https://www.bigmessowires.com/2018/04/12/thoughts-
on-low-lat...](https://www.bigmessowires.com/2018/04/12/thoughts-on-low-
latency-interrupt-handling/) The current link is to some kind of aggregator at
adafruit.com

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Animats
That scope display is a classic test of interrupt latency. One of the tests
for QNX is to do that, and measure how long it takes from an interrupt until a
user-space process can turn on an output pin. The important number for an
real-time OS is not the average, but the worst case.

Some boards fail this test badly because they're doing something below the OS
level in system management board. You set outliers on the scope. Those boards
are unsuitable for real-time work.

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Gibbon1
A good trick is to set the scopes persistence to infinity and leave the thing
running over the weekend.

> system management

Friend that worked on processors said some of them will 'go away' for a ms.

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MrBuddyCasino
> The choice is also influenced by my desire for a mainstream mcu, with broad
> availability, good documentation and community support, good development
> tools, and a positive long-term outlook. This leads me to eliminate some
> options like the Parallax Propeller and Cypress PSoC.

Can anyone elaborate what kills the Cypress PSoC in that scenario? Never used
them, but the reconfigurable logic part looks interesting.

~~~
joezydeco
Yeah, I'm confused about that too. I always had a positive experience with the
PSoC, unless the author considers it a niche chip that most mainstream
embedded developers will never encounter.

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userbinator
For a second I thought the SAMD51 was an 8051-based part. Incidentally, some
of the newish 8051 MCUs (SiLabs makes some good ones) have very low interrupt
latencies too (<10 cycles) when running at 100MHz.

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dmitrygr
OP complains about flash wait states but doesn't know you can move your
handler code to ram to avoid them?

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felixgallo
‘If the flash wait states are a major problem, it may be possible to copy the
interrupt handler code to RAM and run it from there. I’m assuming the internal
RAM has zero wait states, but I might be wrong on that point.‘

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baybal2
Simpler MCUs have real hardwired SRAM access registers.

On more complex systems, even SRAM access goes through some stateful
scheduling circuitry. So, interrupt latency on mainstream MCUs can't be
reduced much.

If you want XIP with adequate latency, there is no alternative to spending
money on Everspin MRAM. You will have accommodate the latency of SPI access,
but that was never an issue in my practice.

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monocasa
There's also parallel versions of MRAM that you can hookup just like SRAM.

~~~
baybal2
Indeed, just the amount of mainstream MCUs with external memory bus connection
is smaller with each year.

