
Intel to Acquire eASIC: Lower Cost ASICs in FPGA Design Time - tpetry
https://www.anandtech.com/show/13075/intel-acquires-easic-lower-cost-asics-in-fpga-design-time
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slivym
This is just bizarre - seems like corporate insanity to me. TO give some
background to this, Intel's PSG is what Intel renamed Altera. Of course Altera
was the FPGA company, and as part of their Stratix III/IV/V range they did
'HardCopy' which, basically was a structured ASIC! They canned it because in
reality whilst customers want to be able to go ASIC in theory, it never really
made much sense in practice. So what? They're buying a company that is doing
something people don't want?

That's what really worries me - because if the acquisition were going into the
group that builds Xeons, basically as an enabling technology for an internal
team that makes sense. But being part of PSG means that they're going to try
and sell this to customers (again).

For investors what you need to watch for is whether what they're really doing
is buying growth. It's a classic move - buy small, similar companies and use
get growth by upselling their product to your existing companies. But once all
the customers have either bought or rejected you're back to brass tacks, the
core business is missing growth/margin targets.

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bgorman
Intel needs more customers for it's fabs.

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mtgx
It can't even fab 10nm chips for its own business.

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voxadam
Most potential fab customers don't want or need 10 nm.

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nickpsecurity
This 2017 survey supports your point:

[http://eecatalog.com/chipdesign/2017/11/26/semiconductor-
ip-...](http://eecatalog.com/chipdesign/2017/11/26/semiconductor-ip-
survey-2017-holds-surprises/)

Most are at 28nm-45nm with some at 55nm-65nm. The things they say they're
concerned about also have some overlap with what eASIC's tech makes easier.
That's on top of the number of companies that might be able to develop a FPGA
but not full ASIC. eASIC's often a cheaper option for companies doing what's
basically a bit faster and lower-power offering.

So, there's definitely potential here for Intel. I hope they realize a good
chunk of it. Who knows if they will.

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pooya13
Article mentions that eASIC replaces SRAM based routing with a scheme that
uses via. What is "via"?

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brandmeyer
If you read up on the structure of an FPGA lookup table (LUT) in detail,
you'll see that most of their size is taken up as memory. A Xilinx 7-series
LUT6 Configurable Logic Block (CLB) is a 64-entry 1-bit sram, read out with a
6-bit address.

If you don't need the ability to reconfigure the system any more, you can
hardwire each of those 64 entries to the VDD and VSS rails instead. Its not
nearly as efficient as the circuits you can get with a set of dedicated logic
cells, but its much more efficient than the baseline FPGA fabric.

If the customer has already validated their logic on FPGA fabric, then its
also much cheaper. You just ask these guys to "burn" it into an ASIC and you
suddenly get a few hundred extra MHz.

Why are they called 'vias'? Because ASIC layout is somewhat similar to PCB
layout - transistors go on one layer, and there are a dozen or so layers of
routing wires below them, with vias in between the layers. So you can replace
the transistors that would have been implementing SRAM cells for read/write
LUTs with vias to power/ground layers instead.

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ksec
McAFee, Infineon, Havok, ZiiLabs ( Or previously more widely known as 3Dlabs
), Altera, Recon Instruments, Mobileye.

Or Name me one thing good that Intel has ever done with their Acquisition.

There is something seriously wrong with Intel.

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baybal2
Imagine a CPLD that is hardwired.

