
A small Lisp-Machine in an FPGA - poindontcare
http://www.aviduratas.de/lisp/lispmfpga/
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e19293001
The verilog code had been poorly written. For example, it's not common for a
combinational circuit to have an input reset. Latches are inferred in some
places that can cause unexpected behavior. That's just my observation though.
It's cool to see projects like this. Sadly, it appears to be inactive after
seeing the project log.

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pryelluw
Could you link to an example?

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gluggymug
There's only one example there.
[http://www.aviduratas.de/lisp/lispmfpga/code.html](http://www.aviduratas.de/lisp/lispmfpga/code.html)

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pryelluw
Thank you.

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krylon
Bonus points for "Wahrscheinlich guckt wieder kein Schwein" \- that triggered
some fond childhood memories. ;-)

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zengid
Another thread with a related subject (and more current projects):

[https://news.ycombinator.com/item?id=8340283](https://news.ycombinator.com/item?id=8340283)

