
Three Generations of Asynchronous Microprocessors (2003) [pdf] - steven741
http://mail.async.caltech.edu/Pubs/PDF/2003_threegen.pdf
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ur-whale
I've always been _fascinated_ by asynchronous hardware design.

When you first learn about H/W design in Verilog or VHDL, it feels like your
mind is immediately shoehorned and molded by both the literature and your
teachers into thinking synchronously (everything has to be clocked, and
signals crossing clock domain boundaries are to be treated like they're some
form electronic nitroglycerin).

As a matter of fact, HDL courses often go without so much as a mention of the
possibility of asynchronous design, or if they mention it, it's to say
something along the lines of "just don't".

It almost feels like designing things asynchronously is a sin to be avoided at
all cost.

Even further, the synthesis tools themselves will yell at you when you try to
do things asynchronously (probably because many of the optimization that can
be done with a clocked design don't work).

Granted: asynchronous design is harder and bug-prone, but - at least to
someone like myself with more of a software engineering background - it also
feels a lot more natural than being forced into the straight jacket of clocks.

This all leads to the unfortunate situation that while there's been a lot
written about how to design with clocks, I haven't come across much literature
about asynchronous design _methodologies_.

If anyone on HN has a a reference on asynchronous hardware design
methodologies, I'd love to dive into that.

~~~
mnw21cam
The major thing with a clock-based design is that you have to dedicate a huge
amount of silicon and power just towards getting a clock signal all over the
whole chip.

A group at Cambridge University also designed and fabricated an asynchronous
CPU based on an early ARM a long time ago now. Like the ones mentioned in this
article, it behaved very well. It would slow down if they pointed a hot air
blower at it.

~~~
moonbug
Not thinking of AMULET from Steve Furber @ University of Manchester?

~~~
mnw21cam
Hmm. It does appear that perhaps when I was wondering around the Cambridge
labs they may have claimed a little more than they should have. Maybe someone
working there was collaborating with the Manchester group.

------
senatorobama
Is there a RISC-V Async CPU?

