
ARM Cortex-A57 Software Optimisation Guide [pdf] - luu
http://infocenter.arm.com/help/topic/com.arm.doc.uan0015a/cortex_a57_software_optimisation_guide_external.pdf
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gshrikant
From page 6,

>> Instructions are first fetched, then decoded into internal micro-operations

Is 'micro-operation' the same as microcode? I'm not familiar with the ARM
Cortex-A architecture but I always thought ARM didn't have microcodes?

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CHY872
ARM does have microcode (though early ones didn't).

Basically if you don't have microcode, you kinda tie your instruction set to
your physical architecture, which makes it hard to progress.

For example, at the time of the Pentium 3, all instructions were 64 bit -
execution units, buses, register renaming tech. SSE had 128 bit vector
instructions, which would screw with this. For this reason, Intel split them
into 2 64 bit micro-instructions.

ARM generally doesn't have _patchable_ microcode, which might be the source of
your confusion?

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zurn
You are confusing the concept of uops (or micro-instructions) with microcode.

Microcode is when the CPU runs microcode from a microcode ROM to implement an
instruction. In CISC days this was often all instructions (these were termed
microcoded CPUs). The same architecture might have cheap microcoded and high
end "hardwired" implementations.

There's a conceptual similarity between uops and microcode, to quote the WP
microcode article: "Modern CISC/RISC implementations, e.g. x86 designs, decode
instructions into dynamically buffered micro-operations with instruction
encodings similar to traditional fixed microcode. Ordinary static microcode is
used as hardware assistance for complex multistep operations such as auto-
repeating instructions and for transcendental functions in the floating point
unit; it is also used for special purpose instructions (such as CPUID) and
internal control and configuration purposes."

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bhouston
Similar table for x86 instructions:

[https://gmplib.org/~tege/x86-timing.pdf](https://gmplib.org/~tege/x86-timing.pdf)

