
Silicon die analysis: inside an op amp with interesting “butterfly” transistors - tubetime
http://www.righto.com/2018/06/silicon-die-analysis-op-amp-with.html
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allegedganon
Ken's reverse engineering articles are always a real pleasure to read, but
this one is special in that it looks at an analog chip and how typical analog
building blocks (current mirrors, differential pairs) are implemented in
silicon.

Also, if you've every looked at an analog IC's schematics and wondered what
those weird "double collectors" BJT are
([https://electronics.stackexchange.com/questions/105777/what-...](https://electronics.stackexchange.com/questions/105777/what-
do-multiple-emitters-collectors-imply-in-a-bjt-schematics-symbol)) , there's a
pretty decent description in there of what a BJT actually looks like when
implemented in silicon.

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raverbashing
Funny, I have actually used this one, the 4 means 4 OPAMPs in a single chip.
IIRC there's also the TL082 with 2 OPAMPs.

Much more performant than the 741 (might have to do with 2 things: the 741
came early and was one of the pioneers and it is BJT only)

It's also curious how the the big butterfly transistors are at the input,
components with a big die size are usually big for a reason (usually power).

One extra fact, the compensation capacitors are more like a wrench on gears
and actually make the circuit "worse" (it lowers the overall bandwidth). But
it is needed for stability purposes because good amplifiers will have a
tendency to oscillate by themselves.

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coupdejarnac
Is there a general purpose op amp that is the modern equivalent of the 741?
Something with a much more recent design with widespread use.

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hatsunearu
What's wrong with the 741?

The 071 is also "jellybean" enough; both are still currently used in modern
designs because how dirt cheap they are.

But they are "high voltage", non rail-to-rail anything, so people tend to use
more modern options for new designs.

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setquk
741 problems: terrible bias current, offset, input range, output range, power
consumption, voltage requirements, GBW, noise.

They’re just horrid. Fine for noddy stuff like power supplies and PID loops
etc though.

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ebikelaw
While you marvel at this circuit remember that it was invented decades ago,
for many purposes it is still state-of-the-art, and it costs fifteen cents.

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jstanley
I sometimes wonder whether integrated-circuit manufacturing wasn't sent to us
by time-travellers from the future. Our ability to manufacture useful things,
on such tiny scales, to such high precision, doesn't seem to match up with our
comparatively-poor capabilities in other areas of manufacturing.

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vvanders
There's a series on transistors that covers this. There's basically no
mechanical process since everything is done via etching and litho. Leads to
the results you see.

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paulmd
Please link it.

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panic
Here's the start of the series:
[https://technicshistory.wordpress.com/2018/01/20/the-
transis...](https://technicshistory.wordpress.com/2018/01/20/the-transistor-
part-1-groping-in-the-dark/)

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bogomipz
I have a few questions about the JFET diagram and JFETs in general if someone
wouldn't mind answering:

In the graphic we see S, G and D - Source Gate and Drain. Is the source
permanently connected to power? If so do all transistor in a circuit connect
to a shared power rail?

Must voltage always be present on both the source and gate in order for
current to flow to the drain?

Lastly when the transistor is switched "on" does voltage leaving the drain
then become input for a gate of some neighboring transistor in the circuit?

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kens
> Is the source permanently connected to power? If so do all transistor in a
> circuit connect to a shared power rail?

Looking at the TL084 schematic, the JFET source is fed from another transistor
(a current source in a current mirror). Some of the transistors are connected
to V++ and some are connected to V-- but many of them are not connected
directly to any power rail.

> Must voltage always be present on both the source and gate in order for
> current to flow to the drain?

There has to be a voltage differential between the source and the drain for
current to flow. JFETs are "normally on" and get pinched off as the voltage
differential between the gate and source increases.

> Lastly when the transistor is switched "on" does voltage leaving the drain
> then become input for a gate of some neighboring transistor in the circuit?

Voltage doesn't really leave the drain, but the drain is connected to the base
of another transistor, part of the second state of the op amp, where most of
the amplification happens. In other words, the output of the differential pair
is the input to the next amplifier stage.

~~~
bogomipz
Thank you for the detailed reply.

Would these last two points also apply to MOSFETs?

In the case of a MOSFET there obviously wouldn't be a "next amplifier stage"
but would the output voltage be input to the next transistor's source or the
next transistor's gate maybe?

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hatsunearu
For MOSFETs the story is about the same.

For the tree transistor horsemen (BJTs, MOSFETs, JFETs), they can all be
fitted into similar transistor amplifier building blocks:

[https://en.wikipedia.org/wiki/Template:Transistor_amplifiers](https://en.wikipedia.org/wiki/Template:Transistor_amplifiers)

You can put these things one after the another to get more complex behavior.

Roughly speaking, common collector/common drain amplifiers have a gain of
approximately 1, but has low output impedance, which makes it suitable for
driving big loads (like the outside world). Common emitter/common source
amplifiers have high output impedance but tons of gain.

The classic op-amp topology is a differential amplifier (long-tailed pair, in
the wikipedia template) feeding into a common emitter/source gain stage, then
into a common collector/drain follower output stage.

To answer your last question, the output of the gain stage is the drain of the
transistor, that feeds the gate of the common drain output stage transistor.

The gate is usually the input terminal, but sometimes the gate is at a fixed
voltage and the drain is the input terminal (cascode-y circuits are like this,
aka common base or common gate).

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bogomipz
Thanks I found the classification in that link quite helpful. Cheers.

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phaet0n
Does anyone have a good reference on how analog is done on logic processes,
specifically the bits that have to interface off the chip, like gpio, lvds,
and serdes. I'd much appreciate it.

There's something I once encountered, but can't find the reference to, that
suggested a kind of "digital-analog" process whereby voltage levels were
replaced by timing measurement (?) due to the limits of feature size in analog
design. I'm not in the field so forgive my ignorance.

~~~
kens
I don't know about modern chips, but 1970s and 1980s logic chips just used big
MOSFETs to drive their outputs. There wasn't any weird timing magic going on.

There are also processes like analog BiCMOS that let you mix bipolar analog
circuitry and CMOS on the same chip. I also wrote recently about the 76477
sound chip that combined I2L logic with bipolar analog circuits.

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phaet0n
Thanks for pointing out your article about the 76477. Fascinating stuff.

As for my second paragraph about "digital-analog", this reference on VCO-based
quantizers [1] is not the one I remember but I think is related. Not that I
really understand the intricacies, but it's a way of doing analog at low-
voltages and finer geometries.

[1]
[http://ewh.ieee.org/r5/central_texas/cas_ssc/meetings/2012/1...](http://ewh.ieee.org/r5/central_texas/cas_ssc/meetings/2012/101112/vco_based_quant_perrott.pdf)

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amelius
Could a genetic algorithm have come up with this design?

(Electronics seems an interesting application area for automated design, since
the search space is relatively small)

~~~
ttul
I modern chip design, simulated annealing is used for placement of parts to
minimize the length of routes and optimize parasitic effects.

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obl
Not my area but I don't think that's the case for the analog ICs, or the
analog part of mixed ICs.

The constraints for generic digital logic soup are comparatively "simple" :
make wires as short and neat as possible and then check the (simulated)
physical timing characteristics.

Analog is more artistic since any noise or crosstalk degrades the signal
irreversibly (for low noise stuff) and any wire is a transmission line (for
high speed stuff).

Actually even for digital I'm sure you still have to do manual layout for the
most critical pieces of high-performance designs (say a register file on a
nvidia gpu).

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ttul
You can still run an analog design through simulation, and feed the results of
simulation into a layout algorithm.

