
Implementing FizzBuzz on an FPGA - jf
http://www.righto.com/2018/03/implementing-fizzbuzz-on-fpga.html
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vvanders
> While this may look like code in a normal programming language, it operates
> entirely differently.

So happy to see this called out up-front. One of the hardest things with FPGAs
as a developer is understanding that you're reconfiguring hardware instead of
a series of serial asm/opcodes. They look superficially the same but have very
different requirements and constraints under the hood.

~~~
xelxebar
> under the hood

Surely, we don't have to work with raw quantum electrodynamics when designing
an FPGA, even though that's what's going on "under the hood".

Thinking that way, gets me wondering about different layers of abstraction
along with the benefits and drawbacks of each. With FPGA programming, what
levels of abstraction are available and what simplifying assumptions does each
model make?

I've got in mind things like Kirchhoff's laws, where we assume perfectly
conducting wires, discrete elements, a conservative ambient B field, and
essentially DC current over the size of circuit elements. When those
assumptions start breaking down, then we can drop down a layer of abstraction.

~~~
vvanders
I think most HDLs are approaching the diminishing returns of abstraction
already. Most of the electrical characteristics are already captured in
routing, setup and hold times so while you may not directly interact with them
anything more than the most trivial design will be constrained by them.

By "under the hood" I was referring to the constraints you have on what you
design. In the software space we are mostly constrained by memory(huge),
network speed(blazing fast), CPU time(tasks running long normally don't break
things).

In FPGA/ASIC land those constraints are much, much smaller(kB vs gB) and there
are many more(thermals, power, hard cycle requirements, etc).

~~~
slededit
> I think most HDLs are approaching the diminishing returns of abstraction
> already.

System Verilog goes a lot of the way, but there are many good abstractions
missing in HDL. Structs were my biggest complaint before System Verilog.

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TomVDB
For those looking for cheap FPGA boards, I highly recommend looking for
something that is based on the Lattice ICE40. The cheapest board you can find
is probably the $9 Upduino, though trickier to get going. (Complete lack of
documentation.)

But there are tons of hobby boards in existence.

The best part is Project IceStorm, a fully open source tool flow, from
synthesis to bitstream. While not the best in terms of optimization, it's
killer feature is that it's blazing fast. You can get small design synthesized
and converted to a place-and-routed bitstream in under a minute.

~~~
katastic
My problem (years ago) was that with Lattice, there just aren't as many
tutorials/easy-EDA and they kind of expect you to know what you're doing.

So if you've never taken a class on FPGA's and learned how netlists work, et
al, Lattice may be a harder time. I ended up buying a cheap Altera afterward
just to learn.

~~~
bri3d
I entirely see where you're coming from, and this has completely changed in
the last 2-3 years. SiliconBlue/Lattice used to be a niche-market low-power
also ran in the FPGA world. Documentation was sparse and most examples from
academia targeted Altera or Xilinx parts.

The open-source toolchain flipped this and allowed Lattice FPGAs to become the
tool of choice for beginners and small-application hobbyists. There's now a
tremendous wealth of resource available around getting started with Lattice
FPGAs. And as the cherry on top, you don't have to wrangle the gigantic
Vivado/Quartus/ISE suites to do so.

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lnsru
Amazing project to learn how FPGAs work. Not overkill with some high speed
interfaces, but touches all problems: no easy division by 3 and 5, counters
everywhere, no copy/paste solutions, no libraries with helpful functions.
Though Xilinx ISE is obsolete, Vivado is the current tool.

~~~
Posibyte
As kens said, and to expand, Xilinx's Vivado doesn't support the Spartan 6,
however they _do_ still fully support the Spartan 6 and continue to produce
new chips. To support this, they've released a Virtualbox compatible image
which runs Oracle Linux with ISE configured specifically to program Spartan 6
FPGAs.[1]

[1]:
[https://www.xilinx.com/support/download/index.html/content/x...](https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/design-
tools.html)

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mrguyorama
The most interesting part of all this is just how CHEAP some of the learning
boards are. I don't know enough to understand how limited the ElbertV2 is, but
at $30, it can still be pretty limited and a fun toy

~~~
leggomylibro
I got a couple of ICESticks I've been meaning to play with a little while ago,
they're only $25 MSRP and have a 'USB stick' form factor.

But it's hard to find and get started with a good open source toolchain. I
have heard good things about IceStorm, but haven't gotten around to setting it
up.

It's great and inspiring to see people successfully stepping through these
sorts of starter projects and documenting them, though!

~~~
gh02t
> But it's hard to find and get started with a good open source toolchain

That's because there aren't any. The one you have happens to be the exception
- it's the only FPGA line with an open source toolchain AFAIK. FPGAs are the
realm of large, heavily proprietary build environments.

~~~
MisterTea
> That's because there aren't any.

Incorrect. See:
[http://www.clifford.at/icestorm/](http://www.clifford.at/icestorm/)

~~~
gh02t
I meant to explicitly say that the Lattice iCE40 is the one exception thanks
to a heroic volunteer effort. I edited a bit to make that clearer.

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sguav
I am pleasantly surprised by this reading!

I have been trained as an EE to consider FPGA design in the hardware skills
domain, and indeed I would say that this writeup ignores the less friendly
parts of FPGA development (timing closure, clock domain crossing and more...).
Nevertheless, I think it is a good introduction for software developers to
start thinking like "hardware description". Good work!

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Cyph0n
Great article! I've also been learning Verilog -- albeit in an academic
setting -- and it has been an interesting experience. I discovered that you
can do surprisingly complex things in Verilog (at least, from a digital logic
point of view) using less code than I initially expected!

~~~
InitialLastName
I would suggest that you be VERY careful with that expressiveness if you want
to do anything in an actual hardware context. Verilog makes it very easy (IME
much easier than VHDL) to create structures that, while technically possible
to synthesize, take enormous amounts of logic resources.

~~~
Cyph0n
The course focuses on synthesizable Verilog for FPGAs, so our instructor has
made sure to clarify the upsides and downsides to using different logic for
common tasks.

Some interesting ones:

* Never use asynchronous resets [on FPGAs]

* if-else if-else chaining leads to unnecessary delays (priority encoders)

* Avoid latches by making sure to assign default values

* Never assume default values and/or states

~~~
eebynight
Your professor seems great so far but pretty silly of him to teach you verilog
instead of VHDL. As an EE myself I haven't seen a job description that says
verilog over vhdl in a long time. Might want to familiarize yourself with both
if you plan to pursue hardware design further.

~~~
TomVDB
VHDL is popular in Europe and the US East Coast. Verilog is king on the West
Coast.

An an EE who was schooled in VHDL, gave VHDL classes to new hires and was
conditioned to look down on Verilog: after moving from Europe to the East
Coast and then the West Coast, I eventually saw the error of my ways and I'm
very happy to not have to deal with VHDL anymore.

And for the open source crowd: there is a much large body of decent quality
open source Verilog tools than there is for VHDL. So as a hobbyist, it's
really a nobrainer.

~~~
monocasa
I always got more of a VHDL for FPGAs and Verilog for chips kind of vibe. Not
that there's anything intrinsic in those languages, just the kinds of
industries that ship FPGAs seem to gravitate to a DoD specified language.

And can you elaborate on what you like about Verilog?

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cesarb
Would it have been better to use a ring counter instead of an adder for the
modulo 3, modulo 5, and state counters?

~~~
JoachimS
Yes, parallel counters would be a simpler solution.

