

The 8085's register file reverse engineered - kens
http://www.righto.com/2013/03/register-file-8085.html

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kragen
Nice post, Ken. I've been appreciating your work since xfractint in 1994 or
so.

Note that in a wired-AND-capable current-mode logic, like open-collector TTL,
you can get a similar RS latch out of a couple of inverters wired into a
Henkin-sentence circuit like this, with the latch inputs being the latch
outputs; but the behavior is slightly different than what Ken documents here.
Here he says that, essentially, the 8085 tolerates bus-fight, but the bus
drivers in the ALU are stronger than the bus drivers in the registers, and so
after a brief bus fight, the register bit flips.

But with the wired-AND approach, bus fight doesn't exist; you just don't hook
up any external zeroes to the Q and /Q lines if you want to read the latch, or
to write it, you assert an external zero on one of them.

The trouble with open-collector logic, as I understand it (I've never built or
debugged an open-collector circuit in my life) is that it's kind of slow. If I
understand Ken's post, the circuit described here is a kind of optimization of
the wired-AND latch I described above: there's a weak positive driver stage to
speed up positive-going edges on the output. Is that right?

It's always interesting to see how real-world circuits depart from the purely
digital, RTL ideal in order to save some resource. Jeri Ellsworth's work
reverse-engineering old chips (which I hope to God is not secret!) found
another example: dynamic stages in pipelines, where rather than using a flip-
flop or even an entire latch, you just rely on the capacitance of an input to
hold the previous value for long enough that the next stage in the pipeline
can do its job. Works as long as you clock it fast enough, fails when you try
to single-step the chip.

(Also, thank God, an actual hacking-related story on Hacker News, as opposed
to "I lost 3lbs and a percent of body fat in a week" or "Every night when my
dad would come home from work he would be filthy from working at the junkyard
all day.")

~~~
kens
Thanks for the detailed comment, Kragen. I didn't think anyone remembered
xfractint :-) I think your analysis is correct, although I'll need to
investigate Henkin-sentence circuits some more

You mention dynamic stages that rely on capacitance - these pass-transistor
circuits are a standard technique, written up in books. The key is the nearly-
infinite input impedance of MOS transistors, which lets the charge hang around
for a while. Interestingly, the Z-80 doesn't use this, so its clock speed can
be reduced down to DC, unlike the 6502, 8085, etc that have a minimum clock
speed as you say.

~~~
mpyne
If Xfractint is the "stone soup" fractal program then I remember. :)

Probably the first program I actually remember was a ratty ol' Mandlebrot
fractal generator in Turbo Pascal 7.0 from probably around 1994-95 or so. Then
I saw programs that were coded by people who actually knew what they were
doing and my head asploded. :)

~~~
kens
The "stone soup" fractal program is Fractint. Xfractint was my port of it to
Unix/X, which was a bit tricky since parts of Fractint were in extremely tight
386 assembler that did crazy stuff like simulating floats with integers for
performance.

------
Breakthrough
And for those who just love seeing silicon dies up and close, you might want
to check out these amazing pictures to really put things into perspective:

[http://zeptobars.ru/en/read/open-microchip-asic-what-
inside-...](http://zeptobars.ru/en/read/open-microchip-asic-what-inside-II-
msp430-pic-z80)

Really cool to see the different designs used in various components, or even
compared to other CPUs/MCUs. The pictures above were taken by dissolving off
the inline package casing with sulfuric acid. No 8085, but there's a picture
of the Z80A available, and you can make out the similar areas to the 8085
(register file, control logic, ALU, etc... the quality is insane, the Z80A
picture is 6200x6000 px). There's also some earlier photos at
[http://zeptobars.ru/en/read/how-to-open-microchip-asic-
what-...](http://zeptobars.ru/en/read/how-to-open-microchip-asic-what-inside)
if you want some more high-res silicon imagery.

~~~
orangethirty
These are great links, thanks.

------
guan
Why is the physical realization of a CPU’s registers called a “file”?

~~~
Breakthrough
It appears to be common nomenclature dating back to the 1960s-70s [1] to refer
to the registers in a CPU as a single "file" in RAM, although the term "file"
denotes the fact that you can access multiple parts of it at once.

From [2]: " _A register file is a critical component of a modern superscalar
processor. It has a large number of entries and read/write ports in order to
enable high levels of instruction parallelism._ "

You might want to think of a register file as "a group of registers with
several (parallel) input/output ports", as opposed to a component which can
only perform a single read/write at a time. Basically, a really fast multi-
channel RAM which can do simultaneous reads/writes. The number of read/write
ports is usually dictated by your hardware, instruction set, parallelism, and
scheduling [3] [4].

\----

[1] Bollesen, V.; , "Core memories," Magnetics, IEEE Transactions on , vol.6,
no.3, pp. 534- 535, Sep 1970

[2] Gonzalez, R.; Cristal, A.; Ortega, D.; Veidenbaum, A.; Valero, M.; , "A
content aware integer register file organization," Computer Architecture,
2004. Proceedings. 31st Annual International Symposium on , vol., no., pp.
314- 324, 19-23 June 2004.

[3] Wallace, S.; Bagherzadeh, N.; , "A scalable register file architecture for
dynamically scheduled processors," Parallel Architectures and Compilation
Techniques, 1996., Proceedings of the 1996 Conference on , vol., no.,
pp.179-184, Oct 1996

[4] Balasubramonian, R.; Dwarkadas, S.; Albonesi, D.H.; , "Reducing the
complexity of the register file in dynamic superscalar processors,"
Microarchitecture, 2001. MICRO-34. Proceedings. 34th ACM/IEEE International
Symposium on , vol., no., pp. 237- 248, 1-5 Dec. 2001

