
TSMC 5-Nanometer Update - rbanffy
https://fuse.wikichip.org/news/2879/tsmc-5-nanometer-update/
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zanny
I wish the industry would move to transistors per mm or something instead of
bongus "nm" numbers that are meaningless - 91 to 171 MTr/mm^2 even sounds more
impressive then whatever 7 to 5 nm means.

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fspeech
It depends on the mix of circuits. Memory don't follow same design rules as
logic so can scale quite well. Logic density may well be limited more by power
dissipation than by design rules. In other words you can pack some circuits a
lot denser than others.

I do agree that it is frustrating for someone from the outside to understand
exactly what kind of scaling one can expect.

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SemiTom
[https://semiengineering.com/5nm-vs-3nm/](https://semiengineering.com/5nm-
vs-3nm/) TSMC’s 5nm technology is 15% faster with 30% lower power than 7nm. A
second version of 5nm, due out next year, is 7% faster. Both versions also
will use EUV.

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car
Seeker released a very insightful feature about the ASML Extreme UV / soft
X-ray (13.5 nanometers) photolithography system that is being referred to in
the article.

[http://youtu.be/f0gMdGrVteI](http://youtu.be/f0gMdGrVteI)

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danharaj
Quick question, what does "ip compatibility" mean between nodes?

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yaakov34
It means that you can produce the same design (IP or intellectual property) on
both processes. The denser process should then result in a better frequency or
power performance without a redesign. Many processes do require a redesign
because of different latency or more redundancy/error checking required and so
on.

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jonplackett
N5s being optimised for high performance computing off from the start (Ratber
than only mobile) look like just the kind of thing an Arm MacBook would use.

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bpye
Or, you know, AMD?

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airesQ
Is it just me or the competition on the CPU market is about to get really
interesting? My understanding is that if Intel loses the edge on fab-tech then
the door is open for all kinds of new entrants. (I could be wrong though.)

Who knows, perhaps even Intel will use TSMC's process at some point.

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axaxs
What makes you think new entrants? Just curious. On the fab side definitely
not... there's really only 3 fabs competing on the bleeding edge side of
things, and it costs way too much to open another. On the 'chip designer' side
maybe, but I'm not sure why Intel's performance affects whether or not someone
jumps in. I basically see a convergence coming, with ARM stuff getting better
performance, and x86 stuff using less power...so there will be an interesting
crossroads of sorts to see which direction things go.

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airesQ
The new entrants would be on the design side. If Intel no longer holds the
keys to best fab-tech in the world then all bets are off.

(I'm assuming that Intel doesn't allow competitors to use their fabs; and that
Intel does indeed have the best fab-tech at the moment; maybe I'm wrong.)

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mng2
Even a fabless semiconductor company (e.g. nVidia, Apple, heck, AMD) needs to
spend hundreds of millions to tape out a leading-edge IC. It's a capital-
intensive business, and would present quite a risky bet for any upstart
competitors. Also, patents.

[https://semiengineering.com/big-trouble-
at-3nm/](https://semiengineering.com/big-trouble-at-3nm/)

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NilsIRL
What does "iso-power" mean?

A quick search didn't bring anything.

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cfallin
That means "same power", in the context of a comparison of some other metric.
So (from the article) "15% higher performance at iso-power" means that for the
same power draw, a chip made with the new process has 15% better performance
(clock speed) than one made with the old process. Likewise for iso-
performance: new chip can get the same perf with less power.

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lettergram
If I’m reading this correctly... the expected soon to be released AMD 7nm
mobile chips (early 2020) will potentially consume 50% less power than their
current generation?

With 5nm further improving that 7nm another 30% reduced power?

If so, we’re talking 25-35% of the current power draw for the same speed in
the next 18-24 months?

I have to be wrong here... I know they use a design which doesn’t get 100% of
the Benefits due to the “chiplet” arch, but still.

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wmf
Maybe not 50% less, but it is definitely more efficient.
[https://www.anandtech.com/show/14605/the-and-
ryzen-3700x-390...](https://www.anandtech.com/show/14605/the-and-
ryzen-3700x-3900x-review-raising-the-bar/19)

(Also, I think a 50% reduction followed by 30% would be 35% of current power
not 15.)

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lettergram
Fair - I’ll edit, I did the math wrong (I was looking at each iteration N7P,
N6, N5, N5P). However, judging from their graph not all paths should be
multiplied.

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lliamander
How is Samsung's 7nm production going? I read that IBM will be using them for
their next gen POWER architecture in a couple years.

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ksec
Depends on who you ask, yield is definitely not as good as TSMC, but Samsung
like to use brute force approach to literally everything so I assume it will
be sorted out soon. The downside to this approach is margin but profits isn't
important to Samsung Foundry ( yet ).

