Essentially pipelining, several years before the RISC movement popularised it? Could the Z80 have been one of the first pipelined single-chip CPUs?
That was a very interesting article. I've tried staring at the Visual6502 chip images for a long time, and although I understand the principles behind how diffusion/polysilicon/metal layers are put together to form transistors, for some reason I feel absolutely lost trying to follow the connections and find the borders between the regions especially when one layer is hidden beneath another.
Even looking at the NOR gate with its layout side-by-side I can't see much beyond the metal layer, despite it being partially transparent. I have no problems with transistor-level schematics, however. Is there some sort of trick to being able to easily read and follow the circuitry in die images and layout-level diagrams? It's like some people can read these and visualise/draw the schematic immediately.
I don't think you can call it a pipeline, they only state that the different parts of the instruction are being decoded in parallel. For instance, which instruction will be executed and the register associated with the operation. There is no instruction pipeline.
After launch, the number of unrecoverable errors (due to multiple bits flipped within the same codeword) was higher than expected. It turned out that someone had swapped some combination of address or data lines, which ended up changing the physical grouping of bits within the codewords. Some of the bits within a logical codeword were so close together that a single event was able flip both of them, causing the error correction to fail.
I felt so clever. Then I remembered that the program in the ROM assumed a particular bit numbering, literally while my board was bubbling away in the ferric chloride. Oops.
Rather than re-design the board, I thought about writing a program to rearrange my binaries, or make a socket adapter for the EEPROM programmer. The socket adapter won out.
In 'Halt and Catch Fire,' one of the characters loads his children's names onto a Speak n Spell's memory. He's portrayed as a very talented engineer, and a lot of the show seems to be pretty true to the tech.
My question is, would this be possible for someone with a lot of patience, experience, and a home workshop at that point, or is it an apocryphal story?
 A last TV season about an early PC startup in the 80s
The second problem is the speech data is stored in a TMS6100 ROM which is kind of a strange chip: the 14-bit address is loaded 4 bits at a time, and then the ROM steps sequentially through memory from there. The point is that you can't reprogram this chip (since it's a ROM), and emulating it with a standard EPROM would be a big pain.
I should point out that I don't have firsthand experience with these chips (apart from using a Speak n Spell years ago). But I happen to have been studying them in detail a couple weeks ago for random reasons.
For more information on this chipset, the datasheets are at http://www.datasheet-pdf.com/datasheet-html/T/M/S/TMS5100_Te... and http://www.ti99.com/exelvision/website/telechargement/tms610...
I just did a search and found someone who hacked new words into a Speak n Spell a couple years ago. But he needed to use a CPLD (like a FPGA) to simulate the ROM, and a Windows LPC encoding program, so this wouldn't have been possible in the 80s. http://furrtek.free.fr/index.php?a=speakandspell&ss=1&i=2
It's gotten me interested in circuit bending again, however.
I wound up writing a C program that took in pristine "Intel HEX" (i.e. from the assembler) and swizzled both the address and data to correct for the board layout. I then spit out corrected Intel HEX. Simple, almost trivial.
Interesting that you were designing single sided PCBs. I certainly wouldn't have wanted to do that layout for anything at all complex. Hopefully you had high volume production to make it pay off.
OTOH, I'm surprised you opted for a socket adapter. Way too much hassle compared to a simple C program.
Many moons ago, I heard a seventh-hand rumor that the guy doing the layout of the Z-80 chip had a nervous breakdown, because of the difficulty of the work.
I have no idea if there was any truth whatsoever to that, but I'm glad to find it's not a Langford Blit thing which maddens those who see it ;-)
I think to connect a memory chip you just don't care and you can swap them as you want (as long as you connect the 8 data pins to 8 data pins in the memory)
For IO you care, of course, or you "just" shuffle all data that you want to write (which is a sure way of making someone go crazy)
Address pins are another matter. The Z80 had a built in static RAM refresh circuit, and there is some schtick about which addresses are refreshed as a group (rows or columns, I forget which). So, rearranging the address bus might result in some nasty surprises. And it might get even more interesting with more modern memory devices, which are way over my head.
On a whim, I got the Howard Sams book on the Z80 while I was in high school, around 1981, and I devoured it.
Furthermore, the high-performance DDR3+ controllers typically hash the data word with the address so that when a repetitive data stream is transmitted it doesn't generate more EMI. (Some controllers also hash with a random seed gaining resilience against chilling the DIMMs of a running machine and reading them out on another machine in search of sensitive data.)
I find it really cool that any time you change the DIMMs in your computer, it essentially has to measure the length of the wires to the ICs on it. (I've found it less cool to have to manipulate timing values to compensate for deviation from PCB design rules, but thankful that it's possible. The fun of board bring-up.) If your BIOS has a "fast boot" option, mostly that means it remembers the wire lengths from last time so it doesn't have to do the measurement again every boot.
But now, sheesh! You need to carefully constrain the PCB CAD program so that all the lines match to within 0.1" or less. And, as you mention, that's just the tip of the design iceberg.
It's no longer possible to layout computers at low cost in a garage. Oh, well. Now hipsters sit around in open offices in SOHO and create silly apps.
Notice the reason why! In fact, I think the idea of a startup producing laptops targeted at developers has been mentioned before here on HN.
I'm in a chatty mood tonight, so I hope you'll excuse my indulgence of another few 'graphs on modern memory bus stuff I think is cool that I had to learn under product ship-date duress: Dynamic Termination.
Remember the high-school physics demonstration of the "reflected wave" where you grab one end of a rope that's tied off at the other end, give it a flick, watch the wave travel from your hand to the knot, then reflect back? Well kind of the same thing happens with voltage level on high speed data signals.
If your high school was fortunate enough in these (or those) fiscally troubled times to afford the equipment, the next demonstration tied off the same rope to some sort of damping spring that absorbed your wave's energy and didn't reflect it back at you. Those springs translate to "termination impedance" in electrical circuits.
So in order to avoid reflections, the address/control/clock lines of the memory bus "fly by" each and every DRAM IC until they reach the end of their path, where they "terminate" via resistors that prevent reflection to a voltage potential (half-way between 1- or 0- value potentials so that it's no more work to drive a 1 that 0 or vice-versa).
The data lines are wired directly from the memory controller to the DRAM chips so the DRAM chips have termination built-in to absorb the energy at the end of the line and prevent reflections.
Except that maybe there's more than one DIMM. DDR3 chips let you command them to connect or disconnect their termination resistors. So when you are accessing the closer-to-the-controller DIMM, the next one that's further out can apply termination. And when addressing the one that's furthest out, you disable on-die termination and rely on the actual resistor on the motherboard at the end of the bus.
My hard-learned lesson: the signals don't so so well when you get confused about which rank of chips are closer and which are further away.
I remember reading about the PCI bus, which I think is the first time I heard of a mainstream digital system requiring serious transmission line design.