I wonder how many of us will immediately try to feed a gate back on itself... (Firefox Hung when Flash came face-to-face with infinity, I had to kill -9 it, so be careful)
Very cool little App. Has a nice feel for a simple little Logic Gate simulator to play with. Would be nice to see it integrated into:
http://www1.idc.ac.il/tecs/
I can't reproduce the problem... it won't let you hook an inverter to itself, but a ring of three inverters works fine (but generates inconsistent output).
agreed. a couple slots for your own black boxing of a component would enable fairly complex ideas to be quickly demonstrated. Could be a great teaching tool.
I'm not sure if it's a bug in this case, but I've used logic simulation software with the same issue and it was considered a "feature". Basically, unconnected nodes of an or-gate are considered HIGH. I suppose it makes more sense when the AND-gate has more inputs.
Confused the hell out of me at the time, especially since I had left the assignment to the last possible minute.
No, that still doesn't make sense to me. The behavior of a logic circuit with unconnected inputs depends on the implementation; in typical CMOS, those floating inputs can do things as wacky as picking up the electrical fields of nearby people. The proper thing to do with floating inputs is to declare them unknown, and for any logic operation which depends on their values to also be unknown. Most logic simulation software I've used or written has worked this way.
1. Instead of a clickable text field that says "Simulation is STOPPED" , use something obviously clickable (obvious even when mouse is not hovering over it), like a button, and make it say "Start Simulation" . Likewise, instead of "Simulation is ACTIVE" , make the button say "Stop Simulation" . [more specific version of thehickmans' suggestion]
2. Make active the default state, i.e. the button says "Stop Simulation" by default. [seconding psyklic's suggestion]
This would be even better if it supported gate delays. If it did, then we could make a ring oscillator by chaining an odd number of NOT gates in a circle, and that would just be so much fun. That sort of simulation is actually easier than it sounds; you just maintain an event queue and add a new event to the queue whenever an input to a gate changes.
it's a clean, visually intuitive simulator - i am using it for a high school class learning logic. thanks for making it available
2 things i wish it had:
1) a way to save the state. sometimes students don't finish a problem in one session and there is no way to save the partially constructed network. and of course there's no easy way for them to give me their finished work.
2) a "T" cable to tie inputs together (for example to make an inverter from a NAND gate. it IS possible to connect both inputs to the same switch but while the result works, it doesn't look the way we usually draw gates with bridged inputs.
Very cool! I recommend just having the simulation always be active (i.e. when I hook up a square wave generator, immediately have it generate a signal).
You can argue that, but to digital circuit designers, switches and clocks are inputs to the system you are designing, and light bulbs and LEDs are outputs of the system. This is going against convention.
That would be an SR flop, which -like the JK one- is taught in academia but hardly (if ever) used in industry. I was referring to the edge-triggered D flop; it can also be built from gates but it should be a primitive element. If the object was to have the minimum number of primitive elements in the library, you'd need only a NAND or a NOR gate.
if a switch is connected to one input of an XOR gate but the other input is left free, the output is low regardless of the switch state. (same if switch is replaced by clock). Other gates (OR for example) work correctly even if one input is left free.
Very cool little App. Has a nice feel for a simple little Logic Gate simulator to play with. Would be nice to see it integrated into: http://www1.idc.ac.il/tecs/