I've seen many approaches to computing in my life - optical, mechanical, hydro, even pneumatic. Classic digital based on CMOS is the most universal with huge range of mature debugging instruments.
CMOS digital is so universal, it even worth to pay magnitudes worse power consumption before find best structure, and then, sure use something less debuggable, but with better consumption.
Unfortunately, I don't have enough data to state, which will be better on power, CMOS or memristor. Just now CMOS is mature COTS tech, but memristor is still few years from COTS.
Cerebras, as I know, based on digital CMOS. Just using some tricks to handle near whole wafer space. BTW, Sir Clive Sinclair tried similar approach to make wafer-scale storage, but unsuccessful.
> it's not really a bus it's just addressed multiple chips on the same wafer
I'm electronics engineer, and even have once baked one chip layer on semiconductor practice, so I'm aware about technologies.
As I said before on Sinclair, few companies tried to make new on semiconductor market, and even some have success.
RAM manufacturers for a long time using approach of make multi-chip on one wafer - most RAM chips actually have 4..6 RAMs in one package, but few of them don't pass tests and disabled by fuses, so appear chips with 2 or 4 RAMs enabled and even with odd number of enabled chips.
Looks like Cerebras use similar to RAM manufacturers approach, just for other niche.
Re: the Von Neumann bottleneck, debuggability, and I guess any form of computation in RAM; https://news.ycombinator.com/item?id=42312971
It seems like memristors have been n years away for quite awhile now; maybe like QC.
Wonder if these would work for spiking neural behavior with electronic transistors:
"Breakthrough in avalanche-based amorphization reduces data storage energy 1e-9" (2024) https://news.ycombinator.com/item?id=42318944
Cerebras WSE is probably the fastest RAM bus, though it's not really a bus it's just addressed multiple chips on the same wafer FWIU.