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The recent generations of Atom CPUs for industrial applications include an in-band ECC controller, which works with non-ECC DDR or LPDDR memory.

Besides the Alder Lake N or Amston Lake CPUs that are branded as the Atom x7000 series, some of the models branded as N CPUs, e.g. N97 and i3-N305 also have a functional IBECC controller, if the computer BIOS provides means to enable it.




But DDR5 has inband ECC by default, so it’s hardly any consolation to be honest.


I stand corrected, DDR5 has on-die, not in-band ECC.




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