Interesting. Difficult to tell how complex the bugs are though. Some of them seem to be just triggered by accessing non-existent CSRs which suggests those chips haven't been very well verified already?
Also:
> Cascade discovered
3 inaccurate performance counter bugs (Perfcnts) in Kronos,
VexRiscv and BOOM (K4, V13, B2). They incur an offset in
the retired instruction counters when written by software.
Also:
> Cascade discovered 3 inaccurate performance counter bugs (Perfcnts) in Kronos, VexRiscv and BOOM (K4, V13, B2). They incur an offset in the retired instruction counters when written by software.
Funnily enough the Sail model had this bug too! https://github.com/riscv/sail-riscv/issues/256