Right. When you are talking cores, this is all fine. A completely valid topic for academic discussion.
When you are talking chips with peripherals and packages and memory configs, it gets a little more muddy.
When the conversation moves from academic to trying to buy a chip and ship a product.
I am aware of a popular chip vendor next year making a three core chip. Core0 the fastest and primary is a RISCV, it will be flanked by two smaller and weaker ARM cortex m0 or m4s.
They’re doing that because they have peripherals established for the ARM and almost none for the RISCV.
When you are talking chips with peripherals and packages and memory configs, it gets a little more muddy.
When the conversation moves from academic to trying to buy a chip and ship a product.
I am aware of a popular chip vendor next year making a three core chip. Core0 the fastest and primary is a RISCV, it will be flanked by two smaller and weaker ARM cortex m0 or m4s.
They’re doing that because they have peripherals established for the ARM and almost none for the RISCV.