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Note that this isn't 'production ready'. Specifically, the reset input on a microcontroller is typically asynchronous. That means it's possible for it to happen 'half way through' a clock cycle, and when that happens, things could end up in an unknown state. Specifically, if it happens half way through a write of SRAM, a garbage address might have garbage data written, effectively meaning that while most of SRAM is maintained across a reset, a few random bytes of it might be written to accidentally during the reset process.

In reality, I have never witnessed this happen on the ATmega 328p used in the common arduinos. They may have undocumented circuitry to prevent it, or perhaps its just vanishingly unlikely.

It isn't vanishingly unlikely. Even without considering low level hardware behavior, any non-atomic write could be interrupted halfway through, leaving invalid data in memory.

I’m probably dumb, but isn’t a possible solution to this to leave a single atomic write for the very last operation after a chain of work that was done, one that flags “there is good data here”?

You would need something that is unlikely to happen from random chance like a valid CRC over the block of data. A flag won't cut it since you can't make any guarantees about data integrity when the system is being torn down mid-write.

Sure, but if we’re talking a 32bit system, a magic number can be your final atomic.

Agreed. If you were talking an 8bit system, you could 32bit CRC your actual data. Even though the CRC would be 32bits and 4 stores, it wouldn’t be “set” until the final atomic write.

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