This seems extremely unlikely to me, do you have a source?
First off, you have the obvious problem of reducing chip power. Even the best CPUs today use ~15W. That's significant.
Secondly, you have the problem of extracting power from ambient air. That's also very very hard - just because something is hot doesn't mean you can extract energy from it. You need a gradient. Your chip will sit close to ambient, maybe even a little higher. I find it hard to believe you will get any power that way.
I'm skeptical that extracting power from ambient RF will scale because there's not that much power _bt design_. Commercial equipment that emits any radiation needs to hit power specs and those regulations are very serious.
These Wiliot tags fit the definition of a computer. They have a 1mhz arm CPU, 2kb RAM, 64kb ROM, GPIO inputs & outputs and sensors. They can harvest cellular RF energy and put out a Bluetooth LE ping that can be read from 20 meters. The specs are quite similar to my first computer, the Apple 2E. They are based on a 40nm process, so imagine a 4nm version or a 400 angstrom version.
We are not going to be using battery-less phones, but these kinds of energy harvesting IOT chips have a lot of interesting future applications. Shoes that give fitness data to your phone? Sunglasses that give you UV alerts? Detergent that gives you a notification when it's low? Egg salad that that texts you when you forget it on the counter? Ketchup that emails you when it's expired? Just some silly examples, but no more silly than half the IOT that's already out there.
There are tons of microcontrollers available today that run on less than mA at 3 V. Sure, they don’t have the power of an M1 but with a bunch of them doing a bunch of lazy computing in the field they can do a lot of sensing and casual computing. Perhaps 60 years from now we will have solved the plastics-in-the-environment problem (and cigarette buts) but be plagued with stray processing power too expensive to clean up and still operating too.
And surely some hacker will be operating a garbage dump as a cryptocurrency mine.
I don't know if there's an easy introduction. But lemme try to make one really quick anyway.
* Transistors themselves are just a hunk of metal, silicon (n-type and p-type) arranged on a platter in a particular way. They are physical objects, and you will do well to remember that. New "shapes" are invented all the time: FinFET, GAA (Gate All Around), and Nanosheets (brought up in this article) are "just" different shapes, with GAA having the best attributes so far.
* The primary difficulty isn't really about "coming up" with a better shape. Everyone knew GAA would have the best attributes compared to others. The question is how do you __MANUFACTURE__ the darn thing. These things are nanometers in size, its not very easy to make these shapes when your shapes are so incredibly tiny.
* Transistors are an analog device, not binary/digital. You need an arrangement of transistors to do something: Diode-logic, Diode-resistor logic, Transistor-transistor logic, nMOS, and other arrangements have existed in the past. But... CMOS is the big winner from the 1970s onwards. As such, understanding how transistors are arranged to make your AND/OR/NAND/Flip flops is kinda important. That being said, I'll skip over the details, aside from saying "CMOS" is the status quo, and has the following characteristics.
* In CMOS-arrangements... when the transistor is "on", you want less resistance. A transistor that offers 0.1 ohms of resistance will be better than one that offers 0.5 ohms of resistance (within the realm of CMOS)
* When the transistor is "off", you want less leakage. The switch will always "leak" some electrons down the wrong path, its the nature of physical object. A transistor that leaks 1-femtoamp is better than a transistor that leaks 5-femtoamps. (temperature dependent: the hotter a transistor is, the more it leaks). Again, CMOS-specific.
* Transistors take a certain amount of time to switch from 0 to 1, largely based off of the gate-capacitance. The lower the capacitance, the faster you can turn the switch on (or off). Being able to go from 0V to 1V in 0.1 nanosecond with 1 femtoamp of electricity... is better than doing the same in 0.2 nanoseconds.
* Note: there is a CMOS specific tradeoff mentioned here. Maybe you can keep the same clockrate (5GHz / 0.2 nanoseconds) but use 1/2 the power (0.5 femtoamps instead of 1 femtoamp). In practice, this relationship is complicated as it varies with voltage, but there's usually a region where 2x the voltage leads to 2x the current and 1/2 the delay (aka 2x the clock rate for 4x power consumption). Or... 1/2 the voltage is 1/2 the current and 2x the delay (aka: 1/2 speed for 1/4th power).
* For CMOS, lower capacitance means faster switching (meaning more GHz), and lower power usage (meaning more power efficiency). Cutting down capacitance requires the "gate" of the transistor to be surrounded with more-and-more metal. When you increase the surface area of an object, you decrease its capacitance (this is a physical law that applies to your hands, feet, desk, etc. etc. Its how your phone knows where your finger is: by the amount of surface area your finger has over the phone's screen. As that surface area changes, your capacitance changes and the phone tracks your finger as it moves).
* Capacitance / surface area applies at nano-scale objects like transistors. So when you made "fins" (aka: FinFET), your capacitance decreased, because "fins" have more surface area than planar (flat) transistors. FinFET became standard like 5 to 10 years ago. To go even further: you need an "even better" shape (where "better" is more surface area). This is called "GAA", gate-all-around, where you surround the gate entirely (physically above, below, and left and right).
* * Photolithography + magic is how these things are physically constructed. So called "Planar" transistors made sense and are relatively simple: you basically shove a bunch of chemicals onto the silicon, and then "reverse take a picture" of it (taking your film, shining light through the film, and then shoving that light through a lens to shrink it down. Like photographs in the 1980s but backwards). Because "planar transistors" are all flat, it was obvious how to make them.
* But how do you _MAKE_ a GAA? Well, no one will tell us. They just show us the pictures of them successfully doing it. The secret sauce is in their magic processes that deposits the bits of metal / silicon / etc. etc. in the correct spots. Photolithography is an innately 2D process: built up layer-by-layer by successive chemicals + light emitted from a film-like substance. They had to make this shape from a bunch of 2D steps (maybe 120+ such steps) played out over the course of 2 or 3 months.
So TL;DR: the name of the game is:
1. Think of a shape with more surface area (less capacitance).
2. Figure out a way how to take ~120+ steps of the photolithography process to actually _make_ that shape in practice. And remember: you're mass producing 10-billion of these per chip, so you wanna make sure whatever process you do is 99.99999% reliable. A single mistake will cause the chip to be worthless.
That's it. Really. All the "better" shapes have more surface area. The "older" shapes were easier to figure out on #2, while the "future" shapes look really hard for #2, but are obviously better from a surface area perspective.
Being pedantic, what matters is the field strength at the gate edge, and effective S term of device.
I remember that surface area of the gate was __very important__, and is the key driver of all of these new and interesting shapes we're seeing. But I seem to have err'd on the reasoning behind that.
baybal2's point about the "strength of the field" seems to be correct. That would mean that surface area would cause the field-effect to turn on faster / stronger?? (aka: lower Ohms / resistance when on, and less energy to reach the on-state)
Well... that's if I'm remembering the physics correctly this time, lol.
EDIT: A FET (field-effect transistor) is the type used in CMOS arrangements. Most people will use BJTs in their undergrad studies, with maybe some FETs.
FET has a gate, source, and drain. The "gate" turns on the source->drain in nMOS (or drain->source in the case of pMOS). The more voltage you put on the gate, the lower the resistance of the source/drain gets.
Its called the "field effect" because the electrical field on the gate (caused by literally shoving electrons into that location), causes a negative-charge to radiate out from the gate. This charge then allows the source/drain (two pins that are nearby) to go from high-resistance (aka: 10kOhms or something) to low-resistance (maybe 0.1 Ohms).
The assertion by bybal2 is that the surface area at the gate is more about the field effect rather than capacitance. Which is... probably correct.