Any chance of the code being released open source? I don't imagine anyone testing a spacecraft in their garage, but at some point, the must arise full-time software historians using automated tools to search through all available history of code. It's very difficult to know what they'll find useful centuries in the future.
The CPU could run 12 MIPS with a 10 MHZ clock while having no pipeline. Rather instructions were bit encoded in a single memory cell so some could be executed in parallel.
Single cycle sub-routine call with zero overhead for return from sub-routine. Two cycle interrupt. (if memory serves me well)
I think you might be remembering the later Seaforth/Greenarrays MISC (minimal instruction set computer) chips (they may have had some similar predecessors) that did that funny encoding. The RTX2010 was more like the Novix and had a 16 bit instruction word. See:
That book has good coverage of the Forth chips of that era. This undergraduate thesis has some later developments:
Related stuff from same site: http://fpgacpu.ca/stack
4.4.4 Architectural features
The NC4016 allows combining nonconflicting sequential operations into the same instruction. For example, a value can be fetched from memory and added to the top stack element using the sequence @ + in a Forth program. These operations can be combined into a single instruction on the NC4016.
An accumulator machine can be thought of as half way between a register/memory machine and a stack machine, where most instructions have an implicit argument (the accumulator) and an explicit argument. This typically means code density somewhere between a stack machine and a register machine, with very little penalty in terms of instruction count. The main downside of an accumulator machine is the accumulator almost always introduces a dependency between adjacent instructions, making performant superscalar implementations more difficult. IIRC, examples of accumulator machines include V8's current internal bytecode and the old Apple II SWEET16 VM.
"CDMS is in charge of controlling the whole Lander operation, including preparations for separation from the orbiter, thermal and power management, as well as separation, descent and touch down. In addition to playing an essential role in controlling the whole landing scenario, CDMS has the following tasks to perform on the comet’s surface: to receive and execute telecommands coming from Earth, to collect and send science and housekeeping information of Lander’s subsystems and scientific experiments to Earth, and to control the sequencing of science operations."
"The Harris RTX2010 processor has been selected for the DPU boards, because it has a very low
power consumption. This space qualified, radiation hardened 16 bit processor has such features that
make it possible to provide the complicated functions that CDMS has to perform. It is a stack based
FORTH oriented processor. All the software components have been written in FORTH language with
its exotic and challenging instruction set. CDMS is a real-time controller and data acquisition system
and it has to process tasks in parallel. Consequently, a pre-emptive, real-time multi-tasking, operating
system has been developed to run application tasks and all the required functions in parallel. All the
parts of CDMS on-board software are specifically developed for this project. Unfortunately, there was
no development environment for this type of processor on the market for creating real-time systems so first of all we had to create our own cross development platform. Our operating system provides
system calls for using all of the hardware components and many features to make the application
tasks more efficient."