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HeapSafe: Securing Unprotected Heaps in RISC-V [pdf] (arxiv.org)
12 points by gbrown_ 29 days ago | hide | past | favorite | 5 comments



Worth pointing out that there is already a proposal making its way through the process: https://github.com/riscv/riscv-j-extension/blob/697ce9c6b1f1...


After SPARC ADI, Phonon, ARM MTE, PAC, now HeapSafe.

The future seems to be C Machines, as the last option to fix the language.


The first sentence in the abstract is wrong. The buzz words here among RISC-V players are still things like AI and machine learning.


You are entirely mistaken. While many people are excited about potential future accelerators and such using RISC-V's extension mechanism, it is very much the case that the RISC-V stuff shipping in volume today is embedded / microcontroller stuff.

This is quite deliberate: RISC-V is on track to follow the same path ARM took, starting with the cost optimized lower capability parts then progressively moving up into performance optimized parts. This is really the only viable strategy, because no one is going to invest the billions and decades it takes to get a new high performance design into a totally unproven ISA.


Waiting for the RISC-V variant of Archimedes and RISC OS.




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