The goal of this project is to provide a better source language that various HDLs can target their compilers at. Currently, every toolchain de facto targets some subset of Verilog as its output language, and expects another tool (the synthesizer, also often proprietary) to map Verilog constructs directly onto silicon features, like multipliers
— and those multipliers get fed to the place & route tools. This approach works, but it's generally brittle, because no two Verilog compilers behave exactly the same (among other reasons) so the contortions needed to map constructs reliably tends to require a lot of trial and error and weird rituals.
e.g. 32-bit floating point is what GPUs are made for, while FPGAs really only handle integers unless you've purchased an expensive one with specialized arithmetic units on chip (e.g. DSP48 slice for Xilinx).