That wasn't my intention, which was to make a simple compiler. Somehow, that got away from me :-/
I suppose if that comes at the cost of a complex compiler I can live with it.
It's sorta like designing your own house. I'm lucky enough to have done it. 20 years on, and it's mostly right. But there are a few maddening mistakes that would be terribly costly to fix.
For example, the garage has 8 feet of headroom. Dammit, I need 10 so I can put a hydraulic lift in. It's really hard working under the car without one. I also should have put in a geothermal heating system, which would have been really cheap when the property was all dug up. I could have saved $$$ in heating bills over the years!
`alias this` in class objects turned out to make no sense. When people have problems with it, I just sigh and say stop using `alias this` in classes.
The x86 machine code format is decently simple to decode. It has a couple of opcode maps (one-byte opcodes, another for a two-byte opcode, and two more for three-byte opcodes. Each opcode needs to note which register bank the r field encodes, which one the r/m field encodes, and which one maps to the first and second argument; and additionally if it uses the ModR/M byte in the first place and the size of the immediate it uses (if any).
There are two complications to this basic scheme. The first is that some prefixes are "mandatory prefixes" (66h/F2h/F3h being the most common) for some instructions as opposed to simple modifications. The second is that some instructions take a ModR/M byte but use the different values of that byte to distinguish instructions. For example, 0FAE esp, [mem] would actually be XSAVE [mem] while 0FAE ebp, [mem] would be XRESTOR [mem].
Personally, I've considered building a kind of "world's worst x86 decoder" where ignoring the latter considerations is actually a feature of the decoder.
If you look at the structure of the encoding you'll see that the 66 prefix, which is traditionally known as the "operand size prefix", is quite sensibly used to select between different register widths, e.g. between the SSE/SSE2 wider (128-bit) registers as opposed to the 64-bit MMX ones for the same instruction.
https://www.sandpile.org/x86/opc_2.htm has a nice summary of this.
Christopher Domas for example used 5 I think when he was fuzzing CPUs.
I recently had a look at ARM64. If you thought decoding x86 was complex... I was seriously expecting something simpler, being a RISC and such, but the instruction encoding is surprisingly complex. They are a fixed length but various fields are packed into each instruction in a pretty nonintuitive way.
| imm[20|10:1|11|19:12] | rd | 1101111 | JAL
Disassembling RISC-V is then quite straightforward because of this feature.
All of the bits being contiguous would just mean that you could just
jump_offset = (((i32)opcode) & 0xFFFFF000) >> 12;
It's got to be saving some muxes on tiny cores by keeping the sign bit and bits 10:5 in the same place, but honestly even that seems like a micro optimization that doesn't have a lot of benefit at the end of the day. I wouldn't think that this single saved mux would have been in a critical path (and the sign bit would have been in the same place regardless).