If anyone is interested in learning about the logical primitives that build up to a computer, and how they're implemented using logic gates, I would deeply recommend the course!
I implemented the course in Logism but unfortunately the simulation is too slow to run Teris!
There are PDFs of each chapter for each project. The icons are (left to right): project, slides, chapter.
1. It seems to only let you save one solution for each level, even though there are two optimization goals. It should let you save one for fewest components and one for fewest NAND gates.
2. It's not really clear how NAND gate counts work in later levels where you're using potentially non-optimal components you've built? Like does it count each one as the number of gates that you used, or the number of gates that is optimal, or what? Someone else told me it was the latter, but it seems like XOR counts as 6 even though there's apparently a way to do it with fewer?
3. Why do some levels give me the message "This is optimal!" while others say "This is the simplest solution!"? What's going on here? What do these messages mean specifically? It's not clear.
All this adds up making attempts at optimization a bit frustrating and as such I just don't really want to play it very far. If you're not worried about optimization it seems fine, but if you are the interface really kind of works against you.
The nand-count is based on how you built the components involved. So optimizing a component will have have cascading effects.
"This is the simplest solution!" means the solution with fewest individual components on the canvas. I realize the text could be clearer.
1. The blue on purple color scheme is a little hard on the eyes. Changing the blue lines and circles to #0f0 green helped a lot. (Green also has strong "on" semantics)
2. My SO and I both had trouble finding the trash can. We both tried to drag components back to the workbench or off of the mat to delete them. A larger trash can icon or just making it red might help.
3. I ran into some z-layering issues (at least on Firefox). Opening a component info bubble from the workbench displays under the mat. Also the "results" popup displays underneath any components that might be on the far side.
Overall great game though! I had a lot of fun with it. Thank you!
Yeah if you see my comment below I think really it should always be explicit both about whether you used the fewest components and (separately) about whether you used the fewest NAND gates. Currently it seems like you sometimes only get told about one or the other...
This is a great game and tbh I think you're just butthurt because you couldn't figure out any of the optimal solutions. Xor is the first one and it sounds like you didn't solve it. (fwiw I haven't figured it out yet either)
1. It does only save one solution for each level but if you can do it in fewer nands, why do you need to keep the fewest components? Most puzzle games like this work this way
2. In later levels it uses your best solution from previous levels. The basic (non-optimal) xor solution has 3 compents with 6 nand. The first time I did half-adder, it told me my solution was 2 components/8 nand (a 2-nand AND plus a 6-nand XOR). After trying for optimal xor again (and failing), solving half-adder shows "2 components used. Mission XOR is not completed, so the total number of gates could not be counted." So it uses YOUR best solutions.
3. I mean it's pretty obvious. optimal == fewest nand, simplest == fewest components. If you optimize for nands, your solution is going to be less simple/more complicated.
I think it's a really great game. You should give it another try
With that said (so you know that I'm not "butthurt" nor do I need to give it another try): I completely agree with all of the feedback Sniffnoy gave and I don't know why you're getting butthurt over someone having feedback like that. Why would you insult someone just because they had comments on it? Are you having a bad day?
It is a great game, nonetheless, though, otherwise I wouldn't have played it as far as I did. I think with some small tweaks and fixes, it could be greater still, however.
I think Sniffoy made some valid points but I don't think they support his premise that "Building circuits is neat, but [...] this has some problems as a game". Sure there are things that could be improved but I don't think they take away from the game. I mean you said you did all of the levels with optimizations and enjoyed it. You didn't let the subpar language stop you from enjoying it. But Sniffoy did. And I guess that rubbed me wrong - he's blaming the game because he got hung up on a couple words.
There's no need to be rude. Insults like this don't add to your argument.
> 1. It does only save one solution for each level but if you can do it in fewer nands, why do you need to keep the fewest components? Most puzzle games like this work this way
Because they're separate optimization goals. I want to hit all of them and have each of them saved. Compare Zachtronics games, as magnostherobot mentions. Also, the ones with fewest components will typically be conceptually clearer.
> 2. In later levels it uses your best solution from previous levels. The basic (non-optimal) xor solution has 3 compents with 6 nand. The first time I did half-adder, it told me my solution was 2 components/8 nand (a 2-nand AND plus a 6-nand XOR). After trying for optimal xor again (and failing), solving half-adder shows "2 components used. Mission XOR is not completed, so the total number of gates could not be counted." So it uses YOUR best solutions.
Thanks for determining this. But it would be better if, you know, the game said this anywhere. None of this is explained.
> 3. I mean it's pretty obvious. optimal == fewest nand, simplest == fewest components. If you optimize for nands, your solution is going to be less simple/more complicated.
I have to disagree that this is "obvious". I'm sure one could figure it out after playing enough, but one shouldn't have to; the messages could easily be made more explicit. And like note that even this isn't exactly a correct description, because if you come up with a solution that minimizes both, it only says "This is optimal!" rather than saying "This is simplest and optimal!". You see the problem?
And honestly I'm just not sure you're correct. Like doing NOR the obvious way, I got a "this is simplest!" message, but did not get a message saying to do it in fewer NAND gates. So what does that mean? Is it optimal or not? If yes it ought to have told me; if no it ought to have given me the message saying it can be done in fewer.
So yes I do think the game is really being badly unclear about this.
It's kind of a learning-first game though so I guess if your goal is to beat the game and get every achievement, yeah you'll be disappointed.
As far as Zachtronics games go, you've been able to save multiple solutions since IIRC Infinifactory, and those games all have two or three optimisation goals.
I think Silicon Zeroes only remembers one solution per puzzle, however in most of its levels its goals are quite closely related.
OCTOPTICOM also only saves one solution per level, but only has one optimisation goal, I believe.
I don't believe your assertion is true; at the least, it is not true in my experience.
On the other hand, my experience with games "like this" are mostly free mobile games or other little browser games. For a paid game I would totally expect to be able to save multiple solutions.
If you use a "select" block (which should really be called "mux") and tie the output to the input, you create a race condition. If the data input is 1, and you change set from 1 to 0, the output can actually glitch to 0 for a very short period of time, which is a big no-no. (If you draw the equivalent circuit out with just nand gates and assume they all have some delay between input and output, you'll see why).
A safer solution would be to cross couple two nand gates into an SR latch , use another two nand gates to control the Set and Reset signals, and an inverter to create NOT(data).
Of course in reality, a latch is usually custom built out of transistors rather than logic gates, but there are some cases where I've used logic-gate-latches to make things easier.
Especially because the d-flipflops found in standard cell libraries are frequently implemented as what amounts to two muxes and some inverters.
For a design that uses latches as stand-alone components the glitch considerations become a lot more important.
I didn't go through the entire game, so its entirely possible that it would not affect this particular "design". But as its far more educational than practical, I think its still worth mentioning.
> Especially because the d-flipflops found in standard cell libraries are frequently implemented as what amounts to two muxes and some inverters.
I'm curious where you've seen that implementation because I've never seen anything like that. Most of what I've seen uses two tri-state inverter latches.
Definitely have seen tgate flip flops. They seem to be less in fashion now though I'm not exactly sure why.
On that topic, digital logic games have been around for a long time: https://en.wikipedia.org/wiki/Rocky%27s_Boots
Also available to play using Flashpoint (https://bluemaxima.org/flashpoint/) if you don't want to try to install flash on your regular browser.
It’s also part of the “ZACH-LIKE” anthology on Steam.
Edit: this continues on with the counter level, where you can use the register but it does not behave like the typical set of edge-triggered flip-flops (or transparent latches) that one would normally use. My best attempt at coming up with an explanation is that it's like two-phase edge-triggered logic.
He has a really great video series where he builds a small computer from scratch on breadboards. Also some other highlights:
Reliable data transmission, more educational: https://www.youtube.com/watch?v=eq5YpKHXJDM
DIY VGA "video card": https://www.youtube.com/watch?v=uqY3FMuMuRo
Super educational, but if you want to get into more embedded hardware hacking, I would say that building a homemade computer like he does is probably not a super exciting place to start. I'd recommend picking up some Teensy 4.0 microcontrollers and build some small hardware projects with the microcontroller before diving into lower-level circuitry.
Can you suggest any resources for FPGAs? What kind of hardware do you intend to implement the Hack CPU on?
It has a USB host port for a keyboard and VGA out for the display. The jury is still out as to whether I can build the entire CPU using nand gates, including the ROM and RAM memory. Doing so will use a lot of the FPGA's resources from calculations I've seen. If that's not possible for the memory, then I plan on using the block RAM that's included on the Xilinx board, but for everything else I plan on following the book's design as close as possible. So far, I am in chapters 1-3 simply porting my solutions in the course's HDL to VHDL, which is relatively straightforward so far. I'm taking my time to make sure I'm doing things "professionally", as I'd like to learn the Xilinx toolchain in my professional work at some point. My experience with FPGAs has been implementing them with LabVIEW, which actually makes learning VHDL somewhat mechanical although a bit frustrating. (If I had an FPGA big enough that's targetable via LabVIEW, I could probably build and test the computer in a day or two aside from the VGA and keyboard.) The combinatorial gates are done now, and I've implemented a DFF and am building things from there. So now I'm learning about clocking and such with VHDL. The most troublesome part I anticipate is what to do about the ROM and RAM memory and the display and keyboard. I'd also like to update the CPU where I can interactively download new code to the CPU from a PC using the assembler and software stack I'm building, which is in F#.
I have several books I am using as reference:
- VHDL By Example by Blaine C. Readler (great first intro to VHDL)
- Digital Design Using Digilent FPGA Boards: VHDL/Vivado Edition by Haskell and Hanna
- Effective Coding with VHDL: Principles and Best Practices by Ricardo Jasinski (I'm using this to sort through the various ways to do things in VHDL and have best practices in my code.)
- VHDL for Logic Synthesis by Andrew Rushton
- FPGA Prototyping by VHDL Examples: Xilinx MicroBlaze MCS SoC by Pong Chu
In the former approach, you won't get anything in a mobile form factor, as your computer would simply be too big. But you might learn more than in the latter approach.
Great game highly recommended
It's worth mentioning that the book is getting a extensively revised (sic) 2nd edition in July 2021.
If it is indeed counting the NANDs used to make the gates I actually used, it'd be useful to have a clear indication of exactly how many NANDs each gate uses so I can chase after a game of NAND Golf.
In any case, this is fun :)
> it'd be useful to have a clear indication of exactly how many NANDs each gate uses
You learned that as part of your first section exercises.
At the end of the day everything is made of NAND gates. That’s what the first section teaches you.
I'd like to see the ability to "unbundle" the composite components. Maybe an intermediate pin in (say) the XOR or half-adder has exactly the signal you need to save a component in a later stage.
This is a great idea, and you are not the first to suggest it. I just haven't gotten around to implement it.
Suggestion: replace the blue button text ("I have completed the level") with something simpler, like "Run", "Check", "Test" or "Go".
I would definitely like to improve the look of the wires.
On a random note, I find it disappointed the tiny of amount of physics material on MOOC sites and such.
(“From Higgs Boson to Hello World” as working title.)
A CMOS game, drawing the various layers that make up transistors, would be interesting to see.