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A Plan 9 C Compiler for RISC-V [video] (youtube.com)
100 points by pmarin 51 days ago | hide | past | favorite | 5 comments



I sure enjoy seeing less popular but well engineered tools reapplied to “modern” problems. Re: 9c and lib9rt being well-suited for constrained bare-metal development, I wonder is this a place where pcc[0] would also thrive?

[0] https://en.wikipedia.org/wiki/Portable_C_Compiler


Where will he put the source since the bell labs site (the default 9fs I think) has been gone for so long?


That's been discussed in 9fans, I think: https://9fans.topicbox.com/groups/9fans


We moved on to 9p.io a loooong time ago.

And 9front has its own hg server and 9p server.


Also, a port to Risc64 using it is on its way: https://9fans.topicbox.com/groups/9fans/Tbe8c3c69c87794db-M2...

Topicbox is having issues for me, so I'm duplicating the contents below:

=================================

Dear 9fans,

I'm forwarding an update from Richard and Geoff about their work porting Plan 9 to RISC-V. I sent a synopsis on twitter; it is included here with more detail:

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Synopsis:

• 32 and 64 bit kernels (and commands) are working under tinyemu

• 64 bit kernel is booting on hardware, still being debugged

• 32 bit kernel is untested on hardware because we don't have access to an RV32 core with MMU

• riscv compiler is available on 9p.io/sources/contrib/miller, and has been added to the inferno distribution on bitbucket.

• tinyemu port will go onto 9p.io/sources/contrib/miller this weekend

• source is still in the experimental development stage. it will be released when ready.

Richard recently gave a talk about his experience porting the Plan 9 C compiler to RISC-V: https://www.youtube.com/watch?v=LHJqdXGb0uc

Description:

TinyEMU has been ported to Plan 9, providing a choice of RV32GC or RV64GC in machine mode, and better diagnostics than hardware provides.

We have 9k kernels running in both modes under tinyemu, but so far using only one CPU. They share quite a bit of non-port source. The RV32 kernel uses Sv32 paging. The RV64 kernel so far uses Sv39 paging, but we expect it to work with Sv48 paging (and beyond) with trivial changes. So far the RV64 kernel resides at physical and virtual 0x80000000, which limits user process size, but we believe it will be straightforward to switch to virtual 0xffffffc080000000.

As described below, the RV32 kernel is not usable on the Polarfire Icicle using the stock firmware and bootloaders. The RV64 kernel is close to working on the Icicle, and on the four main cores, we believe. There have been some surprises with the Icicle: as delivered, it starts OpenSBI as RV64 on all harts (CPUs) and hart 0 (the smaller E51 core) controls the others. OpenSBI on hart 1 starts U-boot, from which we PXE boot the RV64 kernel, which runs in supervisor mode. There is no way back to machine mode, thus no way back to RV32, and there seems to be no way to determine which mode the CPU is in.

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Thanks, -Skip




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