One popular use case is for System-on-Chip (SoC) designs that pair a Processor System (PS) with Programmable Logic (PL); once the PS is running the kernel, the FPGA Manager can be used to program the PL fabric from kernel space.
FPGA Manager has another handy feature for FPGA images that implement new peripherals on buses like SPI, I2C, PCI, AXI, etc. These devices are not "discoverable" in the sense that they are capable of communicating to the kernel what driver must be loaded to support them. So in along with a bitstream, FPGA Manager accepts a device tree overlay which indicates to the kernel what drivers to load for the new resources implemented by the configured FPGA. This causes the kernel to probe the requisite drivers after the FPGA configuration has completed. The FPGA manager can also unload drivers for devices implemented in an FPGA that is being reconfigured.
Unfortunately, in LTS kernels 4.9 and 4.14, while SoC vendors include support for their own PL targets, the FPGA Manager subsystem was written as a singleton; once you've configured e.g, the PL, you can't configure additional peripheral FPGAs.
Can you please explain this? What does it mean exactly? And is it different in versions of the kernel that aren’t the ones you explicitly mention?
On a system with multiple FPGAs, FPGA Manager would fully manage any one of them, as long as it was the first device it probed. The second probe would partially fail after creating nodes on sysfs, and a third probe would crash the kernel.
For that particular system, the upstream vendor hasn't rolled out K4.19 support yet. My initial impression of the FPGA Manager code in 4.19 is that this may be fixed (that an FPGA Manager looks to be allocated per driver instead of one global singleton) but I haven't backported it for testing yet.
I think the interfaces FPGA Manager are well designed, its seems to be adequately expressive for even exotic uses, but I would love to see the implementation mature a bit.
I really don’t understand it.
My understanding is that you can only have a single FPGA.
I've always wanted to play with something like this but FPGAs worth connecting to a PC are $$$.
It's around $300, which might not be cheap, but it's certainly more affordable than other I've seen which are very much out of the range of any hobbyists.
it's still $275, and in addition to lattice tools, it is well supported by the open source trellis/yosys/nextpnr flow:
I guess it depends on your own definition of worth and what’s worthy of a $$$ signifier of expense, but you can get pretty powerful FPGAs for $100-200 these days, and respectable ones that can serve many use cases for under $100.
AWS offers FPGAs for rent  starting at around 1.50 USD/hr -- perfect if you want to dip your toes in without a huge capital expense.
Edit: Or at least the K420T board I found doesn't seem to be supported: https://www.xilinx.com/products/design-tools/vivado/vivado-w...
It’s free and the exercises are very helpful for getting some hands on experience.