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The ratio of HW cost to energy use is different for each computing platform and depends on algorithm etc. For example, it seems Cuckoo Cycle PoW has somewhat higher capex/opex in ASICs because of the heavy memory use.

For photonics the ratio changes significantly due to fundamental physical properties of analog computation, photons vs. electrons and so on.

Anyhow the process of the Si Photonics (and memristors/other analog approaches to AI) maturing to the same degree as digital ASICs will likely be long and gradual so this isn't a practical issue for next decade.




I had high hopes for Cuckoo Cycle PoW, but it turns it cannot be scaled linearly, or even at all predictably. So unless the consensus is to regularly tweak the algorithms pretty heavily, it runs the risk of reaching a situation in the future where the currently immense memory requirements being a piece of cake.


See the long discussion in https://www.grin-forum.org/t/grin-improvement-proposal-1-put...

It will take many years for 1GB of on-chip cache to be common, but when that happens, hopefully commodity computing devices can support somewhat efficient Cuckoo mining...




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