Hacker News new | past | comments | ask | show | jobs | submit login
Ferroelectric RAM (wikipedia.org)
38 points by curtis on Sept 2, 2019 | hide | past | favorite | 27 comments



It's great stuff, but still low capacity and high cost in commercial chips. If you want to play with it, check out TI's MSP430FRxxxx microcontrollers. They have FRAM instead of Flash.

Also, there are 8-pin FRAM chips with the same pinouts as generic QSPI Flash/RAM/etc chips which you can buy today.

Again, it's still low-density and expensive, but that seems to be improving and it's fun to make applications which can re-write nonvolatile data by word rather than by page.


And destructive reads with limited life cycles, assures a steady recurring revenue for TI...


Trillions of cycles isn't that "limited", compared to e.g. Flash.


FRAM is far from trillions of cycles, more close to billions, which still kills it after ~5-7 years of intense use.


No, FRAM really is in the trillions of RW cycles.

https://www.cypress.com/file/209146/download


TI spec for FRAM is 10^10, but in real life you do feel that it's noticeably lower.


TI micros are overpriced anyways. The NXP RTs are way better bang for the buck.


That's more than flash. That's more that an SSD, even, probably.

If you're writing to flash or FeRAM that much it seems to me that You're Doing It Wrong.


Flash, I'd agree. But with FeRAM, if you're reading, you're writing either way.


What microcontroller will see continued and "Intense" use of it's internal flash?

The worst I do to mine is to log sensor data in absence of wifi, that's in the order of bits/minute.


Due to destructive reads, any XIP read ends up in a write. And the most grievous case is when your function code ends up just few bits longer than cache. That means that those few bytes will get hammered, individually, every cycle.

TI's spec for 10^10 endurance is for random writes


Atleast in the µCs that i used that have flash, program code doesn't sit on the same flash as RAM for these precise reasons. Data flash is separate so this shouldn't be an issue.


Well, if you're really concerned about that, most of them do still have small amounts of SRAM where you can put stuff like commonly-run functions and interrupt handlers.


One of the benefits of FRAM is that you can put it through extreme radiation and still have it work afterwards. So you can put it in a medical instrument that undergoes gamma ray sterilization, and it will still not only work but also retain the data.


> One of the benefits of FRAM is that you can put it through extreme radiation and still have it work afterwards.

There are no oxides in the supporting circuitry? [Do you have a link to rad-hard results?]


I only have access to the same public info you would. Here's a technical paper from TI:

http://www.ti.com/lit/wp/sboa154/sboa154.pdf

BTW according to TI's support forum, the MSP430F chips with FRAM are not rated to withstand the high levels of gamma radiation used in medical sterilization.

However, Maxim does have many parts rated for that type of application, with "non-floating gate" NV memories. (Draw your own conclusions about what they are referring to.) https://www.maximintegrated.com/en/app-notes/index.mvp/id/60...

Edit: And of course there are oxides, but you can margin around the assymetric Vt-shift that occurs in the transistors.

Edit 2: At least one part explicitly states in the data sheet that it uses FRAM. https://datasheets.maximintegrated.com/en/ds/DS28E84.pdf


Not too many days ago someone was complaining about how posts about promising new technology always attracts comments warning that lab results aren't the same as commercial products: https://news.ycombinator.com/item?id=20753342. I responded that countless times in the past promising technologies had passed by without leaving a mark. Ferroelectric RAM could be the poster child for that effect - it's been around for decades but still hasn't made an impact.


we make a lot of use of FRAM in our embedded systems. It's great stuff. With huge amount of write cycles it simplifies the data structures you need to store compared to page based / lowish write cycle memories.


“FeRAM's advantages over Flash include: lower power usage, faster write performance and a much greater maximum read/write endurance (about 10^10 to 10^14 cycles).”

This sound impressive until you get to the part where reads are destructive, and reads heavily outweigh writes in most workloads. Sounds like a pretty significant disadvantage.


That's really not a problem just as it's not a problem in normal RAM. With increased speed and endurance it's a doddle to write back a value after reading with your memory controller even if you're not putting in dedicated refresh hardware. It's really all about density and cost.


Unless you lose power in the interim. Flash doesn't have that problem, and normal RAM has it so badly that we rely on Flash to store permanent data and only use DRAM as an ephemeral cache.


Surely you could use a capacitor to buffer enough power to complete the rewrite in the event of an external power failure.


The first datasheet I found for a Cypress FRAM chip gives a required power down rate of at most 30us/V which allows it to continue to provide normal operation protecting data. It's a very easy limitation to live with and engineers often deal with far more difficult problems in unexpected power loss than this.


Yeah, that doesn't sound that bad. Sounds like the kind of thing that often has subtle bugs in the implementation, though.


Because dram loses its memory when powered off not because there's some issue with how refresh works. Needing to refresh memory after a read is hardly any engineering challenge. We've been dealing with it since memory's inception.


Right, obviously.


Fun fact: Sonic 3 for Sega Megadrive/Genesis used FeRAM as save RAM. Generally, a Ramtron FM1208S-200CC. I think a few other carts of theirs used it, I've seen 32X Virtua Racing carts with Ramtron FeRAM parts.




Guidelines | FAQ | Lists | API | Security | Legal | Apply to YC | Contact

Search: