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Nikkei Article from December 2016 mentioning 0.8 micron, while aiming for 0.35 micron in 2018. So that's it, i guess?

[1] https://asia.nikkei.com/Business/Biotechnology/Minimal-fab-t...

According to wikipedia the following CPUs were built with that:

[2] https://en.wikipedia.org/wiki/350_nanometer

Which i think of as more than sufficient to finally being able to implement something like SCED, WAM, CHERI, Applecore, whatever in whichever way one is able to wrap his brains around it. Asynchronous, fully static?

https://en.wikipedia.org/wiki/Mead_%26_Conway_revolution (with MEMS(for sensing)) from scratch?

I want it all! I want it NOW!

That's cool, but your [1] seems to say that the machine uses a wafer 12.5 mm in diameter, which is is probably less area than any of the CPUs in your [2].

Should suffice for my needs, see for example here

[1] https://en.wikipedia.org/wiki/R4200

under R4300i which mentions 45mm² for the die.

Also mentioned here [2] https://bits-chips.nl/artikel/small-series-of-chips-profitab...

are 0.25-micron to be released this year, with 190nm and smaller on the roadmap.

Which leads us to [3] https://en.wikipedia.org/wiki/250_nanometer at least.

Maybe not comparable in die size for all the chips mentioned there, i don't care so much, because i don't want to clone or emulate them. I want to go simpler. Rebranch from the 70ies so to speak, to take all the roads not taken since then. Just to see what's there :-)

That's 122mm², which is larger than some Pentium II dies, so if you're okay with designing to a circular die[0], you could fit a Pentium II-grade CPU on each wafer.

0: The main reason to use a rectangular die is that they tesselate better to fit many dies per wafer.

I wonder how this performs relative to something like HardCopy.

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