What is missing of course is what their feature sizes are and the part at the end where you cut the die and package it. It is those things that would define the set of things you could put on a single chip.
under "E-Beam" for 0.25-micron node and roadmap.
So your 12.5mm wafer can have a 8.8 x 8.8 mm square inside of it, or 78.125 mm^2. If I did the math right that is on the order of 156M transistors given a 4t ram cell that is about 39 million bits of RAM. So basically a pretty useful amount of space for "jelly bean" type applications. A synchronized fab line with a median processing time of 1 minute can produce 60 dice per hour. Assuming a physical plant cost of $8M US (that is "several million Euros + the office space to hold it) and a depreciation cycle of 12 years that is about $500 / day for the machinery we can add another $500 / day for staff + electricity, figuring 8 hour days, that's $125/hour to operate for 60 chips is a bit more than $2/dice.
Well the pencil math works (with all of those assumptions) but even assuming its off by an order of magnitude, $20/dice isn't a deal breaker for your own custom chip that does your special thing. You'll also notice that the 50 weeks a year 40 hours a week assumption. I'm guessing you can get better utilization than that which would offset your depreciation costs.
Mentioned are workflows, used tools, intendend audience and goals,
estimated prices, nda-freeness of spice models and design rule check, open source, open-cores, github, and so on.
If they really make this widely available, then my mind is blown...