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This paper was mentioned in the RISC Is Fundamentally Unscalable post but with respect to VLIW.

  The problem is that this is really fucking hard to
  compile, and that’s what Intel screwed up. Intel
  assumed that compilers in 2001 could extract the
  instruction-level parallelism necessary to make
  VLIW work, but in reality we’ve only very recently
  figured out how to reliably do that.
The ReVec article/repo doesn't mention VLIW as an application but I can see parallels in the problem. If you compile for an 8-wide vector processor and you get a 16-wide machine, you need to re-vectorize your code to take advantage of the newly available width. That's similar if you change widen a VLIW. Similar, not same. It seems an obvious possible application but the authors didn't mention it.

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