In my totally non-expert option, no, it will not slow down RISC-V.
The RISC-V instruction set family does benefit from the decades of research since MIPS was first created.
Also, a lot depends on the ecosystem surrounding whatever MIPS cores are available. Memory crossbars, interrupt handling, etc. There's a lot that goes into a system-on-chip.
The RISC-V instruction set family does benefit from the decades of research since MIPS was first created.
Also, a lot depends on the ecosystem surrounding whatever MIPS cores are available. Memory crossbars, interrupt handling, etc. There's a lot that goes into a system-on-chip.